JPH09214476A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the semiconductor integrated circuit in which the effect due to fluctuation in an offset delay time of a delay time variable circuit caused by dispersion in transistor characteristics is small in the case of applying from a signal generating source to a prescribed point and controlling the delay time at the prescribed point with the delay time variable circuit. SOLUTION: A signal delaying a 1st signal fed from a signal generating source by a prescribed time fixedly is used for a reference signal S2 the 1st signal passing through a delay time variable circuit 802 is used for a 1st comparison signal S3 and the 1st signal passing through the delay time variable circuit 802, a 1st series circuit SC1, and a 2nd series circuit SC2 is used for a 2nd comparison signal S6, and the delay time variable circuit 802 is controlled by a control signal S101 obtained by phase comparison between the reference signal S2 and the 1st comparison signal S3 and the 2nd comparison signal S6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to clock distribution in a synchronous semiconductor integrated circuit, and more specifically, to a clock skew generated in wiring in an LSI by a delay time variable circuit, a phase comparator, and a control circuit, The present invention relates to a semiconductor integrated circuit that reduces the clock skew generated in the wiring between them.

[0002]

2. Description of the Related Art In recent years, various processors have been actively developed, and a processor of an operating frequency of 100 MHz or more has appeared. With such an increase in speed of LSI, the key to synchronous LSI design is to become a key. It is a timing design.
In order to easily achieve high-speed operation and normal operation, it is necessary to make the clocks, which are reference signals for operation, reach the registers of the LSI in the synchronous LSI as much as possible.

However, in reality, the chip area increases,
The clock skew increases due to the increase in the number of transistors and the increase in wiring length due to high integration.
The operation speed of the synchronous LSI is reduced and malfunction occurs. Here, the clock skew is a difference in time when the clock signal reaches each register.

Therefore, in order to reduce the clock skew, various clock distribution methods have been proposed. These clock distribution methods can be roughly divided into layout-based approaches such as equidistant wiring from the clock generation source to the clock supply point. As a method of suppressing clock skew, a batch drive method, a balance tree method, and a method of using both of them are known.

The batch drive system is a system in which a wide main line and each branch line drawn from the wide main line are driven by one driver, and a clock is supplied to all registers inside the LSI without a buffer in the middle. . On the other hand, the balanced tree method is a method of supplying a clock to each register inside the LSI via a plurality of stages of buffers by a tree-shaped wiring in consideration of the balance of branch destinations. Although these methods are effective in reducing clock skew,
It is difficult to cancel the delay from the clock source to the clock supply point.

On the other hand, a method is known in which a delay circuit is used to cancel the wiring delay time, and as a result, the clock skew is reduced. In the following, the case where the wiring delay time is canceled by the delay time variable circuit when the external clock signal is distributed will be taken as an example.

FIG. 5 is a diagram showing a conventional semiconductor integrated circuit LSI3 which realizes a clock distribution method for canceling the wiring delay time.

In the semiconductor integrated circuit LSI3 shown in FIG. 5, the external clock signal CK of the clock signal S5 is the buffer 901, the delay time variable circuit 802, and the buffer 902.
And a signal that has passed through the wiring 951 and the buffer 903, and this clock signal S5 is sent to the buffer 904.
The clock signal S5 is distributed at the output terminal of the buffer 904. A signal after the clock signal S5 has passed through the buffer 905, the wiring 952, and the buffer 906 is the comparison signal S6 of the phase comparison circuit 822. Further, the external clock signal CK becomes the reference signal S2 via the buffer 901 and the delay time circuit 801, and this reference signal S2 is input to the phase comparison circuit 822.

Here, the electric lengths of the wirings 951 and 952 are the same, and the delay time variable circuit 802 and the buffer 90 are
2, 906, delay time circuit 801, phase comparison circuit 822
Exists near the external clock signal supply source, and the length of the wiring connecting them is negligible. Further, the buffers 903, 904, and 905 are arranged close to each other, and the length of the wiring connecting them can be ignored.

The fixed delay time of the delay time circuit 801 is Δt.
_{When const1} is set, the control signal A of the delay time variable circuit 802
_The delay time Δt _vdl for _{1 to} A ₅ is expressed, for example, by the following expression (1).

[0011]

[Equation 1] However, Δt _const2 is an offset delay time, and
t _res corresponds to the time resolution.

Delay time variable circuit 802 to buffer 90
Assuming that the delay time to the input signal S5 of No. 4 is Δt ₀ , the lengths of the wirings 951 and 952 are the same, and therefore the delay time from the output of the delay time variable circuit 802 to the input signal S6 of the phase comparison circuit 822 is 2Δt ₀ . Then, the phase comparison circuit 822 compares the signals S2 and S6, operates the control circuit 840 by the output signal of the phase comparison circuit 822, and based on the output signal S100 of the control circuit 840, changes the phases of the signals S2 and S6. If the delay time in the delay time variable circuit 802 is adjusted so as to match, the signals S2 and S2 within the range of the time resolution of the delay time variable circuit 802.
The phases of 6 and 6 are the same. In this case, the delay time variable circuit 8
02 is 2Δt ₀ + Δt _const2- Δt compared to the initial value.
_The delay time is reduced by _const1 .

Here, in order to equalize the initial value Δt _const2 of the delay time of the delay time variable circuit 802 and the fixed delay time Δt _const1 of the delay time circuit 801, the delay time variable circuit 802 and the delay time circuit 801 are _arranged. Use the same circuit.
However, in the delay time circuit 801, a fixed delay Δt
_The control signal is fixed to _{add const1} . Therefore, Δt _{const2 −Δt const1} are canceled.

In order to match the phases of the signals S2 and S5, the delay time variable circuit 802 is changed by Δt ₀ from this state.
The delay time of 1 may be increased. Here, since the delay characteristic of the delay time variable circuit is linear with respect to the control signal value as defined by the equation (1), the control signal value is halved.
By doing so, the delay time of the delay time variable circuit 802 can be increased by Δt ₀ . The arithmetic operation of these control signals is executed by the control circuit 840.

As described above, the arrival time of the signal S5 does not depend on the electrical length of the wiring 951 and can be matched with the phase of the signal S2 within the range of the time resolution of the delay time variable circuit 802.

However, considering the variation of the transistor, the offset delay time Δ of the delay time variable circuit 802 is changed.
t _const2 and the fixed delay time Δt of the delay time circuit 801
_Does not necessarily match _const1 .

For example, if Δt _res is 100 ps, the delay times Δt _const1 and Δt _const2 are 3.1 ns or more in principle, and usually about 6 ns.
When the delay times Δt _const1 and Δt _const2 are about 6 ns, if the delay time fluctuates by 2% due to variations in transistor characteristics, 120 ps.
Delay difference occurs.

[0018]

SUMMARY OF THE INVENTION In the present invention, when a signal supplied from a signal generation source is supplied to a predetermined point and the delay time at the predetermined point is controlled by a delay time variable circuit, it occurs due to variations in transistor characteristics. It is an object of the present invention to provide a semiconductor integrated circuit that is less affected by fluctuations in the offset delay time of the delay time variable circuit.

[0019]

According to the present invention, a first signal sent from a signal generating source is fixedly delayed by a predetermined time as a reference signal, and a first signal passed through a delay time variable circuit is used. A signal that has passed through the delay time variable circuit, the first series circuit in which the buffer and the wiring are connected in series, and the second series circuit similar to the first series circuit, using the signal as the first comparison signal. 1 signal as the second comparison signal, the delay time variable circuit is controlled by the control signal according to the result of the phase comparison of the reference signal with the first comparison signal and the second comparison signal, The control signal when the phase difference from the comparison signal of 0 becomes 0 is the first control signal value.
The value obtained by dividing the value obtained by adding the first control signal value and the second control signal value by 2 is the control signal when the phase difference from the comparison signal of 0 becomes 0. The control signal is supplied to the delay time variable circuit.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing a semiconductor integrated circuit LSI1 which is an embodiment of the present invention.
It is a circuit diagram which shows the phase correction of the clock signal CK.

The semiconductor integrated circuit LSI1 is a circuit for aligning the phase of the signal S5 at a specific position with the reference signal S2 which is the output signal of the delay time circuit 801. That is, in the semiconductor integrated circuit LSI1, the delay time circuit 801 fixedly delays the first signal S1 sent from the signal generation source by a predetermined time, and this delayed signal is used as the reference signal S2, and the delay time variable circuit is used. 802, a first series circuit SC1 in which the buffers 902 and 903 and the metal wiring 951 are connected in series,
Buffers 905 and 9 similar to those of the first series circuit SC1
06 and the metal wiring 952 are connected in series to the second series circuit SC2, the first signal S1 passes through the second signal.
Of the reference signal S2 and the first comparison signal S3, and the first phase comparison circuit 821 uses the reference signal S2 and the first comparison signal S3 as the first comparison signal S6. Phase comparison is performed, and the control circuit 841 outputs a control signal S101 according to the phase comparison result, and the delay time variable circuit 802 is controlled by the control signal S101.
As a result, the phase difference between the reference signal S2 and the comparison signal S3 is 0.
The value of the control signal S101 at this time is set as the first control signal value, and then the phase comparison circuit 822 performs phase comparison between the reference signal S2 and the second comparison signal S6. , The control circuit 841 outputs the control signal S101,
The delay time variable circuit 802 is controlled by the control signal S101.
And, as a result, the reference signal S2 and the second comparison signal S
The value of the control signal S101 when the phase difference from 6 becomes 0 is set as the second control signal value, and then the value obtained by adding the first control signal value and the second control signal value is calculated. The value divided by 2 is used as the third control signal value, and this third control signal value is supplied to the delay time variable circuit 802.

Next, the semiconductor integrated circuit LSI1 will be specifically described.

The clock signal CK is input to the buffer 901, and the output signal S1 of the buffer 901 is applied to the delay time circuit 801 and the delay time variable circuit 802 near the buffer 901.

Output signal S3 of delay time variable circuit 802
Is a buffer 90 near the delay time variable circuit 802.
2 and the first phase comparison circuit 821. The output signal of the delay time variable circuit 802 is the first phase comparison circuit 8
21 becomes the comparison signal S3.

The output terminal of the buffer 902 is connected to the buffer 903 through the metal wiring 951 (electrical length is l ₁ ) in the semiconductor integrated circuit LSI1, and the output signal S5 of the buffer 903 is connected to the buffer 904 in the vicinity thereof. 905 is applied. The output terminal of the buffer 905 is connected to the buffer 906 near the phase comparison circuit 822 near the delay time circuit 801 through the metal wiring 952 (electrical length l ₁ ) in the semiconductor integrated circuit. The output signal of the buffer 906 becomes the comparison signal S6 of the second phase comparison circuit 822 and is applied to the second phase comparison circuit 822.

The delay time variable circuit 802 is a circuit which can variably set the delay time from the input signal to the output signal by a 5-bit control signal. Although the delay time of the delay time circuit 801 is a fixed time, it needs to be shorter than the maximum delay time of the delay time variable circuit 802. The output signal of the delay time circuit 801 is the reference signal S2 of the phase comparison circuits 822 and 821.

The first phase comparison circuit 821 calculates the phase of the first comparison signal S3 which has passed through the delay time variable circuit 802.
This is a circuit for comparing with the phase of the reference signal S2. Reference signal S
When the phase of the first comparison signal S3 is delayed with respect to 2, the output signal UP1 of the first phase comparison circuit 821 is maintained during the period from the rising edge of the reference signal S2 to the rising edge of the first comparison signal S3. When the phase of the first comparison signal S3 advances with respect to the reference signal S2, on the contrary, when the phase of the first comparison signal S3 rises from the rising edge of the first comparison signal S3 to the first rising edge of the reference signal S2, The output signal DOWN1 of the phase comparison circuit 821 becomes low, and in other cases, the output signal UP1 of the first phase comparison circuit 821,
Both output signals DOWN1 go high.

The second phase comparison circuit 822 includes a delay time variable circuit 802 and buffers 902, 903, 905 and 90.
6, the second comparison signal S6 via the wirings 951 and 952
Of the reference signal S2.
When the phase of the second comparison signal S6 is delayed with respect to the reference signal S2, the output signal of the second phase comparison circuit 822 during the period from the rising edge of the reference signal S2 to the rising edge of the second comparison signal S6. When UP2 becomes low and the phase of the comparison signal S6 leads the reference signal S2, on the contrary, during the period from the rising edge of the second comparison signal S6 to the rising edge of the reference signal S2, the second phase The output signal DOWN2 of the comparator circuit 822 goes low, and otherwise the output signal U of the second phase comparator circuit 822.
Both P2 and output-go DOWN2 go high.

The output signal S2 of the delay time circuit 801 is applied to the phase comparison circuits 822 and 821 located in the vicinity thereof, and becomes the reference signal of the phase comparison circuits 822 and 821. Further, the output signal S2 of the delay time circuit 801 is
It is also applied to 41.

Output signal UP of the second phase comparison circuit 822
2. Output signal DOWN2 and first phase comparison circuit 821
Output signal UP1 and output signal DOWN1 are input to the control circuit 841, and the output signal UP1 and output signal DOWN1 of the first phase comparison circuit 821 and the output signal UP2 and output signal DOWN2 of the second phase comparison circuit 822 are input. Based on the above, the control circuit 841 generates a 5-bit control signal S101, which is a delay time variable circuit 80.
2 is applied.

When the 5-bit control signal of the delay time variable circuit 802 is A ₁ , A ₂ , A ₃ , A ₄ , and A ₅ and the delay time is Δt _vdl , the delay time variable circuit 802 outputs a control signal S101. The delay time characteristic is a linear delay time characteristic as shown in Expression (1).

FIG. 2 is a diagram showing a specific example of the control circuit 841 in the semiconductor integrated circuit LSI1.

In FIG. 2, the counter 721 is a 3-bit up counter, and after being initialized by the signal XSTART, the inverter 711 and the NOR circuit 712 logically operate the values of the output signal UP1 and the output signal DOWN1, The counter 721 counts up based on the signal 51 which is the result of this calculation.

During 10 cycles of the reference signal S2, the comparator 731 detects that the least significant bit (LSB) signal 53 of the output signal 52 of the counter 721 does not change continuously, and at this time, the comparator 731 outputs The output signal 54 goes high. In the state where the comparator 731 is initialized by the signal XSTART, the output signal 54 of the comparator 731 is low. Note that once the output signal 54 of the comparator 731 goes high, the output of the comparator 731 does not change unless it is initialized by the signal XSTART. When the output signal 54 of the comparator 731 makes a transition from low to high, the output signal 52 of the counter 721 is captured in the register 741.

The counter 722 is a 5-bit up counter, and after being initialized by the signal 54, the inverter 713 and the NOR circuit 714 logically operate the values of the output signal UP2 and the output signal DOWN2, and the comparator 731. After the output signal 54 of 1 transitions from low to high, the counter 722 counts up based on the signal 56 which is the result of this calculation.

During the 10 cycles of the reference signal S2, the comparator 732 detects that the least significant bit (LSB) signal 58 of the output signal 52 of the counter 722 does not continuously change, and at this time, the comparator 732 outputs the same signal. The output signal S103 goes high. When the comparator 732 is initialized by the signal 54, the output signal S103 of the comparator 732 is low. The output signal S103 of the comparator 732 is once
When high, unless initialized by signal 54,
The output of the comparator 732 does not change. When the output signal S103 of the comparator 732 changes from low to high, the adder 7
The output signal 60 of 51 is captured in the register 742.

The adder 751 outputs 3 bits, which is the output signal 55 of the register 741, and the output signal 5 of the counter 722.
7 and 5 bits are added, and the upper 5 bits are signal 60
Is output.

In the selector 761, the output signal 54 of the comparator 731 is low, and the output signal S1 of the comparator 732 is low.
Output signal 5 of counter 721 when 03 is low
2 to select the output signal 54 of the comparator 731.
Is high and the output signal of the comparator 732 is S103.
Is low, the output signal 57 of the counter 722 is selected, and the output of the register 742 is output when the output signal 54 of the comparator 731 is high and the output signal S103 of the comparator 732 is high. The signal 61 is selected, and the selected 5-bit signal is output as the control signal S101.

Next, the operation of the above embodiment will be described.

The operation in the above embodiment is performed in the first stage (stage in which the phases of the reference signal S2 and the first comparison signal S3 are aligned) and in the second stage (reference signal S2 and the second comparison signal S6).
And the third step (buffer 903).
Of aligning the phases of the output signal S5 of S1 and the reference signal S2)
And divided into

In the first stage, when the first phase comparison circuit 821 compares the reference signal S2 with the first comparison signal S3, in the initial state, the delay time of the delay time circuit 801 is the delay time variable circuit 802. Since it is shorter than the delay time of
The phase of the first comparison signal S3 lags behind the reference signal S2.

As described above, when the phase of the first comparison signal S3 lags the reference signal S2, the period from the rising edge of the reference signal S2 to the rising edge of the first comparison signal S3, The output signal UP1 of the 1 phase comparison circuit 821 becomes low. Therefore, in this case, the output signals UP1 and D of the first phase comparison circuit 821 are output.
Based on OWN1, output signal S10 of control circuit 841
1 changes from the initial state [00000] by +1, that is, changes to [00001], reduces the delay time in the delay time variable circuit 802 by Δt _res , and
The delay time of the comparison signal S3 is reduced by Δt _res .

In response to the result of the reduction of the delay time of the first comparison signal S3 as described above, the first phase comparison circuit 821 again performs the phase comparison between the reference signal S2 and the first comparison signal S3, and still the same. If the phase difference is detected, in the same way as above,
The output signal S101 of the control circuit 841 is incremented by 1, the delay time in the delay time varying circuit 802 is reduced by Δt _{res, and the} delay time of the first comparison signal S3 is reduced by Δt _res .

By repeating these operations, the first phase comparison circuit 821 finally makes the reference signal S2
The phase difference between the first comparison signal S3 and the first comparison signal S3 cannot be detected.
Therefore, the output signal 52 of the counter 721 in the control circuit 841 does not change. As a result, the first stage is completed and the phases of the reference signal S2 and the first comparison signal S3 are aligned.

As the second stage, the reference signal S2 of 10
During the cycle, unless the output signal 52 of the counter 721 continuously changes, the reference signal S2 and the first comparison signal S3
Therefore, the phase of the reference signal S2 and the phase of the second comparison signal S6 are aligned.

The first phase comparison circuit 821 outputs the reference signal S2.
And the first comparison signal S3 are compared with each other to complete the first stage, the wirings 951 and 952, the buffer 90
Due to the delays of 2, 903, 905, and 906, the phase of the second comparison signal S6 is delayed with respect to the reference signal S2.

Here, as described above, when the phase of the second comparison signal S6 is delayed with respect to the reference signal S2, during the period from the rising edge of the reference signal S2 to the rising edge of the second comparison signal S6, The output signal UP2 of the second phase comparison circuit 822 becomes low. Therefore, based on the output signal UP2 and the output signal DOWN2 of the second phase comparison circuit 822, the output signal S101 of the control circuit 841 is
The state is changed by +1 from the completed state, and the delay time by the delay time variable circuit 802 is reduced by Δt _res .
In response to this result, the reference signal S2 and the second comparison signal S6
The second phase comparison circuit 822 again performs the phase comparison with
If the phase difference is detected, the control circuit 8
The output signal S101 of 41 is incremented by 1.

By repeating the above operation, the second phase comparison circuit 822 cannot finally detect the phase difference between the reference signal S2 and the second comparison signal S6. Therefore, the output signal 57 of the counter 722 in the control circuit 841 does not change. As a result, the second stage is completed and the phases of the reference signal S2 and the second comparison signal S6 are aligned.

As the third step, the reference signal S2 of 10
During the cycle, unless the output signal 57 of the counter 722 changes continuously, the reference signal S2 and the second comparison signal S6.
Therefore, the control circuit 841 performs a logical operation for aligning the phases of the reference signal S2 and the comparison signal S5. This makes the buffer 90
The output signal S5 of No. 3 and the reference signal S2 have the same phase.

That is, the register 74 in the control circuit 841
The control circuit 841 performs an operation of dividing the value obtained by adding the output signal 55 of 1 and the output signal 57 of the counter 722 by 2, and supplies the control signal S101 as the operation result to the delay time variable circuit 802. That is, the output of the control circuit 841 when the phase difference between the reference signal S2 and the first comparison signal S3 becomes 0 is the first control signal, and the reference signal S
2 and the first comparison signal S3, the control circuit 841 controls the delay time of the delay variable circuit 802 after the above operation to set the phase difference to 0. As a result, the reference signal S2 and the second comparison signal S6 are obtained.
When the output of the control circuit 841 when the phase difference between and becomes 0 is the second control signal, the value of the first control signal and the value of the second control signal are added, and the added value The delay time variable circuit 841 with a value obtained by dividing 2 by 2 as a control signal.
To supply. In this way, the phase of the signal at the connection point between the first series circuit SC1 and the second series circuit SC2 is controlled.

In other words, by executing the first step, the second step, and the third step, the reference signal S2 is applied to the reference signal S2 within the range of the time resolution of the delay time variable circuit 802 regardless of the electrical length of the wiring. Thus, the phases of the output signal S5 of the buffer 903 can be aligned.

In the above embodiment, the signals S3 to S
When the delay time up to 6 is ΔT _delay , the delay time variable range Δt _v of the delay time variable circuit 802 is Δt.
_The requirement is that _v ≥ ΔT _delay .

It is desirable that the metal wirings 951 and 952 be laid out as a pair in the semiconductor integrated circuit LSI1. Specifically, the metal wirings 951 and 95
2 and 2 are wired in parallel adjacent to each other, or are wired in parallel with a GND line interposed therebetween, and the parallel portions are all made of the same kind of metal wiring, and the wiring widths are also made to coincide with each other. The reason for doing this is that even if the wiring length is the same, considering the capacitance between different metal wiring layers and the capacitance between the same metal wiring layers, the capacitance may differ even if the wiring length is the same, and the electrical lengths are the same. Because it will disappear. Therefore, the metal wiring 95
The above influence can be reduced by treating 1 and 952 as pair wiring and laying out most of the same paths. In the above embodiment, the delay time variable circuit 80 is used.
Although the delay characteristic of 2 is given by the equation (1), the delay characteristic of the delay time variable circuit 802 may be given by the following equation (2).

[0054]

[Equation 2] In this case, all the 5-bit initial values of the control signal S101 are set to high, and the logic of the control circuit 841 is partially changed.

When a buffer is inserted in the middle of the metal wiring 951 and the position of the inserted buffer is the electrical length l _x of the metal wiring from the buffer 902, the buffer 905 also in the metal wiring 952. It suffices to install the buffer at the position of the electrical length l _x of the metal wiring.

Furthermore, a signal other than 5 bits may be used as the control signal of the delay time variable circuit 802, and the number of bits of the control signal S101 has an appropriate value depending on the variable range of the delay time variable circuit 802 and the time resolution. The logic of the control circuit 841 is partially changed according to the number of bits.

In the above embodiment, when the input data is the same for 10 consecutive cycles with respect to the reference signal S2, the output signal 54 of the comparator 731 and the output signal S103 of the comparator 732 are changed. However, instead of this, during the number of cycles other than 10 cycles of input data,
When they are the same, the signal 54 and the signal S103 may be changed.

According to the above embodiment, when there are n clock signal distribution destinations, n main circuits C1 which are the portions surrounded by the dotted line in FIG. 1 are required. According to the above embodiment, the fixed delay time of the delay time circuit 801 and the offset delay time of the delay time variable circuit 802 are aligned, so that the delay time difference caused by the manufacturing variation of the transistors can be canceled.

That is, in the above embodiment, the delay time circuit 80
1 fixed delay time Δt _const1 and delay time variable circuit 80
Since the offset delay time Δt _{const2 of} 2 is canceled in the circuit, it is possible to reduce the influence of the initial delay time difference caused by the manufacturing variation of the transistor. For example, Δt
_{Even if} the values of _const1 and Δt _const2 are the same, if they are not the same due to variations in transistor manufacturing,
A skew of Δt _{const1 −Δt const2} | / 2 occurs.

Further, a plurality of sets each including the first series circuit SC1, the second series circuit SC2, and the delay time variable circuit 802 are provided, and a predetermined point is used as a branch start point, and a signal generation source is used. The signal at the branch start point supplied from the signal source is connected to the branch start point as the first signal, and the first signal is distributed in a tree shape to a plurality of points by the buffer wiring. Delay time variable circuit 802
By controlling the phase of each signal at the output terminal of, the signal supplied from the signal generation source is branched and supplied to n points, and the clock skew caused by the wiring capacitance and the wiring resistance is delayed. This can be reduced by 802, and moreover, the influence of the initial delay time difference caused by variations in transistor manufacturing can be reduced.

When signals are supplied to a plurality of locations in this way, a fixed value may be set for each control circuit that controls the delay time of the plurality of series circuits. That is, when signals are supplied to a plurality of locations, the signal arrival time at the signal supply point at each location may differ due to the difference in the load at each location, etc. For example, the signal arrival times can be matched by changing the fixed value to be given.

Further, when the phase comparison circuit cannot detect the phase difference between the reference signal and the comparison signal, the control circuit 8
Output signal 55 of register 741 in 41 and counter 72
A fixed value determined by the phase error in the phase comparison circuits 821 and 822 and the time resolution of the delay time variable circuit is added to the value obtained by dividing the addition value of the output signal 57 of 2 by 2 and the added value is controlled. As a signal, the delay time variable circuit 8
02, it is possible to reduce the phase error,
Clock skew can be further reduced.

In each of the above embodiments, the control circuit 841
However, the control circuit 841 has been described above.
Can be considered to be composed of a first control circuit and a second control circuit. That is, in the above embodiment, the first control circuit that outputs the control signal according to the output signal of the first phase comparison circuit to the delay time variable circuit and the control signal according to the output signal of the second phase comparison circuit. To a delay time variable circuit, and a first series circuit is connected between the delay time variable circuit and the second series circuit.
As a result of the control circuit controlling the delay time of the delay time variable circuit, the output signal of the first control circuit when the phase difference between the reference signal and the first comparison signal becomes 0 is the first control signal, After the above-described operation of setting the phase difference between the reference signal and the first comparison signal to 0, the second control circuit controls the delay time of the delay variable circuit, and as a result, the phase difference between the reference signal and the second comparison signal is obtained. When the output signal of the second control circuit is 0, the value of the first control signal and the value of the second control signal are added, and the value obtained by dividing by 2 is the control signal. Is supplied to the delay time variable circuit, and the signal at the connection point of the first series circuit and the second series circuit is used as the signal for phase control.

FIG. 3 is a circuit diagram showing a semiconductor integrated circuit LSI2 according to the second embodiment of the present invention. 3, the same members as those shown in FIG. 1 are designated by the same reference numerals.

The semiconductor integrated circuit LSI2 is a circuit for aligning the phase of the signal S5 at a predetermined position with the phase of the reference signal S1.

The semiconductor integrated circuit LSI2 basically has
This is the same as the semiconductor integrated circuit LSI1, but a circuit is added to the semiconductor integrated circuit LSI1 to simultaneously reduce clock skew and clock delay. Hereinafter, of the semiconductor integrated circuit LSI2, circuit blocks different from the semiconductor integrated circuit LSI1 will be described.

The third phase comparison circuit 823 uses the reference signal S
It is a circuit that compares the phase of 2 with the phase of the signal S1. When the phase of the reference signal S2 is delayed with respect to the signal S1, the output signal UP3 of the third phase comparison circuit 823 becomes low during the period from the rising edge of the signal S1 to the rising edge of the reference signal S2, and vice versa. When the phase of the reference signal S2 leads the signal S1, the output signal DOWN3 of the third phase comparison circuit 823 becomes low during the period from the rising edge of the reference signal S2 to the rising edge of the signal S1. In other cases, the third phase comparison circuit 82
The output signal UP3 of 3 and the output signal DOWN3 of both become high. The third phase comparison circuit 823 is located near the buffer 901 and the delay time circuit 801.

The control circuit 841a controls the delay time variable circuit 802 based on the output signal UP1 and output signal DOWN1 of the first phase comparison circuit 821 or the output signal UP2 and output signal DOWN2 of the second phase comparison circuit 822. A 5-bit control signal S101 is sent, and the control circuit 842
It is a circuit that sends a 1-bit control signal S103 to.

The control circuit 842 is the third phase comparison circuit 8
23 is a circuit that sends a 7-bit control signal S102 to the delay time variable circuit 803 based on the output signal UP3 and the output signal DOWN3 of 23 and the output signal S103 of the control circuit 841a.

The clock signal CK is an input signal of the buffer 901, and the output signal S1 of this buffer 901 is
It is applied to the frequency divider 851, the third phase comparison circuit 823, and the selector 861. The output signal S11 of the frequency divider is
The output signal S103 of the control circuit 841a applied to the selector 861 is applied to the selector 861 as a selection signal. The output signal S12 of the selector 861 is applied to the delay time variable circuit 803, and the output signal S13 of the delay time variable circuit 803 is applied to the delay time circuit 801 and the delay time variable circuit 802.

While the output signal S103 of the control circuit 841a is low, the selector 861 selects the signal S11 which is the output signal of the frequency divider 851. When the output signal S103 of the control circuit 841a becomes high, the selector 861 Selects the signal S1.

When the 7-bit control signal of the delay time variable circuit 803 is B ₁ , B ₂ , B ₃ , B ₄ , B ₅ , B ₆ , B ₇ , and the delay time is Δt _vd l ₃ , the delay time is Variable circuit 8
The delay time characteristic with respect to the control signal of No. 03 is expressed by the following equation (3).
And has a linear delay time characteristic with respect to the control signal.

[0073]

(Equation 3) However, Δt _const3 corresponds to the offset delay time, and Δt _res3 corresponds to the time resolution.

FIG. 4 is a block diagram showing an example of an internal circuit of the control circuit 842 in the semiconductor integrated circuit LSI2.

In FIG. 4, the counter 723 is a 7-bit up counter, and after being initialized by the signal S103, the EX-OR circuit 715 outputs the output signal UP3,
The value of the output signal DOWN3 is logically calculated, and the counter 723 counts up based on the signal 62 which is the calculation result.

During the 10 cycles of the reference signal S2, the comparator 733 detects that the least significant bit (LSB) signal 64 of the output signal 63 of the counter 723 does not change continuously. The output signal 65 goes high. In the state where the comparator 733 is initialized by the signal S103, the output signal 65 of the comparator 733 is low. Note that once the output signal 65 of the comparator 733 becomes high, the output of the comparator 733 does not change unless it is initialized by the signal S103. Inverter 716 and N
The OR circuit 717 logically operates the values of the signal 65 and the reference signal S2, and the register 743 fetches the output signal 63 of the counter 723 based on the signal 67 which is the operation result. While the output signal 65 of the comparator 733 is low,
When the reference signal S2 rises, the output signal 63 of the counter 723 is taken into the register 743, but the comparator 7
When the output signal 65 of 33 goes high, the register 743 holds the data.

Next, the operation of the semiconductor integrated circuit LSI2 will be described.

The operation of the semiconductor integrated circuit LSI2 is as follows.
The first stage (stage in which the phases of the reference signal S2 and the first comparison signal S3 are aligned), the second stage (stage in which phases of the reference signal S2 and the second comparison signal S6 are aligned), and the third stage ( It is divided into a step of aligning the phase of the output signal S5 of the buffer 903 and the reference signal S2) and a fourth step (stage of aligning the phase of the signal S5 and the output signal S1 of the buffer 901).
The operations of the first step, the second step, and the third step are the same as the operations of the semiconductor integrated circuit LSI1.
Only the operation of the fourth stage will be described.

When the operation of the third stage in the semiconductor integrated circuit LSI2 is completed, the output signal S1 of the control circuit 841a is output.
03 transitions from low to high. The reason why the signal S13 obtained by frequency-dividing the clock signal CK is used while the signal S103 is low is that the output signal S5 of the buffer 903 is output if the cycle time of the clock signal is not larger than ΔT _delay defined in the semiconductor integrated circuit LSI1. This is because a malfunction may occur at the stage where the phase and the phase of the reference signal S2 are aligned.

When the output signal S103 of the control circuit 841a becomes high, the output signal S1 of the buffer 901 changes the selector 861, the delay time varying circuit 803, and the delay time circuit 80.
1 becomes the reference signal S2 and is applied to the third phase comparison circuit 823. When the third phase comparison circuit 823 compares the signal S1 and the reference signal S2 and if these phases do not match, based on the output signal UP3 and the output signal DOWN3 of the third phase comparison circuit 823, The output signal S102 of the control circuit 842 is [000 in the initial state.
Change from 0000] to [0000001] by +1
The delay time in the delay time variable circuit 803 is reduced by Δt _res3 . In response to this result, the third phase comparison circuit 823 performs the phase comparison between the signal S1 and the reference signal S2 again, and if the phase difference is detected, the control circuit 8 is operated in the same manner as above.
The output signal S102 of 42 is incremented by 1.

By repeating the above operation, finally, the third phase comparison circuit 823 cannot detect the phase difference between the signal S1 and the reference signal S2. Therefore, the output control signal S102 in the control circuit 842 does not change. As a result, the fourth stage ends, and the phases of the signal S1 and the reference signal S2 match.

Here, the phases of the signal S5 and the reference signal S2 are aligned by the operations up to the third step, and the operation of the fourth step has no influence on the phase relationship between the signal S5 and the reference signal S2. Does not reach. Therefore, when the fourth stage is completed,
The phase of the signal S5 can be aligned with the signal S1.

The above first step, second step, third step, fourth step
By executing the steps, the delay time variable circuit 802
Within the time resolution of, regardless of the electrical length of the wiring,
The phase of the output signal S5 of the buffer 903 can be aligned with the reference signal S2, and the delay time variable circuit 80
Within the range of the time resolution of 3, the phase of the output signal S5 of the buffer 903 can be aligned with the signal S1.

In the above embodiment, when the cycle time of the clock signal CK is t _CK , the delay time variable circuit 803
For the delay time variable range Δt _v3 of, it is necessary that Δt _v3 ≧ t _CK .

In the above embodiment, the clock phases in the LSI are made uniform, but the wiring 9
If it is considered that the wirings 51 and 952 connect the LSIs, the clock phases between the LSIs can be made uniform.

Further, a phase advancing means for advancing the phase of the signal is provided between the signal generating source and the predetermined point, and the phase between the signal and the reference signal between the signal generating source and the predetermined point is set. They may be aligned, and by doing so, the phase of the distributed signal can be aligned with the phase of the external signal.

[0087]

According to the present invention, it is possible to reduce the influence of variations in the offset delay time of the delay time variable circuit due to variations in transistor manufacturing. Therefore, the synchronization can be achieved without much dependence on the wiring length and the wiring width. There is an effect that clock distribution to each circuit block in the designed chip can be realized with low clock skew and low delay, and layout is easy.

[Brief description of drawings]

FIG. 1 is a semiconductor integrated circuit LSI according to an embodiment of the present invention.
1 is a circuit diagram showing phase correction of the clock signal CK. FIG.

FIG. 2 is a control circuit 84 in the semiconductor integrated circuit LSI1.
FIG. 3 is a diagram showing a specific example of FIG.

FIG. 3 is a semiconductor integrated circuit L according to a second embodiment of the present invention.
It is a circuit diagram which shows SI2.

FIG. 4 is a control circuit 84 in the semiconductor integrated circuit LSI2.
It is a block diagram which shows an example of the internal circuit of FIG.

FIG. 5 is a circuit diagram showing conventional clock distribution for canceling wiring delay time.

[Explanation of symbols]

LS1, LSI2, LSI3 ... Semiconductor integrated circuit, SC1 ... First series circuit, SC2 ... Second series circuit, S2 ... Reference signal, S3 ... First comparison signal, S5 ... First series circuit and second series circuit Signal at connection point with serial circuit, S6 ... Second comparison signal, S101, S102, S103 ... Control signal, 801 ... Delay time circuit, 802, 803 ... Delay time variable circuit, 821 ... First phase comparison circuit, 822 ... 2nd phase comparison circuit, 823 ... 3rd phase comparison circuit, 951, 952 ... Metal wiring.

Claims (5)

[Claims] 1. A delay time circuit for fixedly delaying a first signal at a predetermined point supplied from a clock signal generating source by a predetermined time; the first signal according to a predetermined control signal.
And a delay time variable circuit capable of changing the delay time of the signal and setting the maximum delay time longer than the fixed delay time by the delay time circuit; the buffer and the wiring are connected in series. A first series circuit; a buffer having the same electrical characteristics as the buffer in the first series circuit, and a wiring having substantially the same electrical characteristics as the wiring in the first series circuit, connected in series A series circuit of 2; a signal delayed by the delay time circuit as a reference signal, the first signal passed through the delay time varying circuit as a first comparison signal, and the reference signal and the first comparison signal. A first phase comparison circuit for comparing the phase of the signal; a second phase signal for the first signal that has passed through the delay time variable circuit, the first series circuit, and the second series circuit.
A second phase comparison circuit that compares the phase of the reference signal with the phase of the second comparison signal as the comparison signal of the above; and the control signal corresponding to the output signal of the first phase comparison circuit is delayed. A first control circuit for outputting to the time variable circuit; a second control circuit for outputting the control signal according to the output signal of the second phase comparison circuit to the delay time variable circuit; The first series circuit is connected between the delay time variable circuit and the second series circuit, and as a result of the first control circuit controlling the delay time of the delay time variable circuit, the reference signal and the The output signal of the first control circuit when the phase difference between the first comparison signal and the first comparison signal is zero is used as the first control signal, and the phase difference between the reference signal and the first comparison signal is zero. After the above operation, the second control circuit causes the delay variable time As a result of controlling the delay time of the path, the output signal of the second control circuit when the phase difference between the reference signal and the second comparison signal becomes 0 is the second control signal, and the first control signal is the first control signal. The value of the control signal and the value of the second control signal are added, and the value divided by 2 is supplied to the delay time variable circuit as the control signal, and the first series circuit and the second series circuit are provided. A semiconductor integrated circuit characterized in that a signal at a connection point with is used as a signal for phase control. 2. The supply circuit according to claim 1, wherein a plurality of series-connected circuits of the first series circuit and the second series circuit are provided, and the predetermined point serves as a branch starting point, and the signal is supplied from the signal generation source. The signal at the branch start point is used as a first signal, the first signal is distributed in a tree shape to a plurality of points, and the first signal in each series connection circuit is provided.
2. A semiconductor integrated circuit, which controls the phase of each signal at the connection point between the serial circuit and the second serial circuit. 3. The second phase comparison circuit according to claim 1 or 2, wherein the value of the first control signal and the value of the second control signal are added and divided by two. The semiconductor integrated circuit is characterized in that a fixed value determined by the phase error in the delay time variable circuit and the time resolution of the delay time variable circuit is added, and the added value is supplied to the delay time variable circuit as the control signal. 4. The fixed value according to claim 3, wherein when the signals are supplied to a plurality of locations, the fixed value can be set for each of the control circuits that control the delay times of the plurality of series circuits. Semiconductor integrated circuit. 5. The phase advancing means for advancing the phase of a signal is provided between the signal source and the predetermined point according to claim 1, and the signal source and the predetermined point are connected to each other. A semiconductor integrated circuit in which the phase of the signal between the reference signal and the reference signal is aligned.