JPH09213912A - Nonvolatile semiconductor memory device, and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the flatness of the top of a stack gate by suppressing the leak passage from the edge of a floating gate. SOLUTION: A field oxide film 4 for element isolation and a gate insulating film 6 are made on a silicon substrate 12, and then, a first polysilicon layer 8, an insulating film 12, and a second polysilicon layer 14 are stacked. The stack is patterned by one time of photolithography, and not only the floating gate 8 but also the control gate 14 are separated, memory cells and all. An interlayer insulating film 16 is made from above the control gate 14, and a part of the control gate 14 is exposed by CMP method (chemical mechanical polishing method), and the area between the exposed parts is connected by an aluminum film 30 and it is made a word line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device having a stack gate composed of a floating gate and a control gate, and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 1 shows a manufacturing process including a commonly used method for forming a stack gate. (A) ~
(C) is XX ′ of (a) to (c) described on the right side thereof.
It is sectional drawing in a line position. (A) After forming a field oxide film 4 as an element isolation region on a silicon substrate 2 and forming a gate insulating film 6, a first polysilicon layer 8 to be a floating gate is formed.
To form A resist layer is formed on the polysilicon layer 8, and a resist pattern having a groove for forming a slit 10 for separating the floating gate in the word line direction is formed by photolithography, and the polysilicon layer is used as a mask. The slit 10 is formed by etching 8.

(B) The insulating film 1 is formed on the surface of the polysilicon layer 8.
2 is formed, and a second polysilicon layer 14 is further formed thereon. Then, the silicon layer 14, the insulating film 12 and the polysilicon layer 8 are patterned by photolithography and etching to complete the control gate 14, the insulating film 12 and the floating gate 8.

(C) After that, an interlayer insulating film 16 is formed,
After forming the contact hole 18 on the drain region, an aluminum film is formed, an aluminum wiring 20 is formed by patterning by photolithography and etching, and the aluminum wiring 20 and the drain region are connected through the contact hole 18. The aluminum wiring 20 becomes a bit line and the control gate 14 becomes a word line.

The stack gate forming method shown in FIG. 1 is a basic method, and the stack gate forming method described in, for example, JP-A-2-31466 and JP-A-3-34470 is also used. Is the same.

[0006]

The method of FIG. 1 has the following problems. (1) Photolithography and etching step (A) for forming the slit 10 for separating the floating gate in the word line direction, and photolithography and etching step for separating the floating gate and the control gate in the bit line direction. (B) is included. That is,
Two photoengravings are needed to form the stack gate,
This leads to higher costs and longer construction periods.

(2) The area 22 shown in FIG. 1 (b) is
This is an area in which etching is performed twice, that is, etching for forming the slit 10 and etching for separating the floating gate and the control gate in the bit line direction. In this area 22, excessive etching is performed.
A step is generated, which hinders the flattening of the surface of the interlayer insulating film in a later process. In addition, a residue during etching tends to remain in the region 24 along the step, which causes a short between word lines. These lead to a decrease in reliability.

(3) As shown in FIG. 1B, an electric leak path easily exists from the edge portion 26 of the floating gate 8 to the opposing control gate 14, and the electrons accumulated in the floating gate 8 disappear. Therefore, there is a reliability problem that the retention characteristics deteriorate.

(4) Since the flatness with respect to the stack gate is insufficient, there arise problems such as insufficient coverage of metal wiring formed on the stacked gate via the interlayer insulating film, and further insufficient margin for multilayer wiring. Therefore, it is an object of the present invention to provide a structure of a memory device and a manufacturing method thereof that solve these problems.

[0010]

In the nonvolatile semiconductor memory device of the present invention, the floating gate of the stack gate formed on the substrate and the control gate formed on the floating gate via the insulating film have the same planar shape. Drains formed and separated for each memory cell, electrically connected between control gates adjacent in the word line direction by the first metal layer, and arranged separately in the bit line direction The region or the source region is electrically connected by a metal layer that serves as a bit line.

The control gate preferably has a laminated structure in which the lower layer is a polysilicon layer and the upper layer is a conductive metal layer. The conductive metal layer above the control gate is preferably a refractory metal silicide composed of W, Mo, Ti or Ta.

The bit line can be formed by the first metal layer. In that case, a band-shaped second metal layer patterned in a strip shape extending in the word line direction is formed on the stack gate via the interlayer insulating film, and the second metal layer is a through film of the interlayer insulating film. 1st which electrically connects between control gates through a hole
It is preferably electrically connected to the second metal layer. The bit line can also be formed by the second metal layer.

The manufacturing method of the present invention includes the following steps (A) to (E) to form a stack gate on a semiconductor substrate. (A) After forming an element isolation region and a gate insulating film on a semiconductor substrate, a laminated film including a polysilicon layer to be a floating gate, an insulating film on the polysilicon layer, and a conductive layer to be a control gate on the polysilicon layer is formed. Step (B) A single photolithography process is performed to form a resist pattern that is separated for each memory cell so that the isolation position in the word line direction is on the element isolation region, and the resist pattern is used as a mask. A patterning step of etching the laminated film, (C) a step of forming an interlayer insulating film having a thickness such that the upper surface of the laminated film is buried, (D)
A step of polishing the interlayer insulating film by a chemical mechanical polishing method to expose a part of the upper surface of the laminated film; (E) forming a first-layer metal film, and between control gates adjacent in the word line direction. Patterning the metal film to connect the.

[0014]

FIG. 2 is a process drawing of an embodiment showing the formation of a stack gate. (A) to (E) are shown as sectional views, and (c) to (e) are (C) to (E), respectively. It is a top view corresponding to (E). The cross-sectional view is taken along the line YY 'in the plan view. (A) Element isolation field oxide film 4 on silicon substrate 2
And a gate insulating film 6 are formed, and then a first polysilicon layer 8 to be a floating gate is formed.

(B) An insulating film 12 is formed thereon, and a second polysilicon layer 14 to be a floating gate is further formed thereon. (C) A resist layer is formed on the polysilicon layer 14, and a stack gate pattern is formed by photolithography. This pattern is a pattern that is separated for each memory cell by being separated in the word line direction and the bit line direction, and the separation in the word line direction is made by a slit passing over the field oxide film 4 as in the conventional case. , A resist pattern is formed. Using the resist pattern as a mask, the polysilicon layer 14, the insulating film 12 and the polysilicon layer 8 are sequentially etched and patterned.

FIGS. 3C and 3C show a patterned laminated body in which not only the floating gate 8 but also the control gate 14 is separated for each memory cell. Further, the separation in the word line direction is made by the slit 10 passing over the field oxide film 4,
Since the opposing ends of the control gates 14, 14 arranged in the word line direction and adjacent to each other across the slit 10 are on the field oxide film 4, the substrate 2
It projects more than the upper part.

(D) After removing the resist layer, an interlayer insulating film 16 is formed on the control gate 14 to a thickness such that the control gate 14 is sufficiently buried. Then, the CMP method (chemical mechanical polishing method) is used until the control gate 14 is partially exposed. Control gate 14 exposed by polishing by the CMP method
The portion marked with is a portion facing the slit 10 on the field oxide film 4.

(E) An aluminum film 30 is formed on the entire surface, and the aluminum film 30 is formed by photolithography and etching so that the exposed portions of the control gates 14, 14 facing each other across the slit 10 are connected by the aluminum film 30. Pattern. As a result, as shown in FIG. 2E, the control gates 14 separated for each memory cell are connected by the aluminum wiring 30 between the control gates 14 adjacent to each other in the word line direction. Form a word line extending in the horizontal direction.

In the step corresponding to FIG. 2B, as shown in FIG. 3, the polysilicon layer 1 which becomes the control gate is formed.
2 after the conductive metal layer 32 is overlaid and deposited on FIG.
A stack gate can be formed by the processes of (C) to (E). This can reduce the resistance of the control gate, that is, the word line. As the conductive metal layer 32, W (tungsten), Mo
(Molybdenum), Ti (titanium) or Ta (tantalum)
A refractory metal silicide consisting of is preferred.

As shown in FIG. 2E, the region 34 of the substrate 2 is a drain and is isolated by the element isolation field oxide film 4. On the other hand, the region 36 is a source region and is continuous in the word line direction. Bit lines are required to connect the drain regions 34.

FIG. 4 shows an example of the bit line. (A) is a cross-sectional view, (B) is a plan view thereof, and (A) is a cross-sectional view taken along line ZZ ′ of (B). To form this bit line, refer to FIG.
In the state of (E) and (e), the aluminum wiring 30
A contact hole 38 is formed in the drain region 34 before the formation of. After that, in the patterning process of forming an aluminum film and forming the aluminum wiring 30, the bit line 40 of the aluminum wiring is simultaneously formed. The bit line 40 is in the vertical direction in FIG.

An interlayer insulating film 36 is formed on the aluminum wirings 30 and 40, a through hole is formed on the aluminum wiring 30, and then a second aluminum film is formed, and the aluminum film is patterned by photolithography and etching. As a result, an aluminum wiring 42 extending in the word line direction is formed on the control gate 14. Aluminum wiring 42 is connected to aluminum wiring 30 through a through hole in interlayer insulating film 36. Aluminum wiring 4
Reference numeral 2 is also a word line, which contributes to lowering the resistance of the word line together with the control gate 14 and the metal line 30.

FIG. 5 shows another example of the bit line. (A) is a cross-sectional view, (B) is a plan view thereof, and (A) shows a cross-sectional view taken along line WW ′ of (B). To form this bit line, refer to FIG.
In the state of (E) and (e), the aluminum wiring 30
A contact hole 38 is formed in the drain region 34 before the formation of. Then, an aluminum film is formed, and in the patterning step of forming the aluminum wiring 30, the aluminum pattern 44 for contact is simultaneously formed.

An interlayer insulating film 36 is formed on the aluminum wiring 30 and the pattern 44, and the aluminum pattern 4 is formed.
5 is formed on the drain region 34, a second aluminum film is formed on the drain region 34, and a second aluminum film is formed on the drain region 34 by photolithography and etching.
In (B), the bit line 46 extending in the vertical direction is formed.
The bit line 46 is a drain region 34 arranged in the vertical direction in FIG. 5B through the through hole of the interlayer insulating film 36, the aluminum pattern 44 and the contact hole 38.
Connected to. In this case, the word line is only composed of the control gate 14 and the aluminum wiring 30 connecting the control gates 14 and 14, and the word line by the metal wiring is not provided as shown in FIG.

Aluminum wiring 30, bit line 4
The materials of 0, 46, the word line 42, and the aluminum pattern 44 are not limited to pure aluminum, but include aluminum alloys containing Si or Cu in aluminum,
Any material may be used as long as it is used as a material for metal wiring.

[0026]

According to the present invention, as shown in the steps of FIGS. 2 (C) and 2 (c), the stack gate can be formed in one photoengraving step, resulting in higher cost and longer construction period. Disappears. Further, from this fact, a region such as a region to be excessively etched (a region indicated by symbol 22 in FIG. 1B) does not occur in principle, so that a problem associated with excessive etching does not occur. . Further, since the edge portion 26 shown in FIG. 1B does not exist, the retention characteristic of the memory element is improved. Insulating film filling the stack gate is C
Since the polishing is performed by the MP method, the processed surface becomes a flat surface, the coverage of the metal wiring formed thereabove is improved, and the margin for multi-layer wiring is widened. By making the upper layer of the control gate a conductive metal layer,
The polishing end point can be easily detected by the CMP method, and the processing accuracy is improved. It also leads to lower resistance of the word line and improvement of operation speed. There are two word lines, one with the control gate and the other with the second metal layer.
With the layered structure, the resistance of the word line can be reduced and the operation speed can be improved. If the bit line is formed by the second metal layer, it is not necessary to provide the space S as shown in FIG. 4B, the cell size can be reduced, and a large capacity and highly integrated memory device can be obtained. Can be realized.

[Brief description of drawings]

1A to 1C are views showing a conventional stack gate manufacturing method, in which (A) to (C) are cross-sectional views thereof, (a) to (c) are plan views thereof, and the cross-sectional views are X- of the plan view. The cross-sectional view at the X ′ line position is shown.

2A to 2E are views showing a method up to forming a stack gate in one embodiment, in which (A) to (E) are cross-sectional views thereof, and (a) to (e) are plan views thereof. Shows a cross-sectional view taken along the line YY 'in the plan view.

FIG. 3 is a cross-sectional view showing a stacked state in a manufacturing method in which a control gate has a stacked structure.

FIG. 4 is a diagram showing a first embodiment in which even bit lines are formed, (A) is a cross-sectional view, (B) is a plan view, and the cross-sectional view is taken along line ZZ ′ of the plan view. A cross-sectional view is shown.

5A and 5B are views showing a second embodiment in which even bit lines are formed. FIG. 5A is a sectional view, FIG. 5B is a plan view, and the sectional view is taken along the line WW ′ of the plan view. A cross-sectional view is shown.

[Explanation of symbols]

2 substrate 4 element isolation field oxide film 6 gate insulating film 8 first polysilicon layer (floating gate) 10 slits 12 insulating film 14 second polysilicon layer (control gate) 16 interlayer insulating film 30 connecting control gates Aluminum wiring 32 Conductive metal layer 40 Bit line made of first aluminum film 42 Word line made of second aluminum film 46 Bit line made of second aluminum film

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] April 19, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Brief description of drawings

[Correction method] Change

[Correction contents]

[Brief description of drawings]

1A to 1C are views showing a conventional stack gate manufacturing method, in which (A) to (C) are cross-sectional views thereof, (a) to (c) are plan views thereof, and the cross-sectional views are X- of the plan view. The cross-sectional view at the X ′ line position is shown.

FIG. 2 is a diagram showing a method for forming a stack gate in one embodiment, (A) to (E) are cross-sectional views thereof, and (c) and (e) are (C) and (E), respectively. FIG. 3 is a plan view of the above, and the cross-sectional view is a cross-sectional view taken along line YY ′ of the plan view.

FIG. 3 is a cross-sectional view showing a stacked state in a manufacturing method in which a control gate has a stacked structure.

FIG. 4 is a diagram showing a first embodiment in which even bit lines are formed, (A) is a cross-sectional view, (B) is a plan view, and the cross-sectional view is taken along line ZZ ′ of the plan view. A cross-sectional view is shown.

5A and 5B are views showing a second embodiment in which even bit lines are formed. FIG. 5A is a sectional view, FIG. 5B is a plan view, and the sectional view is taken along the line WW ′ of the plan view. A cross-sectional view is shown.

[Explanation of symbols] 2 substrate 4 element isolation field oxide film 6 gate insulating film 8 first polysilicon layer (floating gate) 10 slits 12 insulating film 14 second polysilicon layer (control gate) 16 interlayer insulating film 30 Aluminum wiring connecting control gates 32 Conductive metal layer 40 Bit line made of first aluminum film 42 Word line made of second aluminum film 46 Bit line made of second aluminum film

Claims (6)

[Claims] 1. A floating gate of a stack gate formed on a substrate and a control gate formed on the substrate via an insulating film are formed in the same plane shape and are separated for each memory cell. The control gates adjacent to each other in the direction are electrically connected by the first metal layer, and the drain regions or the source regions separated and arranged in the bit line direction are electrically connected by the metal layer serving as the bit line. A non-volatile semiconductor memory device, characterized in that it is connected to. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the control gate has a laminated structure in which a lower layer is a polysilicon layer and an upper layer is a conductive metal layer. 3. The non-volatile semiconductor memory device according to claim 2, wherein the conductive metal layer above the control gate is a silicide of a refractory metal made of W, Mo, Ti or Ta. 4. The bit line is formed of a first metal layer, and a second metal layer patterned in a strip shape extending in the word line direction on the stack gate via an interlayer insulating film. Is formed, and the second metal layer is electrically connected to the first metal layer electrically connecting the control gates through the through hole of the interlayer insulating film. The nonvolatile semiconductor memory device according to claim 1, 2, or 3. 5. The non-volatile semiconductor memory device according to claim 1, wherein the bit line is formed of a second metal layer. 6. A method for manufacturing a non-volatile semiconductor memory device, comprising forming a stack gate on a semiconductor substrate, including the steps (A) to (E) below. (A) After forming an element isolation region and a gate insulating film on a semiconductor substrate, a laminated film including a polysilicon layer to be a floating gate, an insulating film on the polysilicon layer, and a conductive layer to be a control gate on the polysilicon layer is formed. Step (B) A single photolithography process is performed to form a resist pattern that is separated for each memory cell so that the isolation position in the word line direction is on the element isolation region, and the resist pattern is used as a mask. A patterning step of etching the laminated film; (C) a step of forming an interlayer insulating film having a thickness to bury the upper surface of the laminated film; (D) polishing the interlayer insulating film by a chemical mechanical polishing method to form the laminated film. Step of exposing a part of the upper surface of the film, (E) forming a first-layer metal film and connecting control gates adjacent to each other in the word line direction The step of patterning the metal film on the jar.