JPH09213860A - Semiconductor lead forming method - Google Patents
Semiconductor lead forming methodInfo
- Publication number
- JPH09213860A JPH09213860A JP8040704A JP4070496A JPH09213860A JP H09213860 A JPH09213860 A JP H09213860A JP 8040704 A JP8040704 A JP 8040704A JP 4070496 A JP4070496 A JP 4070496A JP H09213860 A JPH09213860 A JP H09213860A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- bending
- molding
- semiconductor
- semiconductor package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 238000000034 method Methods 0.000 title claims abstract description 42
- 238000005452 bending Methods 0.000 claims abstract description 55
- 238000000465 moulding Methods 0.000 claims abstract description 47
- 238000007723 die pressing method Methods 0.000 claims abstract description 6
- 238000003825 pressing Methods 0.000 claims description 4
- 229910000679 solder Inorganic materials 0.000 abstract description 13
- 241000272168 Laridae Species 0.000 abstract description 7
- 230000007547 defect Effects 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010409 ironing Methods 0.000 description 2
- 238000007790 scraping Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Bending Of Plates, Rods, And Pipes (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体リードをガ
ルウイング曲げする半導体リード成形方法に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor lead molding method for gull-wing bending a semiconductor lead.
【０００２】[0002]
【従来の技術】半導体のＩＣパッケージ等における半導
体リードの曲げ形状の一つとしてガルウイング曲げ（図
４参照）が知られている。従来、このガルウイング曲げ
の形成には、大半はしごき曲げの方法が採用されていた
（特開平１−２１４１４８号公報等）。この曲げ方法
は、簡単な金型構成で平坦性の良いリード成形が行える
が、上からパンチを垂直下方に降ろしてくるので、予め
リードの表面にメッキされているハンダが擦れて剥がれ
やすい傾向があった。このため、リード成形に使用され
る成形ダイの成形部へ剥がれ落ちたハンダの付着が激し
く、成形ダイを頻繁にクリーニングしなければならず、
稼働率、生産性に難点があった。また、近年の半導体リ
ードのリード間ピッチの狭小化等にともない、剥がれ落
ちたハンダのカスがリードどうしに接触したりして、品
質不良を起こすという問題があった。2. Description of the Related Art Gullwing bending (see FIG. 4) is known as one of the bending shapes of semiconductor leads in a semiconductor IC package or the like. Conventionally, most of the methods for forming the gull wing bending have been the ironing bending method (Japanese Patent Laid-Open No. 1-214148, etc.). With this bending method, lead molding with good flatness can be performed with a simple mold structure, but since the punch is lowered vertically downward from above, the solder that has been plated on the lead surface in advance tends to rub and peel off. there were. For this reason, the peeled-off solder adheres strongly to the molding part of the molding die used for lead molding, and the molding die must be frequently cleaned.
There were difficulties in operating rate and productivity. Further, as the pitch between leads of semiconductor leads has become narrower in recent years, there is a problem that scraps of solder that have come off come into contact with leads to cause poor quality.
【０００３】上記のような不都合を解消するために、ロ
ーラによるガルウイング曲げの方法が提案されている
（特開平２−１１９２５１号等）。この方法は、ローラ
の回転によりリード成形を行うため、ハンダの擦れ落ち
には効果を示すものの、回転による加圧力の逃げのた
め、成形後のリードの平坦性に問題がある上、半導体パ
ッケージ単体カット後の曲げ加工しかできず、フレーム
状態での加工ができないという問題がある。さらに、こ
の方法は、用いる装置の構造上、寸法の大きな半導体パ
ッケージにしか採用できない。In order to solve the above-mentioned inconvenience, a method of gull wing bending with a roller has been proposed (Japanese Patent Laid-Open No. 2-119251, etc.). This method is effective for scraping off the solder because the lead is formed by rotating the roller, but there is a problem in the flatness of the lead after forming due to the escape of the pressing force due to the rotation. There is a problem that only bending after cutting can be performed, and processing in the frame state cannot be performed. Furthermore, this method can be applied only to a semiconductor package having a large size due to the structure of the device used.
【０００４】また、上記のようなハンダの擦れ、剥がれ
落ちの不具合を軽減するため、上金型の曲げパンチと下
金型の可動ダイでリードを挟み込みながらガルウイング
曲げする方法も提案されている（実開平２−１７８５３
号公報等）。しかしながら、この方法もハンダの擦れ落
ちには多少効果を示すが、可動ダイに曲線状軌跡の運動
をさせるため若干のハンダの剥がれ落ちは避けられな
い。また、若干の磨耗でも曲げ形状が変形するため、こ
の方法に使用する金型の寿命は他の金型に比べて短く、
成形後のリードの平坦性も十分ではない。Further, in order to reduce the above-mentioned problems of rubbing and peeling off of the solder, a method has also been proposed in which a lead is sandwiched between a bending punch of an upper die and a movable die of a lower die to perform gull wing bending ( Actual Kaihei 2-17853
No.). However, this method also has some effect on the scraping off of the solder, but some peeling off of the solder is inevitable because the movable die moves along a curved locus. In addition, the bending shape is deformed even with slight wear, so the life of the mold used in this method is shorter than other molds,
The flatness of the leads after molding is also insufficient.
【０００５】以上のような従来技術の問題点を一挙に解
決すべく、本出願人は、特開平６−２２４３４９号公報
において、新規な半導体リード成形方法を提案した。こ
の方法は、予め別の金型で半導体リードの予備曲げを行
ってリードを根本部から下方に斜めに成形し、次いで、
リードの最終形状に対応した成形ダイ上にリードが位置
するように半導体パッケージを支持し、リードの最終形
状に対応した形状の成形部を先端に有する曲げパンチ
を、前記斜めに予備曲げされたリードの曲げ部が描く円
弧軌跡の弦とほぼ同一直線方向に押圧することにより前
記リードをガルウイング曲げするものである。この方法
によれば、予備曲げされたリードの曲げ部が描く円弧軌
跡の弦とほぼ同一直線方向に曲げパンチを押圧するの
で、リードと成形部との擦れが極めて小さく、ハンダカ
スがほとんど生じない。また、ローラによる方法、可動
ダイによる方法の欠点を補い、成形後のリードの平坦性
が向上する。In order to solve the above-mentioned problems of the prior art all at once, the present applicant has proposed a new semiconductor lead molding method in Japanese Patent Laid-Open No. 6-224349. This method preliminarily bends the semiconductor leads with another mold to form the leads obliquely downward from the root, and then
The semiconductor package is supported so that the lead is positioned on the molding die corresponding to the final shape of the lead, and the bending punch having the molding portion of the shape corresponding to the final shape of the lead at the tip is formed by the above-mentioned diagonally pre-bent lead. The lead is gull-wing bent by pressing the lead in a direction substantially straight to the chord of an arc locus drawn by the bent part. According to this method, since the bending punch is pressed in a direction substantially on the same straight line as the chord of the arc locus drawn by the bent portion of the pre-bent lead, rubbing between the lead and the forming portion is extremely small, and solder residue hardly occurs. Further, the defects of the roller method and the movable die method are compensated for, and the flatness of the leads after molding is improved.
【０００６】ところで、半導体パッケージのリードをガ
ルウイング状に成形するにあたって、図５の（ａ）のよ
うにソリが生じている半導体パッケージを加工の対象と
しなくてはならない場合が多々ある。ところが、従来方
法によれば、半導体リードをガルウイング状に成形する
際、図５の（ｂ）のように、半導体パッケージ１１のリ
ード１２の根本部１２’をノックアウトプレートのよう
な上金型押さえ部材１３と成形ダイ１４との間に挟み込
んで成形している。この挟み込みにより半導体パッケー
ジ１１は強制的にフラットにされた状態で成形され、成
形が終わって挟み込みが解除された時、半導体パッケー
ジ１１は元のソリのある状態に復帰する。このため、成
形後のリード１２の平坦性が悪くなり、品質の低下、歩
留まりの低下を招いてしまう。この問題は、本出願人が
特開平６−２２４３４９号公報において提案した方法に
おいても同様に存在する。Incidentally, in forming the leads of the semiconductor package in a gull wing shape, it is often the case that the semiconductor package having warpage as shown in FIG. 5A must be processed. However, according to the conventional method, when the semiconductor leads are formed into a gull wing shape, as shown in FIG. 5B, the root 12 'of the leads 12 of the semiconductor package 11 is fixed to an upper die pressing member such as a knockout plate. It is sandwiched between 13 and the molding die 14 for molding. By this sandwiching, the semiconductor package 11 is forcibly molded in a flattened state, and when the sandwiching is released after the molding is completed, the semiconductor package 11 returns to the original warped state. For this reason, the flatness of the leads 12 after molding is deteriorated, resulting in deterioration of quality and yield. This problem also exists in the method proposed by the present applicant in Japanese Patent Laid-Open No. 6-224349.
【０００７】[0007]
【発明が解決しようとする課題】本発明は、このような
従来技術の問題点に鑑みてなされたもので、擦れによる
ハンダカスがほとんど発生せず、前記ローラによる方
法、可動ダイによる方法の欠点を補い、かつソリのある
半導体パッケージを加工の対象とした場合においても成
形後のリードの平坦性が非常に良好で、高品質かつ歩留
まりの高い半導体リード成形方法を提供することをその
課題とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art. It hardly causes solder dust due to rubbing, and has the drawbacks of the roller method and the movable die method. It is an object of the present invention to provide a semiconductor lead molding method of high quality and high yield, in which the flatness of the leads after molding is very good even when a complementary and warped semiconductor package is targeted for processing.
【０００８】[0008]
【課題を解決するための手段】本発明者らは、上記課題
を解決すべく鋭意研究を重ねた結果、本発明を完成する
に至った。すなわち、本発明によれば、予備曲げにより
予め根本部から下方斜めに折曲げられた半導体リードを
有する半導体パッケージを、リードの最終形状に対応し
た成形部を有する成形ダイと上金型押さえ部材との間
に、リード根本部の位置において隙間を設けた状態で支
持し、リードの最終形状に対応した形状の成形部を先端
に有する曲げパンチを、前記予備曲げされたリードに対
してリードの曲げ部が描く円弧軌跡の弦とほぼ同一直線
方向に押圧することにより該リードをガルウイング曲げ
することを特徴とする半導体リード成形方法が提供され
る。また、本発明によれば、上記構成において、リード
根本部の位置における該隙間の量を、半導体パッケージ
のソリの量に応じて設定することを特徴とする半導体リ
ード成形方法が提供される。Means for Solving the Problems The inventors of the present invention have completed the present invention as a result of intensive studies to solve the above problems. That is, according to the present invention, a semiconductor package having a semiconductor lead that is preliminarily bent obliquely downward from a root portion by a pre-bending is formed with a molding die having a molding portion corresponding to the final shape of the lead and an upper die pressing member. A bending punch having a molding part having a shape corresponding to the final shape of the lead at the tip is supported with a gap provided at the position of the root of the lead between the lead and the pre-bent lead. There is provided a semiconductor lead forming method, characterized in that the lead is gull-wing bent by pressing in substantially the same straight line direction as the chord of an arc locus drawn by the section. Further, according to the present invention, there is provided a semiconductor lead molding method characterized in that, in the above configuration, the amount of the gap at the position of the lead root portion is set according to the amount of warpage of the semiconductor package.
【０００９】[0009]
【発明の実施の形態】以下本発明の半導体リード成形方
法を図面を参照しながら詳述する。図１及び図２は本発
明の方法の原理説明図である。図中１は半導体パッケー
ジ、２は半導体リード、２’はリード根本部、３は曲げ
パンチ、４は曲げパンチ３の成形部、５はノックアウト
プレート（上金型押さえ部材）、６は成形ダイ、７は隙
間、２ａは予備曲げにより折曲状態となった半導体リー
ド、２ｂは本曲げにより最終形状となった半導体リード
である。BEST MODE FOR CARRYING OUT THE INVENTION The semiconductor lead molding method of the present invention will be described in detail below with reference to the drawings. 1 and 2 are explanatory views of the principle of the method of the present invention. In the figure, 1 is a semiconductor package, 2 is a semiconductor lead, 2'is a lead root part, 3 is a bending punch, 4 is a forming part of the bending punch 3, 5 is a knockout plate (upper die pressing member), 6 is a forming die, Reference numeral 7 is a gap, 2a is a semiconductor lead bent by preliminary bending, and 2b is a semiconductor lead having a final shape by main bending.
【００１０】本発明によれば、公知方法により予備曲げ
が施されている半導体パッケージ１の半導体リード２が
成形の対象とされる。すなわち、半導体リード２は、予
備曲げにより予め根本部から下方斜めに折曲げられてい
る。図３は半導体パッケージ１から水平に出ている半導
体リード２を予備曲げする方法の一例を示すもので、
（ａ）は予備曲げ前の状態、（ｂ）は予備曲げ後の状態
を示す。図中、８は予備曲げパンチ、９はリードフレー
ムである。この予備曲げでは、予備曲げパンチ８を垂直
下方に降ろして、半導体リード２の根本部から下方斜め
に成形する。According to the present invention, the semiconductor lead 2 of the semiconductor package 1 which has been pre-bent by a known method is targeted for molding. That is, the semiconductor lead 2 is previously bent obliquely downward from the root portion by preliminary bending. FIG. 3 shows an example of a method of pre-bending the semiconductor lead 2 which is horizontally projected from the semiconductor package 1.
(A) shows the state before pre-bending and (b) shows the state after pre-bending. In the figure, 8 is a pre-bending punch, and 9 is a lead frame. In this pre-bending, the pre-bending punch 8 is vertically lowered and is formed obliquely downward from the root of the semiconductor lead 2.
【００１１】本発明では、上記のような成形対象に対し
て以下のような条件で本曲げが行われる。 (1）半導体パッケージ１を成形ダイ６の上に載置した
後、上金型下降によりノックアウトプレート５との間に
固定支持する。この時、半導体リード２の根本部２’に
おいて、ある量の隙間７が形成されるようにする。 (2）成形ダイ６としては、リードの最終形状に対応した
成形部を有するものを使用する。また、曲げパンチ３と
して、リードの最終形状に対応した成形部４を先端に有
するものを使用する。 (3）曲げパンチ３の成形部４の先端をリード２（２ａ）
上の特定点Ｐｓに当接させ、曲げパンチ３を最終形状に
おけるリード２（２ｂ）の曲げ部Ｐｅに向かう直線方向
に押圧し、該点Ｐｅに到達させる。この時、曲げ部は図
２のＡの円弧軌跡（中心点は予備曲げの折曲点）を描い
て点Ｐｓから点Ｐｅに達するようにする。従って、上記
特定点Ｐｓは、予備曲げの折曲点を中心に点Ｐｅまでの
長さを半径とする円Ａを描いたときに、この円Ａと予備
曲げされたリード２ａとの交点として設定できる。曲げ
パンチ３は点Ｐｓと点Ｐｅを結ぶ直線、すなわち円弧軌
跡の弦に沿って直線的に移動することになる。なお、図
中θは半導体リード２の予備曲げの折曲角度、ｄは円弧
と直線の動きの差を示している。In the present invention, the main bending is performed on the above-mentioned forming object under the following conditions. (1) After the semiconductor package 1 is placed on the molding die 6, it is fixedly supported between the semiconductor package 1 and the knockout plate 5 by lowering the upper die. At this time, a certain amount of gap 7 is formed in the root portion 2'of the semiconductor lead 2. (2) As the molding die 6, one having a molding portion corresponding to the final shape of the lead is used. Further, as the bending punch 3, one having a molding portion 4 corresponding to the final shape of the lead at the tip is used. (3) Lead 2 (2a) at the tip of forming part 4 of bending punch 3.
The bending punch 3 is brought into contact with the specific point Ps above, and is pressed in the linear direction toward the bent portion Pe of the lead 2 (2b) in the final shape to reach the point Pe. At this time, the bending portion draws an arc locus of A in FIG. 2 (the center point is a bending point for preliminary bending) so as to reach the point Pe from the point Ps. Therefore, the specific point Ps is set as an intersection of the circle A and the pre-bent lead 2a when the circle A having the radius up to the point Pe as the radius is drawn around the bending point of the pre-bend. it can. The bending punch 3 moves linearly along the straight line connecting the points Ps and Pe, that is, along the chord of the arc locus. In the figure, θ represents the bending angle of the preliminary bending of the semiconductor lead 2, and d represents the difference between the movement of the arc and the straight line.
【００１２】上記において、リード根本部２’において
形成する隙間７の量は半導体パッケージ１のソリ量に応
じて設定することが好ましい。In the above, the amount of the gap 7 formed in the lead root portion 2'is preferably set according to the amount of warpage of the semiconductor package 1.
【００１３】従来のしごき曲げの方法、ローラによる方
法、可動ダイによる方法において、上記のように半導体
リードの根本部位において隙間を形成した状態で成形を
すると、リードが引っ張られるため、リードがパッケー
ジから抜けるリード抜けやリードの根本側が開いてしま
う口開きが起きてしまう。これに対して、本発明の成形
方法によれば、曲げパンチが斜め上方から降りてきてス
ライド曲げをするため、隙間を形成して成形してもリー
ドが引っ張られることがないため、リード抜けや口開き
は起こらず、成形後も半導体パッケージの変形がなく、
ソリが大きな半導体パッケージに対してもリードの平坦
性は非常に良好なものとなる。また、本発明の方法によ
れば、成形の際の曲げパンチ３による擦れはごくわずか
であり、リード表面のハンダが削りとられるほどの擦れ
はなく、ハンダカスは殆ど生じない。In the conventional ironing and bending method, roller method, and movable die method, when molding is performed with a gap formed at the base portion of the semiconductor lead as described above, the lead is pulled, so that the lead is removed from the package. There will be a lead dropout or a mouth opening that opens the root side of the lead. On the other hand, according to the molding method of the present invention, since the bending punch descends obliquely from above and performs slide bending, the lead is not pulled even when forming a gap, and therefore, the lead is not pulled out or dropped. Opening does not occur, there is no deformation of the semiconductor package even after molding,
Even for a semiconductor package having a large warp, the flatness of the leads is very good. Further, according to the method of the present invention, the rubbing by the bending punch 3 at the time of molding is very small, there is no rubbing such that the solder on the lead surface is scraped off, and almost no solder residue occurs.
【００１４】[0014]
【発明の効果】本発明によれば、前記のような方法を採
用したので、以下のような顕著なる効果が得られる。 (1）スライド曲げを行っているので、曲げパンチによる
擦れはごくわずかであり、ハンダカスの発生が効果的に
防止できる。 (2）成形時に半導体パッケージを変形させないため、ソ
リがある半導体パッケージを成形対象としても、成形後
のリードの平坦性が非常に良好となる。 (3）隙間を形成して成形しても、リードの引っ張りはな
く、リード抜けや口開きが起こらない。 (4）成形時にリード根本部を挟み込まないものの、曲げ
パンチの力がリード曲げ部分の全箇所で板厚方向に加わ
るので、リード先端部におけるスプリングバックの量が
安定し、曲げ精度が向上する。 (5）半導体パッケージのソリの影響を受けずにリード成
形を行えるため、精度向上が計れ、歩留まりを大きくで
きる。According to the present invention, since the above method is adopted, the following remarkable effects can be obtained. (1) Since slide bending is performed, the rubbing by the bending punch is very small, and the generation of solder residue can be effectively prevented. (2) Since the semiconductor package is not deformed during molding, the flatness of the leads after molding is very good even when a semiconductor package with warpage is targeted for molding. (3) Even if a gap is formed, the lead will not be pulled and the lead will not come off or open. (4) Although the lead root portion is not sandwiched during molding, the bending punch force is applied in the plate thickness direction at all points of the lead bending portion, so the amount of springback at the lead tip is stable and bending accuracy is improved. (5) Since lead molding can be performed without being affected by warping of the semiconductor package, accuracy can be improved and yield can be increased.
【図１】本発明の半導体リード成形方法の原理説明図で
ある。FIG. 1 is an explanatory view of the principle of a semiconductor lead molding method of the present invention.
【図２】本発明の半導体リード成形方法の原理説明図で
ある。FIG. 2 is an explanatory view of the principle of the semiconductor lead molding method of the present invention.
【図３】予備曲げ方法の説明図で、（ａ）は予備曲げ前
の状態、（ｂ）は予備曲げ後の状態を示す。FIG. 3 is an explanatory view of a pre-bending method, (a) shows a state before the pre-bending, and (b) shows a state after the pre-bending.
【図４】リードのガルウイング曲げの説明図で、（ａ）
は正面図、（ｂ）は斜視図である。FIG. 4 is an explanatory view of the gull wing bending of the lead, (a)
Is a front view and (b) is a perspective view.
【図５】（ａ）はソリの生じた半導体パッケージを示す
斜視図、（ｂ）は従来の成形法の説明図である。5A is a perspective view showing a warped semiconductor package, and FIG. 5B is an explanatory view of a conventional molding method.
１ 半導体パッケージ ２ 半導体リード ２’リード根本部 ３ 曲げパンチ ４ 成形部 ５ ノックアウトプレート（上金型押さえ部材） ６ 成形ダイ ７ 隙間 1 semiconductor package 2 semiconductor lead 2'lead root part 3 bending punch 4 molding part 5 knockout plate (upper die pressing member) 6 molding die 7 gap
Claims (2)
に折曲げられた半導体リードを有する半導体パッケージ
を、リードの最終形状に対応した成形部を有する成形ダ
イと上金型押さえ部材との間に、リード根本部の位置に
おいて隙間を設けた状態で支持し、リードの最終形状に
対応した形状の成形部を先端に有する曲げパンチを、前
記予備曲げされたリードに対してリードの曲げ部が描く
円弧軌跡の弦とほぼ同一直線方向に押圧することにより
該リードをガルウイング曲げすることを特徴とする半導
体リード成形方法。1. A semiconductor package having a semiconductor lead, which is preliminarily bent from a root portion in a diagonally downward direction, is provided between a molding die having a molding portion corresponding to a final shape of the lead and an upper die pressing member. , A lead punch draws a bending punch, which is supported at a position of the lead root portion with a gap provided, and has a forming portion having a shape corresponding to the final shape of the lead at the tip, with respect to the pre-bent lead. A method of molding a semiconductor lead, characterized in that the lead is gull-wing bent by pressing in a direction substantially the same as the chord of an arc locus.
を、半導体パッケージのソリの量に応じて設定すること
を特徴とする請求項１に記載の半導体リード成形方法。2. The semiconductor lead molding method according to claim 1, wherein the amount of the gap at the position of the lead root portion is set according to the amount of warpage of the semiconductor package.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8040704A JPH09213860A (en) | 1996-02-02 | 1996-02-02 | Semiconductor lead forming method |
| TW085115435A TW315516B (en) | 1996-02-02 | 1996-12-13 | |
| KR1019960072084A KR100331292B1 (en) | 1996-02-02 | 1996-12-26 | Method of bending leads of semiconductor package |
| SG1997000042A SG64415A1 (en) | 1996-02-02 | 1997-01-10 | Method of bending leads of semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8040704A JPH09213860A (en) | 1996-02-02 | 1996-02-02 | Semiconductor lead forming method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09213860A true JPH09213860A (en) | 1997-08-15 |
Family
ID=12587970
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8040704A Pending JPH09213860A (en) | 1996-02-02 | 1996-02-02 | Semiconductor lead forming method |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPH09213860A (en) |
| KR (1) | KR100331292B1 (en) |
| SG (1) | SG64415A1 (en) |
| TW (1) | TW315516B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102916155A (en) * | 2012-10-23 | 2013-02-06 | 东莞新能源科技有限公司 | Equipment for reducing back steps of winding type flexibly packaged battery cell |
-
1996
- 1996-02-02 JP JP8040704A patent/JPH09213860A/en active Pending
- 1996-12-13 TW TW085115435A patent/TW315516B/zh active
- 1996-12-26 KR KR1019960072084A patent/KR100331292B1/en not_active IP Right Cessation
-
1997
- 1997-01-10 SG SG1997000042A patent/SG64415A1/en unknown
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102916155A (en) * | 2012-10-23 | 2013-02-06 | 东莞新能源科技有限公司 | Equipment for reducing back steps of winding type flexibly packaged battery cell |
Also Published As
| Publication number | Publication date |
|---|---|
| KR970063596A (en) | 1997-09-12 |
| KR100331292B1 (en) | 2002-06-20 |
| SG64415A1 (en) | 1999-04-27 |
| TW315516B (en) | 1997-09-11 |
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