JPH09213086A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a flash EEPROM in which the power consumption is little, the operation speed is fast, and the circuit scale is small. SOLUTION: In a bit deleting mode, potentials of a common source line SL and a bit line BLn are made aground level, +5V is supplied to a bit line BL. m+15V is supplied to a word line WLm, and the potential of a word line WLn is made ground level. Deleting operation of performed for a memory cell 1c. For a memory cell 1a, electrons in a floating gate FG is not extracted to the control gate CG side, and deleting operation is not performed, Deleting operation is not performed for a memory cell 1d, too. For a memory cell 1b, as a channel CH is in a OFF state, both of writing operation and deleting operation are not performed. Therefore, deleting operation is performed for only arbitrary memory cell by controlling a potential of a floating gate FG for each memory cell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art In recent years, FRAM (Ferro-electric Rando)
m Access Memory), EPROM (Erasable and Progr
ammable Read Only Memory), EEPROM (Electric
Non-volatile semiconductor memory such as al Erasable and Programmable Read Only Memory) is drawing attention. EPRO
In M and EEPROM, data is stored by storing charge in a floating gate and detecting a change in threshold voltage due to the presence or absence of a charge by a control gate. The EEPROM includes a flash EEPROM that erases data in the entire memory chip or divides the memory cell array into arbitrary blocks and erases data in each block.

The flash EEPROM has advantages such as (1) non-volatility of stored data, (2) low power consumption, (3) electric rewriting (on-board rewriting), and (4) low cost. , As a memory for storing programs and data in mobile phones and personal digital assistants,
Its range of use is expanding more and more.

Flash EEPROMs are roughly classified into split gate type and stacked gate type. Conventionally, a split gate type flash EEPROM disclosed in USP 5202850 (G11C 11/40) has been proposed.

FIG. 21 shows a sectional structure of a split gate type memory cell 101 described in the publication. An N type source S and a drain D are formed on a P type single crystal silicon substrate 102. On the channel CH sandwiched between the source S and the drain D, the floating gate FG is formed via the first insulating film 103. The control gate CG is formed on the floating gate FG via the second insulating film 104. A part of the control gate CG is arranged on the channel CH via the first insulating film 103 and constitutes the select gate 105.

FIG. 22 shows a flash EE using the split gate type memory cell 101 described in the publication.
1 shows the overall configuration of a PROM 121. Memory cell array 1
Reference numeral 22 denotes a configuration in which a plurality of memory cells 101 are arranged in a matrix. The control gates CG of the memory cells 101 arranged in the row direction are connected to the common word lines WLa to WLz. The drain D of each memory cell 101 arranged in the column direction
Are connected to common bit lines BLa to BLz.
Sources S of all memory cells 101 are common source lines SL
It is connected to the.

Each word line WLa-WLz is connected to a row decoder 123, and each bit line BLa-BLz is connected to a column decoder 124. The row address and column address specified from outside are
25. The row address and the column address are transferred from the address pin 125 to the address buffer 12
6 to the address latch 127. Of the addresses latched by the address latch 127, the row address is transferred to the row decoder 123, and the column address is transferred to the column decoder 124. The row decoder 123 selects one word line WLa to WLz corresponding to the row address, and controls the potential of the selected word line corresponding to each operation mode, as described later. The column decoder 124 selects the bit lines BLa to BLz corresponding to the column address, and controls the potential of the selected bit line corresponding to each operation mode, as described later.

Data designated externally is input to the data pin 128. The data is the data pin 128.
From the column decoder 124 via the input buffer 129
Transferred to The column decoder 124 controls the potentials of the bit lines BLa to BLz selected as described above in accordance with the data, as described later.

Data read from an arbitrary memory cell 101 is transferred from the bit lines BLa to BLz to the sense amplifier group 130 via the column decoder 124. The sense amplifier group 130 includes several sense amplifiers (not shown).
It is composed of The column decoder 124 connects the selected bit lines BLa to BLz to each sense amplifier. As will be described later, the data determined by the sense amplifier group 130 is transferred from the output buffer 131 to the data pin 128.
Is output to the outside via.

The operation of each of the circuits (123 to 131) is controlled by a control core circuit 132. next,
Each operation mode (word line erase mode, write mode, read mode) of the flash EEPROM 121 will be described with reference to FIG.

(A) Word line erase mode In the word line erase mode, all bit lines BLa ...
The potential of BLz is held at the ground level (= 0V). Also, the potential of the common source line SL is held at the ground level. + 15V is supplied to the selected word line WLm, and the other word lines (non-selected word lines) W
The potentials of La to WLl and WLn to WLz are set to the ground level. Therefore, the control gate CG of each of the memory cells 101a and 101c connected to the selected word line WLm is raised to + 15V.

By the way, comparing the capacitance between the floating gate FG and the drain D with the capacitance between the control gate CG and the floating gate FG, the former is overwhelmingly larger. Therefore, when the control gate CG is + 15V and the drain is 0V, a high electric field is generated between the control gate CG and the floating gate FG. As a result, the Fowler-Nordheim Tunnel Current,
Hereinafter, an FN tunnel current) flows, electrons in the floating gate FG are extracted to the control gate CG side, and the data stored in the memory cells 101a and 101c are erased.

This erase operation is performed for all the memory cells 1 connected to the selected one word line WLa to WLz.
01. In addition, a plurality of word lines WLa to W
By selecting Lz at the same time, the erase operation can be performed on all the memory cells 101 connected to each word line. Such an erase operation is called block erase.

(B) Write Mode In the write mode, the potential of the common source line SL is held at the ground level. Selected memory cell 10
+ 1V is supplied to the word line WLm connected to the control gate CG of 1a, and the other word lines (non-selected word lines) WLa to WLl and WLn to WLz.
Is set to the ground level. Bit line BL connected to the drain D of the selected memory cell 101a
+ 12V is supplied to m, and the potentials of the other bit lines (non-selected bit lines) BLa to BLl and BLn to BLz are set to the ground level.

By the way, the threshold voltage of the memory cell 101 is + 1V. Therefore, the selected memory cell 101a
Then, the control gate CG becomes near the threshold voltage,
The electrons in the source S move into the weakly inverted channel CH. On the other hand, since + 12V is applied to the drain D, the potential of the floating gate FG is raised by the coupling. Therefore, a high electric field is generated between the control gate CG and the floating gate FG. Therefore, the electrons in the channel CH are accelerated and become hot electrons, which are injected into the floating gate FG.
As a result, negative charges are accumulated in the floating gate FG of the selected memory cell 101a, and 1-bit data is written and stored.

This writing operation is different from the erasing operation.
This can be performed for each selected memory cell 101. (C) Read Mode In the read mode, the potential of the common source line SL is held at the ground level. Selected memory cell 10
+ 5V is supplied to the word line WLm connected to the control gate CG of 1a, and the other word lines (non-selected word lines) WLa to WLl and WLn to WLz.
Is set to the ground level. Bit line BL connected to the drain D of the selected memory cell 101a
+ 2V is supplied to m, and the other bit lines (non-selected bit lines) BLa to BLl and BLn to BLz are set to the ground level.

As described above, since electrons are extracted from the floating gate FG of the memory cell 101 in the erased state, the floating gate FG is positively charged. Further, since electrons are injected into the floating gate FG of the memory cell 101 in the written state, the floating gate FG is negatively charged. Therefore, the memory cell 1 in the erased state
The channel CH immediately below the floating gate FG of 01 is on, and the channel CH immediately below the floating gate FG of the memory cell 101 in the written state is off. Therefore, when +5 V is applied to the control gate CG, the current (cell current) flowing from the drain D to the source S is larger in the erased memory cell 101 than in the written memory cell 101.

By discriminating the magnitude of the cell current between the memory cells 101 by each sense amplifier in the sense amplifier group 130, the value of the data stored in the memory cell 101 can be read. For example, reading is performed with the data value of the memory cell 101 in the erased state set to “1” and the data value of the memory cell 101 in the written state set to “0”.

Unlike the erase operation, this read operation is different from
This can be performed for each selected memory cell 101.

[0020]

Conventional flash EE
The erase operation of the PROM is performed on all the memory cells 101 connected to the same word line WLa to WLz. That is, the erase operation can be performed only in units of word lines WLa to WLz, and the erase operation cannot be performed for each memory cell 101.

Therefore, when performing an erase operation on an arbitrary memory cell 101, first, the memory cell 101 is erased.
It is necessary to perform an erase operation on all the memory cells 101 connected to the same word line WLm and then rewrite the original data to each memory cell 101 other than the arbitrary memory cell 101. there were.

As described above, when erasing the data stored in any memory cell 101, the erasing operation which is originally unnecessary for the other memory cells 101 which do not need to erase the stored data. Since the write operation is performed, there are the following problems.

[A] The durability of another memory cell 101 which does not need to erase stored data is reduced. There is a limit to the number of times data can be rewritten in the flash EEPROM memory cell. This is because electrons have to be taken in and out of the floating gate FG in the erase operation and the write operation, and the electrons are taken in by the insulating films 104 and 1.
Because you have to go through 03. Therefore, the characteristics of the insulating film 104 deteriorate each time the erase operation is performed, and the characteristics of the insulating film 103 deteriorate each time the write operation is performed. When the characteristics of the insulating films 104 and 103 are deteriorated to a certain extent or more, erasing and writing defects occur, which hinders data storage.

[B] Since an erasing operation and a writing operation, which are originally unnecessary, are performed, the flash EEPROM is correspondingly used.
The power consumption of 121 increases. [C] Since the erase operation and the write operation, which are originally unnecessary, are performed, the operation speed of the flash EEPROM 121 is reduced accordingly.

[D] Since the control of the erase operation and the write operation is complicated, the load on the control core circuit 132 increases. Therefore, the circuit scale of the control core circuit 132 is increased and the operation speed is reduced.

The present invention has been made to solve the above problems and has the following objects. 1] To provide a nonvolatile semiconductor memory device having excellent durability.

2) To provide a nonvolatile semiconductor memory device with low power consumption. 3) To provide a nonvolatile semiconductor memory device having a high operation speed. 4) To provide a nonvolatile semiconductor memory device having a small circuit scale.

[0028]

The gist of the invention according to claim 1 is that the erase operation is performed only on an arbitrary memory cell by controlling the potential of the floating gate for each memory cell. .

According to a second aspect of the present invention, each memory cell (1) is composed of a floating gate (FG), a control gate (CG), a source (S), a drain (D) and a channel (CH), and its memory cell (1). By controlling the potential of the floating gate for each memory cell, a control circuit (123, 12) that performs an erase operation only for an arbitrary memory cell
4, 132) is provided.

According to a third aspect of the present invention, each memory cell (1) is composed of a floating gate (FG), a control gate (CG), a source (S), a drain (D) and a channel (CH), and its memory cell (1). By controlling the potential of the floating gate for each memory cell, a write operation is performed on a certain memory cell, and at the same time, an erase operation is performed on another certain memory cell, and both write and erase operations are performed. For memory cells that are not needed, the control circuit (123, 1) that keeps the previous state as it is.
24, 132).

According to a fourth aspect of the present invention, in the non-volatile semiconductor memory device according to the second or third aspect, the control gate of each memory cell for controlling the potential of the floating gate has a common word line (WLm). ) Is to be connected to the gist.

According to a fifth aspect of the present invention, each memory cell (1) comprising a floating gate (FG), a control gate (CG), a source (S), a drain (D) and a channel (CH), and its memory cell (1). By controlling the potential of the floating gate for each memory cell, a control circuit (123, 12) that performs an erase operation only for an arbitrary memory cell
4, 132), the control gate of each memory cell controlling the potential of the floating gate is connected to a common word line (WLm), and is connected to the common word line and does not perform an erase operation. For (1a), the bit line (BL
The gist of the invention is to control the potential of m) to a high value such that Fowler-Nordheim tunnel current does not flow between the floating gate and the control gate.

According to a sixth aspect of the present invention, each memory cell (1) comprises a floating gate (FG), a control gate (CG), a source (S), a drain (D) and a channel (CH), and the memory cell (1). By controlling the potential of the floating gate for each memory cell, a write operation is performed on a certain memory cell, and at the same time, an erase operation is performed on another certain memory cell, and both write and erase operations are performed. For memory cells that are not needed, the control circuit (123, 1) that keeps the previous state as it is.
24, 132), the control gate of each memory cell for controlling the potential of the floating gate is connected to a common word line (WLm), and the write operation and the erase operation connected to the common word line are performed. For the unnecessary memory cell (1a), the potential of the bit line (BLm) to which the drain is connected is set to a high value such that the Fowler-Nordheim tunnel current does not flow between the floating gate and the control gate. The point is to control.

According to a seventh aspect of the present invention, each memory cell (1) is composed of a floating gate (FG), a control gate (CG), a source (S), a drain (D) and a channel (CH), and the memory cell (1). By controlling the potential of the floating gate for each memory cell, a write operation is performed on a certain memory cell, and at the same time, an erase operation is performed on another certain memory cell, and both write and erase operations are performed. For memory cells that are not needed, the control circuit (123, 1) that keeps the previous state as it is.
24, 132), the control gates of the respective memory cells for controlling the potential of the floating gate are connected to a common word line (WLm), and the memory cells connected to the common word line to perform a write operation ( 1e)
For the bit line (BL
The gist of the invention is to control the potential m) to a high value such that a high electric field is generated between the floating gate and the control gate and hot electrons are injected from the channel to the floating gate.

According to an eighth aspect of the present invention, each memory cell (1) is composed of a floating gate (FG), a control gate (CG), a source (S), a drain (D) and a channel (CH), and the memory cell (1). By controlling the potential of the floating gate for each memory cell, a write operation is performed on a certain memory cell, and at the same time, an erase operation is performed on another certain memory cell, and both write and erase operations are performed. For memory cells that are not needed, the control circuit (123, 1) that keeps the previous state as it is.
24, 132), the control gate of each memory cell for controlling the potential of the floating gate is connected to a common word line (WLm), and the write operation and the erase operation connected to the common word line are performed. For the unnecessary memory cell (1a), the potential of the bit line (BLm) to which the drain is connected is set to a high value such that the Fowler-Nordheim tunnel current does not flow between the floating gate and the control gate. For the memory cell (1e) which is controlled and connected to the common word line to perform the write operation, the potential of the bit line (BLm) to which the drain is connected is set high between the floating gate and the control gate. An electric field is generated and hot electrons are injected from the channel to the floating gate. To control to a higher value of the degree as its gist.

According to a ninth aspect of the present invention, in the nonvolatile semiconductor memory device according to any one of the second to eighth aspects, a cell current flowing from the drain to the source is generated by controlling the potential of the source. It is the gist to prevent.

The invention according to claim 10 is the invention according to claims 2 to 8.
In the nonvolatile semiconductor memory device according to any one of items 1 to 3, the source is in a floating state, and the generation of a cell current flowing from the drain to the source is prevented.

The invention according to claim 11 is the invention according to claims 2 to 8.
In the nonvolatile semiconductor memory device according to any one of items 1 to 5, it is possible to prevent the generation of a cell current flowing from the drain to the source by simultaneously controlling the potentials of the sources of the memory cells arranged in the column direction. Use as a summary.

The invention according to claim 12 is the invention according to claims 2 to 8.
In the non-volatile semiconductor memory device according to any one of items 1 to 3, the generation of a cell current flowing from the drain to the source is prevented by separately controlling the potential of the source for each memory cell arranged in the column direction. Is the gist.

The invention described in claim 13 is the invention according to claims 1 to 1.
3. The nonvolatile semiconductor memory device according to any one of 2 above, by monitoring a cell current flowing from a drain to a source, the amount of charge accumulated in the floating gate is controlled to detect the end of the erase operation. This is the gist.

The invention described in claim 14 relates to claims 1 to 1.
In the nonvolatile semiconductor memory device according to any one of 3 above, by controlling the amount of charges accumulated in a floating gate for each memory cell, a multivalued data is stored in the memory cell. To do.

The invention described in claim 15 is the invention according to claims 1 to 1.
In the nonvolatile semiconductor memory device according to any one of Items 4 to 4, the gist is to control the potential of the floating gate by controlling the potentials of the drain, source, and control gate, respectively.

According to a sixteenth aspect of the present invention, in the nonvolatile semiconductor memory device according to the fifteenth aspect, the potential of the floating gate is controlled by the potential of the bit line connected to the drain and the source connected to the source. The gist of this is to control the potential of the line and the potential of the word line to which the control gate is connected, respectively.

The invention according to claim 17 is the invention according to claims 1 to 1.
In the nonvolatile semiconductor memory device according to any one of 6), the gist is that the memory cell is a split gate type or a stacked gate type.

The "control circuit" in the claims and means for solving the problems comprises a row decoder 123, a column decoder 124, and a control core circuit 132 in the embodiments of the invention described below.

[0046]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments in which the present invention is embodied in a split gate type flash EEPROM will be described below with reference to the drawings. The structure of the split gate type memory cell 1 in each embodiment is the same as that of the conventional embodiment shown in FIG.

(First Embodiment) A first embodiment will be described below with reference to the drawings. Flash EEPR of this embodiment
The overall configuration of the OM21 is the same as the conventional configuration shown in FIG. In this embodiment, only the operation of the control core circuit 132 is different from the conventional form.

The flash EEPROM 21 of this embodiment
Each operation mode (word line erase mode, write mode, read mode, standby mode, bit erase mode) will be described with reference to FIGS. 23 and 1.

The (a) word line erase mode, (b) write mode, and (c) read mode are the same as those of the conventional embodiment shown in FIG. (D) Standby Mode In the standby mode, the common source line SL, all word lines WLa to WLz, and all bit lines BLa to BL
The potential of z is kept at the ground level. In this standby mode, no operation (erase operation, write operation, read operation) is performed on all the memory cells 1.

(E) Bit erase mode In the bit erase mode, the potential of the common source line SL is held at the ground level. Here, only the data stored in the selected memory cell 1c is erased, and the other memory cells (non-selected memory cells) 1a, 1b,
An example will be described in which the data stored in 1d is not erased.

The potential of the bit line BLn connected to the drain D of the memory cell 1c is set to the ground level, and the other bit lines (non-selected bit lines) BLa to BL.
+ 5V is supplied to m and BLo to BLz. Further, + 15V is supplied to the word line WLm connected to the control gate CG of the memory cell 1c, and the other word lines (non-selected word lines) WLa to WLl, WLn.
The potential of WLz is set to the ground level.

Since the memory cell 1c has the same conditions as the above-mentioned (a) word line erase mode, the stored data is erased. In addition, the memory cell 1c
With respect to the other memory cells 1a connected to the same word line WLm, + 5V is applied to the drain D, so that the potential of the floating gate FG is raised by the coupling. Therefore, control gate C
Even if + 15V is applied to G, the potential difference between the control gate CG and the floating gate FG of the memory cell 1a does not become so large that an FN tunnel current flows. Therefore, the electrons in the floating gate FG are not extracted to the control gate CG side, and the memory cell 1a
The data stored in is not erased.

Further, the same bit line BL as the memory cell 1c
The other memory cell 1d connected to n has the same condition as the above-mentioned (d) standby mode.
The stored data is not erased.

In addition, unselected bit lines BLa to BLm,
BLo to BLz and word lines WLa to WLl, WLn
For memory cells 1b connected to ~ WLz,
Since + 5V is applied to the drain D, the potential of the floating gate FG is raised by the coupling. However, the word lines WLa to WLl and WLn to WLz
Since the potential of is at the ground level, the channel CH of the memory cell 1b is off. Therefore, the memory cell 1b
At the channel CH to the floating gate FG
No hot electrons are injected into and no data is written.

As described above, according to this embodiment, the following actions and effects can be obtained. (1) Only the selected memory cell 1c can be erased. That is, the erase operation can be performed for each selected memory cell 1 (that is, for each bit). Therefore, when erasing the data stored in an arbitrary memory cell 1, it is possible to perform unnecessary erasing and writing operations on other memory cells 1 that do not need to erase the stored data. Good. Therefore, the following effects can be obtained.

(2) The durability of the other memory cells 1 which do not need to erase the stored data does not deteriorate. (3) Since unnecessary erase operation and write operation are not performed, the power consumption of the flash EEPROM 21 does not increase.

(4) Since unnecessary erase and write operations are not performed, the operating speed of the flash EEPROM 21 does not decrease. (5) Since the control of the erase operation and the write operation is simple, the load on the control core circuit 132 is small. for that reason,
The circuit scale of the control core circuit 132 can be reduced, and the operation speed can be improved.

(6) Conventional flash EEPROM 12
In No. 1, the erase operation could be performed only in units of word lines WLa to WLz, and the erase operation could not be performed for each memory cell. In other words, conventional flash EEPR
In the OM121, the data could not be rewritten in 1-bit units. On the other hand, DRAM and SRAM
In, data can be rewritten in 1-bit units. Therefore, the conventional flash EEPROM 121 is
When it is replaced with RAM or SRAM, the rewriting unit of data is greatly different, and thus it is difficult to use. However, in the flash EEPROM 21 of the present embodiment, since data can be rewritten in 1-bit units,
Easy to use even when replaced with DRAM or SRAM,
The applications of DRAM and SRAM can be covered.

In the (e) bit erase mode, the following conditions must be satisfied for the potential (+5 V in the above embodiment) supplied to the non-selected bit lines BLa to BLm and BLo to BLz.

(1) The potential is so high that the FN tunnel current does not flow between the control gate CG and the floating gate FG of the memory cell 1a. (2) The potential is so low that hot electrons are not injected from the channel CH of the memory cell 1a to the floating gate FG.

(3) The potential is so low that the FN reverse tunnel current does not flow between the control gate CG and the floating gate FG of the memory cell 1b. (4) In order to reduce the current (cell current) flowing from the drain D to the source S of the memory cell 1a, the potential should be low within the range of the above condition (1). That is, the source S of the memory cell 1a is set to the ground level and the drain D
Is applied to + 5V, and + 15V is applied to the control gate CG. Therefore, when the floating gate FG rises to about + 5V due to coupling, the channel CH of the memory cell 1a turns on and a cell current flows.
However, since the potential of the floating gate FG is low and the cell current is determined by the state of the channel CH under the floating gate FG, only a cell current of the same level as in the read mode flows in the bit erase mode.

(Second Embodiment) Next, a second embodiment will be described with reference to the drawings. In this embodiment, the same components as those in the first embodiment have the same reference numerals, and a detailed description thereof will be omitted.

In this embodiment, the same word lines WLa to W are used.
In the plurality of memory cells 1 connected to Lz, a write operation is performed on a certain memory cell 1 and at the same time, an erase operation is performed on another certain memory cell 1. Further, the memory cell 1 which does not need to perform the writing operation and the erasing operation retains the previous state.

The write and bit erase modes of this embodiment will be described with reference to FIGS. Other operation modes of this embodiment (word line erase mode,
Read mode, standby mode)
This is the same as the flash EEPROM 21 of the embodiment.

As shown in FIG. 2, the potential of the common source line SL is held at the ground level. Here, each memory cell 1a, 1c, 1 connected to the same word line WLm
In e, the case where neither the writing operation nor the erasing operation is performed on the memory cell 1a, the erasing operation is performed on the memory cell 1c, and the writing operation is performed on the memory cell 1e will be described as an example. Word lines other than the word line WLm (non-selected word lines) WLa to WLl, WLn to W
Each memory cell 1 (1b, 1d, 1 connected to Lz
For f), neither write operation nor erase operation is performed, and the state before that is retained as it is.

Similar to (a) the bit erase mode of the first embodiment, + 5V is supplied to the bit line BLm, + 15V is supplied to the word line WLm, and the potentials of the bit line BLn and the word line WLn are at the ground level. To be Then, + 12V is supplied to the bit line BLo.

As a result, the memory cells 1a to 1d have the same conditions as the (a) bit erase mode of the first embodiment. Further, with respect to the memory cell 1e connected to the bit line BLo, + 12V is applied to the drain D, so that the potential of the floating gate FG is raised by the coupling. Therefore, a high electric field is generated between the control gate CG and the floating gate FG. Further, since the potential of the word line WLm is + 15V, the channel CH of the memory cell 1e is on. Therefore, in the memory cell 1e, the electrons in the channel CH are accelerated, become hot electrons, and are injected into the floating gate FG to perform the write operation.

That is, assuming that the data value of the memory cell 1 in the erased state is "1" and the data value of the memory cell 1 in the written state is "0", it is already stored in the memory cell 1 as shown in FIG. The potentials of the bit lines BLa to BLz are determined from the stored data (previous data) and the data to be newly written (write data). Therefore, after setting the potentials of the bit lines BLa to BLz as shown in FIG. 3, the potentials of the selected word lines WLa to WLz are +15.
If the voltage is raised to V, as described above, the write operation and the erase operation can be performed at the same time. Further, the memory cell 1 which does not need to perform the writing operation and the erasing operation can retain the previous state as it is.

FIG. 4 shows the flash EEPR of this embodiment.
The whole structure of OM31 is shown. The 1-byte write data (write data) specified from the outside is the data pin 1
28 to the write data latch 32 via the input buffer 129. The write data latched by the write data latch 32 is transferred to the data comparator 33 and the internal write data generation circuit 34.

One byte of read data (read data) is read from any eight memory cells 1 connected to the same word line WLa to WLz. The read data is transferred from each bit line BLa to BLz to the sense amplifier group 130 via the column decoder 124.
The read data determined by the sense amplifier group 130 is transferred to the read data latch 35 and the output buffer 131. The read data latched by the read data latch 35 is transferred to the data comparator 33.

As will be described later, the data comparator 33 compares the corresponding bits of the write data and the read data to generate 1-byte mask data. The mask data latch 36 latches the mask data, and the mask data is transferred to the internal write data generation circuit 34.

The internal write data generation circuit 34 determines the potentials of the bit lines BLa to BLz based on the write data and the mask data, as described later. The column decoder 124 controls the potentials of the bit lines BLa to BLz according to the determination of the internal write data generation circuit 34.

The above circuits (32 to 36, 123)
Operations 131 to 131) are controlled by the control core circuit 132. Next, the write and bit erase modes of this embodiment will be described with reference to FIGS.

FIG. 5 is a flow chart of the write and bit erase modes. First, in step (S) 1, the row address and column address input to the address pin 125 are transferred to the address latch 127 via the address buffer 126, and the address latch 12
Latched at 7. Then, the process proceeds to S2.

In S2, the pre-read operation is performed. That is, of the addresses latched by the address latch 127, the row address is transferred to the row decoder 123 and the column address is transferred to the column decoder 124. The row decoder 123 selects one word line WLa to WLz (for example, WLm) corresponding to the row address. The column decoder 124 has eight bit lines BLa to BLz (for example,
BLm to BLt). And the word line WLm
1 byte of read data is read from the eight memory cells 1 connected to the bit lines BLm to BLt. The read data is the bit lines BLm to BL.
Sense amplifier group 1 from t via the column decoder 124
30 is transferred. The read data determined by the sense amplifier group 130 is latched by the read data latch 35. Then, the process proceeds to S3.

In S 3, the 1-byte write data input to the data pin 128 is transferred to the write data latch 32 via the input buffer 129 and latched in the write data latch 32. Then, the process proceeds to S4.

In S4, the data comparator 33 generates mask data. That is, the write data latch 32
The write data latched by the write data and the read data latched by the read data latch 35 are transferred to the data comparator 33.
Transferred to The data comparator 33 compares the corresponding bits of the write data and the read data, and when the two match, the value of the corresponding bit of the mask data is "1", and when the two do not match, the corresponding bit of the mask data is compared. Is set to "0". Then, the generated 1-byte mask data is latched by the mask data latch 36. Then, the process proceeds to S5.

At S5, the control core circuit 132 sets 1
It is determined whether or not the value of each bit of the byte mask data is "1". Then, if all are "1", the process proceeds to S6, and if even one bit is "0", the process proceeds to S7.

In S7, the internal write data generation circuit 34 determines the potentials of the bit lines BLm to BLt corresponding to the write data and the mask data from the write data and the mask data, as shown in FIG. Then, the process proceeds to S8.

At S8, the column decoder 124
According to the decision of the internal write data generation circuit 34, the potentials of the corresponding bit lines BLm to BLt are controlled. And
The row decoder 123 supplies + 15V to the word line WLm. As a result, the word line WLm and each bit line B
As described above, the write operation and the erase operation are simultaneously performed on each memory cell 1 connected to Lm to BLt. In addition, for the memory cell 1 which does not need to perform the writing operation and the erasing operation, the previous state is retained as it is. Then, control goes to a step S9.

In S9, a read operation for verification is performed. That is, after a write operation and an erase operation have been performed for a fixed time, 1 byte of read data is read from each memory cell 1 connected to the word line WLm and each bit line BLm to BLt, as in S2. The read data is read data latch 35.
Is latched in. As a result, the read data latched by the read data latch 35 replaces the read data newly read from each memory cell 1. Then, the process returns to S4.

Therefore, by repeating the operations of S4 to S9, even if the characteristics of the memory cells 1 vary,
The values of all the bits of the mask data can be all "1" (that is, the write data and the read data can be matched in all the bits). Then, in S6, the write operation and the read operation are completed.

As described above, according to this embodiment, the following operation and effect can be obtained in addition to the operation and effect of the first embodiment. [1] In a plurality of memory cells 1 connected to the same word line WLa to WLz, a write operation is performed on a certain memory cell 1 and an erase operation is performed on another certain memory cell 1. A write operation and an erase operation can be performed simultaneously.

[2] By comparing the data (previous data) already stored in the memory cell 1 with the newly written data (write data), the memory cell 1 requiring the erase operation or the write operation is selected. However, only the memory cells 1 can be erased or written.

In the conventional form, an arbitrary memory cell 1
When the write operation is performed on 01, the memory cell 101 is already in the erased state (data value is “1”),
Even if the value of the newly written data is "1",
It is necessary to perform the write operation after performing the erase operation. In addition, even when the memory cell 101 is already in the written state (data value is “0”) and the newly written data value is “0”, it is necessary to perform the write operation after performing the erase operation once. There is. That is, the memory cell 10
In the case of storing the same data value as that of 1 before, it was necessary to perform a completely useless erase operation and write operation.

According to this embodiment, such wasteful erase operation and write operation are unnecessary. [3] Due to the above [1] and [2], the effects (1) to (3) of the first embodiment can be further enhanced. In addition, the writing operation can be speeded up.

(Third Embodiment) Next, a third embodiment will be described with reference to the drawings. In the present embodiment, the same components as those in the first and second embodiments are designated by the same reference numerals, and detailed description thereof will be omitted.

FIG. 7 shows the flash EEPR of this embodiment.
The whole structure of OM41 is shown. In the present embodiment, the second
The difference from the flash EEPROM 31 of the embodiment is that
Adjacent odd and even word lines WLa to WLz
The source S of each memory cell 1 connected to is connected to the same source line SLa-Slm.
That is, the source S of each memory cell 1 connected to each word line WLa, WLb is connected to the source line SLa, and the source S of each memory cell 1 connected to each word line WLm, WLn is the source line SLg. Each memory cell 1 connected to each word line WLy, WLz
Source S of is connected to the source line SLm.

The row decoder 123 not only selects each of the word lines WLa to WLz and controls the potential thereof, but also one source line SLa to Sla corresponding to the row address.
Slm is selected, and the potential of the selected source line is controlled corresponding to each operation mode as described later.

Next, the bit erase mode of the flash EEPROM 41 will be described with reference to FIG. The other operation modes (word line erase mode, write mode, read mode, standby mode) of the flash EEPROM 41 are the same as those of the flash EEPROM 21 of the first embodiment.

In the bit erase mode of this embodiment,
The difference from the first embodiment shown in FIG. 1E is that the source line SLg connected to the source S of the selected memory cell 1c is connected to the bit line BLm connected to the drain D of the memory cell 1a. Only at the point where the same potential (= + 5V) is supplied.

In the memory cells 1b and 1d, the channel CH is off because the potential of the word line WLn is at the ground level. Therefore, even if the potential of the source line SLg rises, the erase operation and the write operation are not performed, and the cell current does not flow.

As for the memory cell 1a, the stored data is not erased as in the first embodiment. However, unlike the first embodiment, the memory cell 1a
Since +5 V is applied to both the source S and the drain D of the cell and the potential difference between the source S and the drain D is zero, no cell current flows.

Regarding the memory cell 1c, originally,
In the written state, electrons are injected into the floating gate FG, so the floating gate FG is negatively charged. Therefore, before supplying + 15V to the word line WLm, the channel CH immediately below the floating gate FG of the memory cell 1c is off,
Despite the potential difference of +5 V between the source S and the drain D, no cell current flows. And + to the word line WLm
When 15 V is supplied, the erase operation starts, the potential of the floating gate FG rises, and the cell current starts to flow. The cell current increases as the erase operation progresses, and the value of the cell current reaches the maximum when the erase operation ends. become.

As described above, in the present embodiment, the cell current does not flow in the memory cell 1a connected to the same word line WLm as the memory cell 1c performing the erase operation, while the memory cell 1c performing the erase operation does not flow. Cell current flows. However, the memory cell 1 that performs the erase operation at the same time
If the number of cells is not increased (that is, when simultaneously erasing from 1 bit to 1 byte), the total amount of cell current does not increase so much, which is not a problem. By the way, the cell current flowing through the memory cell 1c performing the erase operation is about the same as in the read mode.

Further, the progress of the erase operation can be detected by monitoring the cell current of the memory cell 1c performing the erase operation. Therefore, it becomes possible to optimize the amount of charges accumulated in the floating gate FG.

Next, the bit erase mode and the write mode of this embodiment will be described with reference to FIGS. FIG. 9 is a flowchart of the bit erase mode and the write mode. Note that, in FIG. 9, the same steps as those in the flowchart of the second embodiment shown in FIG. 5 have the same step numbers, and description thereof will be omitted.

First, the processes of S1 to S4 are performed, and when the process is completed, the process proceeds to S12. Thereafter, the bit erase mode is performed in S12 to S16. In S12, the internal write data generation circuit 34 determines the potentials of the bit lines BLm to BLt corresponding to the write data and the mask data from the write data and the mask data, as shown in FIG. Then, control goes to a step S13.

At S13, the control core circuit 132
Each bit line BLm to BLt is connected to each sense amplifier to activate each sense amplifier. Then, the process proceeds to S14.

In S14, the column decoder 124
Controls the potentials of the corresponding bit lines BLm to BLt according to the determination of the internal write data generation circuit 34. Then, the row decoder 123 applies + 15V to the word line WLm.
To supply + 5V to the source line SLg. As a result, the erase operation is started for the eight memory cells 1 connected to the word line WLm and each of the bit lines BLm to BLt as described above. Then, the process proceeds to S15.

In S15, the bit lines BLm to BLm
The sense amplifiers connected to t monitor the cell currents of the eight memory cells 1 connected to the word line WLm and the bit lines BLm to BLt, respectively, so that the erase operation proceeds as described above. Detect the condition. Then, the process proceeds to S16.

At S16, the control core circuit 132
When the cell current of each memory cell 1 monitored by each sense amplifier reaches a predetermined value, the column decoder 124 is controlled to end the erase operation. Then, the process proceeds to S5.

Hereinafter, S5, S17, S18, S9, S
4, the write mode is performed in S19. In S5, the control core circuit 132 determines whether or not all the values of each bit of the 1-byte mask data are "1". Then, if all are "1", the process proceeds to S19, and if even one bit is "0", S17.
Move to.

In S17, as shown in FIG. 11, the internal write data generation circuit 34 determines the potentials of the bit lines BLm to BLt corresponding to the write data and the mask data from the write data and the mask data. Then, the process proceeds to S18.

In S18, the column decoder 124
Controls the potentials of the corresponding bit lines BLm to BLt according to the determination of the internal write data generation circuit 34. Then, the row decoder 123 supplies +1 V to the word line WLm and sets the potential of the source line SLg to the ground level. As a result, the word line WLm and each bit line BLm
The write operation is performed on the eight memory cells 1 connected to BLt as described above. And
Move to S9.

In S9, a read operation for verification is performed. Then, the process proceeds to S4. After the process of S4, the process returns to S5. Therefore, S5, S17, S1
By repeating the operation of S8, S9, and S4, all the values of all bits of the mask data can be set to "1" even if the characteristics of each memory cell 1 vary (that is, write data and read data). And all bits can be matched). Then, in S19, the write mode is ended.

As described above, according to this embodiment, the following operation and effect can be obtained in addition to the operation and effect of the first embodiment. <1> In the first embodiment, as described in (4) above, the memory cell 1 that performs the erase operation in the bit erase mode.
Memory cell 1 connected to the same word line WLm as c
A cell current flows in a. Similarly, also in the second embodiment, in the write and bit erase modes, the memory cell 1c performing the erase operation and the memory cell 1 performing the write operation.
Memory cell 1 connected to the same word line WLm as e
A cell current flows in a.

According to this embodiment, since no cell current flows through the memory cell 1a, the flash EEPR is correspondingly increased.
The power consumption of the OM 41 can be reduced. <2> A cell current flows through the memory cell 1c that performs the erase operation. However, the memory cell 1 that performs the erase operation at the same time
1 to 8 (that is, 1 bit to 1
In the case of simultaneous erasing of about bytes), the total amount of cell current does not increase so much. Therefore, the power consumption reduction effect of <1> above is more significant, and the flash EE
It is possible to reduce the power consumption of the PROM 41 as a whole. By the way, the cell current flowing through the memory cell 1c performing the erase operation is about the same as in the read mode.

<3> The sense amplifier monitors the cell current of the memory cell 1 that performs the erase operation. As a result, the progress of the erase operation can be detected, and the amount of charges accumulated in the floating gate FG can be optimized. Further, since the end point of the erase operation can be accurately detected, it is not necessary to perform an extra erase operation, and the erase operation can be speeded up.

In the bit erase mode, the potentials supplied to the unselected bit lines BLa to BLm and BLo to BLz and the source lines SLa to SLm connected to the source S of the selected memory cell 1 (the above-described embodiment). Then +5
Regarding V), it is necessary to satisfy the following condition (4) in addition to the conditions (1) to (3) of the first embodiment.

(4) In order to reduce the source current of the memory cell 1c, the potential should be low within the range satisfying the condition (1). (Fourth Embodiment) Next, a fourth embodiment will be described with reference to the drawings. In the present embodiment, the same components as those in the third embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

FIG. 12 shows the main structure of this embodiment.
The present embodiment differs from the third embodiment only in that the source lines SLa to SLm are grounded via the NMOS transistors 42. In the bit erase mode, the gate of each NMOS transistor 42
The low level signal is applied only when the word lines WLa to WLz connected to the source lines SLa to SLm via the memory cell 1 rise. That is, only in the bit erase mode, the NMOS transistor 42 is turned off and the source lines SLa to SLm are put in the floating state. In addition, each NMOS transistor 4
The signal applied to the second gate is generated by the row decoder 123. By doing so, the cell current does not constantly flow through the memory cells 1a and 1c in the bit erase mode.

Therefore, according to the present embodiment, it is possible to reduce the power consumption as in the third embodiment. (Fifth Embodiment) Next, a fifth embodiment will be described with reference to the drawings. In the present embodiment, the same components as those in the fourth embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

FIG. 13 shows the flash EEPR of this embodiment.
The overall structure of the OM 51 is shown, and FIG. 14 shows the main structure of the OM 51. The present embodiment is different from the fourth embodiment in that
Source lines SLa to SL for each bit line BLa to BLz
z, and the sources S of the memory cells 1 connected to the same bit lines BLa to Blz are the same source line SL.
It is only the point connected to a-Slz. The source lines SLa to SLz are connected to the NMOS transistors 52, respectively.
Grounded. Each NMOS transistor 52
A low level signal is applied to the gate of the gate only in the bit erase mode. The signal applied to the gate of each NMOS transistor 52 is generated by the control core circuit 132. That is, only in the bit erase mode, the NM
The OS transistor 52 is turned off, and the source line SLa-
SLz is brought into a floating state.

In the fourth embodiment shown in FIG. 12, when the erase operation of the memory cell 1c progresses and the channel CH turns on,
As shown by arrow A, bit line BLm (= + 5V) connected to memory cell 1a → source line SLg → memory cell 1c → bit line B connected to memory cell 1c
The current flows through the path Ln (= 0V). However, when the number of the memory cells 1 performing the erase operation at the same time is about 1 to 8, the total amount of this current is not so large. Therefore, in the fourth embodiment, low power consumption can be achieved unless the number of memory cells 1 performing the erase operation at the same time is increased.

On the other hand, in the present embodiment, the source lines SLa to SLz are provided for the bit lines BLa to BLz, respectively.
Is provided, no current flows as in the fourth embodiment. Therefore, according to the present embodiment, it is possible to reduce the power consumption even when the number of memory cells 1 that simultaneously perform the erase operation is increased.

(Sixth Embodiment) Next, a sixth embodiment will be described with reference to the drawings. In the present embodiment, the first to
The same components as those in the fifth embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

The present embodiment makes it possible to store multivalued data in the memory cell 1. FIG.
23 shows the characteristics of the charge amount Q of the floating gate FG and the read current (cell current) I in the read mode (c) shown in FIG. The charge amount Q of the floating gate FG and the read current I show a proportional relationship, and the characteristics thereof are similar to the characteristics of the gate voltage VGS and the drain current ID in the enhancement type NMOS transistor.

As described above, in the memory cell 1, the read current I is uniquely determined by the charge amount Q of the floating gate FG. In the erase operation or the write operation, the charge amount Q of the floating gate FG can be controlled by adjusting the operation time. Therefore, the read current I can be arbitrarily set by controlling the charge amount Q of the floating gate FG.

Therefore, as shown in FIG. 15, when the read current I is an arbitrary value Ia or less (I <Ia), the data value is "00", and when the read current I is the value Ia or more and an arbitrary value Ib or less. (Ia <I <Ib) is the data value “01”, and the read current I is the value Ib or more and the arbitrary value Ic or less (Ib
<I <Ic) is the data value “10” and the read current I is the value I
If c or more (Ic <I) is associated with the data value “11”, four-value (= 2 bits) data can be stored in one memory cell 1.

FIG. 16 shows a circuit example of the sense amplifier 61 for reading the four-valued data stored in the memory cell 1. The sense amplifier 61 includes a reference voltage generator 62, comparators 63 to 65, an NMOS transistor 66, an inverter 67, a NOR 68, a NAND 69, and resistors R1 and R.
2 is comprised.

The sense amplifier 61 operates in the following order. (1) Initially, both the signal SA and the word line WL are at low level. (2) When the signal SA rises, the transistor 66 is turned on, and the potential of the bit line BL becomes 2 due to the resistors R1 and R2.
V is set.

(3) The word line WL rises, the read current I of the memory cell 1 flows, and the potential of the bit line BL becomes 2
It is lower than V. (4) Bit line B when the read current I is an arbitrary value Ia
The potential of L is the reference voltage Vref1, and the read current I is an arbitrary value I
The potential of the bit line BL when b is the reference voltage Vref2, and the potential of the bit line BL when the read current I is an arbitrary value Ic is the reference voltage Vref3. These reference voltages Vref1 and Vref
2, Vref3 is generated from the reference voltage generator 62, and the reference voltages Vref1, Vref2, Vref3 are applied to the negative input terminals of the comparators 63 to 65, respectively. The positive input terminal of each of the comparators 63 to 65 is connected to the bit line BL.

(5) Each of the comparators 63 to 65 compares the potential of the bit line BL with each of the reference voltages Vref1, Vref2 and Vref3, and the comparison result is the inverter 67, NOR68,
It is sent to NAND69.

(6) As shown in FIG. 17, the values of the read data DATA1, DATA2 of the sense amplifier 61 are determined from the potentials of the outputs a1, a2, a3 of the comparators 63-65. Each of the read data DATA1 and DATA2 becomes the above-mentioned four-valued data.

As described above, by using the sense amplifier 61, the four-valued data stored in the memory cell 1 can be read based on the read current (cell current) I of the memory cell 1.

FIG. 18 shows the flash EEPR of this embodiment.
The whole structure of OM71 is shown. In the present embodiment, the third
The difference from the flash EEPROM 41 of the embodiment is that
The data comparator 33 is a data comparator 74, the mask data latch 36 is an internal write data latch 72, the internal write data generation circuit 34 is a bit line potential setting circuit 73,
The only difference is that each is replaced.

As will be described later, the data comparator 74 compares the size of the write data with the read data for each memory cell 1 (that is, for every 2 bits) to determine the four memory cells 1
To generate internal write data of 1 byte in total. The internal write data latch 72 latches internal write data, and the internal write data is stored in the bit line potential setting circuit 73.
Transferred to

As will be described later, the bit line potential setting circuit 73 determines each bit line BLa based on the internal write data.
Determine the potential of ~ BLz. The column decoder 124 is
According to the decision of the bit line potential setting circuit 73, the potentials of the bit lines BLa to BLz are controlled.

The sense amplifier group 130 is composed of four sense amplifiers 61. The operation of each circuit (32, 35, 72 to 74, 123 to 131) described above is controlled by the control core circuit 132.

Next, the write and bit erase modes of this embodiment will be described with reference to FIGS.
The other operation modes (word line erase mode, read mode, standby mode) of this embodiment are the same as those of the flash EEPROM 41 of the third embodiment.

FIG. 19 is a flow chart of the write mode and the bit erase mode. Incidentally, in FIG. 19, the same steps as those in the flowchart of the second embodiment shown in FIG. 5 have the same step numbers, and the description thereof will be omitted.

First, the process of S1 is performed, and the process proceeds to S22. In S22, the pre-read operation is performed. That is,
Of the addresses latched by the address latch 127, the row address is transferred to the row decoder 123, and the column address is transferred to the column decoder 124. The row decoder 123 selects one word line WLa to WLz (for example, WLm) corresponding to the row address. The column decoder 124 has four bit lines BLa to BLz (for example, BLm) corresponding to the column address.
~ BLp) is selected. Then, read data is read from the four memory cells 1 connected to the word line WLm and each bit line BLm to BLp, and the read data is sensed from each bit line BLm to BLp via the column decoder 124. It is transferred to the amplifier group 130. As a result, 2 bits are read from each memory cell 1 and a total of 1 byte of read data is read. The read data is latched by the read data latch 35. Then, the process proceeds to S3.

After the processing of S3, the process proceeds to S23. S2
3, the control core circuit 132 selects the memory cell 1 that performs the erase operation and the memory cell 1 that performs the write operation. Then, first, the following processes of S24 to S29 are performed on the memory cell 1 that performs the erase operation.

In S24, the data comparator 74 generates internal write data. That is, the write data latched by the write data latch 32 and the read data latched by the read data latch 35 are transferred to the data comparator 74. As shown in FIG. 20, the data comparator 74 compares the size of the write data and the read data for each memory cell 1 (that is, for every 2 bits), and the internal write of a total of 4 bits from the four memory cells 1 is performed. Generate data. Then, the generated 4-bit internal write data is latched by the internal write data latch 72. Then, the process proceeds to S25.

At S25, the control core circuit 132
It is determined whether or not the value of each bit of the 4-bit internal write data is "0". Then, when all are "0", the process proceeds to S26, and when even one bit is "1", the process proceeds to S27.

In S27, the bit line potential setting circuit 7
As shown in FIG. 20, reference numeral 3 indicates the bit lines BLm to BLp corresponding to the internal write data from the internal write data.
Determine the potential of. Then, the process proceeds to S28.

At S28, the column decoder 124
Controls the potentials of the corresponding bit lines BLm to BLp according to the determination of the bit line potential setting circuit 73. And
The row decoder 123 supplies + 15V to the word line WLm and + 5V to the source line SLg. as a result,
For each memory cell 1 connected to the word line WLm and each bit line BLm to BLp, as described above,
Erase operation is performed. Then, the process proceeds to S29.

In S29, a read operation for verification is performed. That is, after the erasing operation is performed for a certain time, 1 byte of read data is read from each memory cell 1 connected to the word line WLm and each bit line BLm to BLp, and the read data is read, as in S22. Are latched in the read data latch 35. As a result, the read data latched by the read data latch 35 replaces the read data newly read from each memory cell 1. And S2
Return to 4.

Therefore, by repeating the operations of S24 to S29, all the values of all bits of the internal write data can be set to "0" even if the characteristics of the memory cells 1 vary.

Then, in S26, the control core circuit 1
32 determines whether or not the erase operation is completed, and if so, returns to S23. In S23, the control core circuit 132 writes to the memory cell 1 that performs the write operation,
The processing of S24 to S29 is performed. In S28, unlike the case of the erase operation, the row decoder 123 sets the word line WL
+ 1V is supplied to m to bring the potential of the source line SLg to the ground level. Then, in S26, the control core circuit 132 determines whether or not the write operation is completed,
If completed, all processing is completed.

As described above, according to this embodiment, in addition to the operation and effect of the third embodiment, two memory cells 1 are provided.
Data can be stored bit by bit. The above-described embodiments may be modified as follows, and in that case, the same operation and effect can be obtained.

(1) In the second to sixth embodiments, the erase operation or the write operation is performed on 1-byte data.
However, the number of bits of data to be erased or written is not limited to 1 byte, and any number of bits may be used. However, in the second to fourth embodiments, power consumption increases as the number of memory cells 1 that perform the erase operation at the same time increases, so about 1 bit to 1 byte is preferable.

(2) In the sixth embodiment, one memory cell 1 stores data of 3 bits or more. (3) Any one of the second, fourth, and fifth embodiments and the sixth
Combine with the embodiment. In this case, in addition to the operation and effect of each embodiment, multi-valued data can be stored in each memory cell 1.

(4) Split gate type flash E
It is applied to a stacked gate type flash EEPROM instead of an EPROM. However, regarding the electrostatic capacitance between the drain and the floating gate, the split gate type memory cell is larger than the stacked gate type memory cell. Therefore, each of the above-described embodiments can obtain a particularly great effect when applied to a split gate type flash EEPROM.

By the way, (Yasuo Sato et al .: Flash erasable using a one-transistor type memory cell.
EEPROM technology, IEICE Technical Report SDM93-23, ICD93-25 (1993-0
5), pp9-14), a bit erasing technique in a stacked gate type flash EEPROM has already been proposed. In the method of the same paper, a write operation is performed using the FN tunnel current flowing from the drain to the floating gate, and a word line erase operation is performed using the FN tunnel current flowing from the floating gate to the entire channel (in the same paper, sector erase (Notated)
Then, the bit erase operation is performed by utilizing the injection of hot electrons from the channel to the floating gate.

However, the method of this paper has the following drawbacks. (1) Since the erasing method differs between the word line erasing operation and the bit erasing operation, the entire circuit of the flash EEPROM becomes complicated.

(2) In the stacked gate type memory cell, the injection efficiency of hot electrons from the channel to the floating gate is low. Therefore, in the bit erase operation, the number of memory cells that can simultaneously perform the erase operation cannot be increased.

(3) When the write operation is performed by using the FN tunnel current flowing from the drain to the floating gate, DINOR is used to prevent disturb.
Type or AND type memory cell configuration must be adopted, and a simple NOR type memory cell configuration cannot be adopted.

Since each of the above-mentioned embodiments does not have the above-mentioned drawbacks, it is far more practical than the method of the same paper. Although the embodiments have been described above, technical ideas other than the claims that can be grasped from the embodiments will be described below along with their effects.

(A) In the nonvolatile semiconductor memory device according to the thirteenth aspect, each word line (WLa to WLa to which the control gate of each memory cell arranged in the row direction is connected).
WLz) and each bit line (BLa to BLz) to which the drains of the memory cells arranged in the column direction are connected, the drain potential is controlled by controlling the potential of the bit line, and A nonvolatile semiconductor memory device in which the potential of a control gate is controlled by controlling the potential.

In this way, when the drain voltage of the memory cell is increased during the erase operation, the floating gate is lifted by the coupling, the potential difference from the control gate is reduced, and the Fowler-Nordheim tunnel current stops flowing. Therefore, by changing the potentials of the bit line of the memory cell to be erased and the bit lines other than that, the erase operation can be performed only on an arbitrary memory cell.

(B) In the nonvolatile semiconductor memory device according to the tenth aspect, each word line (WLa to WLa to which the control gate of each memory cell arranged in the row direction is connected).
WLz), the bit lines (BLa to BLz) connected to the drains of the memory cells arranged in the column direction, and the source lines (SLa to BLa to the source lines connected to the sources of the memory cells arranged in the column direction). SLz) and a non-volatile semiconductor memory device.

In this way, by controlling the potential of each source line, the potential of the source can be controlled separately for each memory cell arranged in the column direction.

[0155]

【The invention's effect】

1] It is possible to provide a nonvolatile semiconductor memory device having excellent durability. 2) It is possible to provide a nonvolatile semiconductor memory device with low power consumption.

3] It is possible to provide a nonvolatile semiconductor memory device having a high operation speed. 4] It is possible to provide a nonvolatile semiconductor memory device having a small circuit scale.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a main part for explaining an operation of a first embodiment.

FIG. 2 is a circuit diagram of a main part for explaining the operation of the second embodiment.

FIG. 3 is an explanatory diagram for explaining the operation of the second embodiment.

FIG. 4 is a block circuit diagram of a second embodiment.

FIG. 5 is a flowchart for explaining the operation of the second embodiment.

FIG. 6 is an explanatory diagram for explaining the operation of the second embodiment.

FIG. 7 is a block circuit diagram of a third embodiment.

FIG. 8 is a circuit diagram of a main part for explaining the operation of the third embodiment.

FIG. 9 is a flowchart for explaining the operation of the third embodiment.

FIG. 10 is an explanatory diagram for explaining the operation of the third embodiment.

FIG. 11 is an explanatory diagram for explaining the operation of the third embodiment.

FIG. 12 is a circuit diagram of a main part for explaining the operation of the fourth embodiment.

FIG. 13 is a block circuit diagram of a fifth embodiment.

FIG. 14 is a main-portion circuit diagram for explaining the operation of the fifth embodiment.

FIG. 15 is a characteristic diagram for explaining the operation of the sixth embodiment.

FIG. 16 is a circuit diagram of a main part of the sixth embodiment.

FIG. 17 is an explanatory diagram for explaining the operation of the sixth embodiment.

FIG. 18 is a block circuit diagram of a sixth embodiment.

FIG. 19 is a flowchart for explaining the operation of the sixth embodiment.

FIG. 20 is an explanatory diagram for explaining the operation of the sixth embodiment.

FIG. 21 is a cross-sectional view of a memory cell used in the conventional form and each embodiment.

FIG. 22 is a block circuit diagram of a conventional form and the first embodiment.

FIG. 23 is a circuit diagram of a main part for explaining the operation of the conventional form and the first embodiment.

[Explanation of symbols]

 1 ... Memory cell FG ... Floating gate CG ... Control gate S ... Source D ... Drain CH ... Channel WLa-WLz ... Word line BLa-BLz ... Bit line SLa-SLz ... Source line 123 ... Row decoder 124 ... Column decoder 132 ... Control Core circuit 132

Claims (17)

[Claims] 1. A non-volatile semiconductor memory device that performs an erase operation only on an arbitrary memory cell by controlling the potential of a floating gate for each memory cell. 2. A floating gate (FG), a control gate (CG), a source (S) and a drain (D).
A control circuit (123, 124, 123) for performing an erase operation only on an arbitrary memory cell by controlling the potential of each memory cell (1) including 132) and a non-volatile semiconductor memory device. 3. A floating gate (FG), a control gate (CG), a source (S) and a drain (D).
By controlling the potential of each memory cell (1) consisting of a memory cell and a channel (CH) and its floating gate for each memory cell, a write operation is performed to a certain memory cell and at the same time, another memory cell A non-volatile semiconductor memory including a control circuit (123, 124, 132) for performing an erasing operation on a cell, and for a memory cell which does not need to perform a writing operation and an erasing operation, holds the previous state as it is. apparatus. 4. The nonvolatile semiconductor memory device according to claim 2, wherein the control gate of each memory cell controlling the potential of the floating gate is connected to a common word line (WLm). Semiconductor memory device. 5. A floating gate (FG), a control gate (CG), a source (S) and a drain (D).
A control circuit (123, 124, 123) for performing an erase operation only on an arbitrary memory cell by controlling the potential of each memory cell (1) including 132), the control gate of each memory cell for controlling the potential of the floating gate is connected to a common word line (WLm), and the memory cell (1a connected to the common word line that does not perform the erase operation). ), The potential of the bit line (BLm) to which the drain is connected is controlled to a high value such that Fowler-Nordheim tunnel current does not flow between the floating gate and the control gate. . 6. A floating gate (FG), a control gate (CG), a source (S) and a drain (D).
By controlling the potential of each memory cell (1) consisting of a memory cell and a channel (CH) and its floating gate for each memory cell, a write operation is performed to a certain memory cell and at the same time, another memory cell A memory cell that performs an erase operation on a cell and does not need to perform a write operation or an erase operation is provided with a control circuit (123, 124, 132) for keeping the previous state as it is, The control gate of each memory cell for controlling the potential is connected to a common word line (WLm), and for the memory cell (1a) connected to the common word line that does not need to perform a write operation or an erase operation, Bit line with drain connected (BLm)
A non-volatile semiconductor memory device for controlling the electric potential of the device to such a high value that a Fowler-Nordheim tunnel current does not flow between its floating gate and control gate. 7. A floating gate (FG), a control gate (CG), a source (S) and a drain (D).
By controlling the potential of each memory cell (1) consisting of a memory cell and a channel (CH) and its floating gate for each memory cell, a write operation is performed to a certain memory cell and at the same time, another memory cell A memory cell that performs an erase operation on a cell and does not need to perform a write operation or an erase operation is provided with a control circuit (123, 124, 132) for keeping the previous state as it is, The control gate of each memory cell that controls the potential is connected to a common word line (WLm), and the memory cell (1e) that is connected to the common word line and performs a write operation has its drain connected to the bit. A high electric field is generated between the floating gate and the control gate of the potential of the line (BLm), The nonvolatile semiconductor memory device for controlling Le to the floating gate to the high value enough hot electrons are injected. 8. A floating gate (FG), a control gate (CG), a source (S) and a drain (D).
By controlling the potential of each memory cell (1) consisting of a memory cell and a channel (CH) and its floating gate for each memory cell, a write operation is performed to a certain memory cell and at the same time, another memory cell A memory cell that performs an erase operation on a cell and does not need to perform a write operation or an erase operation is provided with a control circuit (123, 124, 132) for keeping the previous state as it is, The control gate of each memory cell for controlling the potential is connected to a common word line (WLm), and for the memory cell (1a) connected to the common word line that does not need to perform a write operation or an erase operation, Bit line with drain connected (BLm)
Memory cell (1e) connected to the common word line and performing a write operation by controlling the potential of the memory cell to a high value such that Fowler-Nordheim tunnel current does not flow between the floating gate and the control gate. Controls the potential of the bit line (BLm) to which the drain is connected to such a high value that a high electric field is generated between the floating gate and the control gate and hot electrons are injected from the channel to the floating gate. Nonvolatile semiconductor memory device. 9. The nonvolatile semiconductor memory device according to claim 2, wherein the potential of the source is controlled to prevent generation of a cell current flowing from the drain to the source. apparatus. 10. The non-volatile semiconductor memory device according to claim 2, wherein the source is set in a floating state to prevent generation of a cell current flowing from the drain to the source. apparatus. 11. The nonvolatile semiconductor memory device according to claim 2, wherein the potentials of the sources of the memory cells arranged in the column direction are simultaneously controlled,
A nonvolatile semiconductor memory device that prevents generation of a cell current flowing from a drain to a source. 12. The non-volatile semiconductor memory device according to claim 2, wherein the potential of the source is separately controlled for each memory cell arranged in the column direction, so that the drain to the source are controlled. A non-volatile semiconductor memory device that prevents the generation of a cell current flowing to the memory cell. 13. The nonvolatile semiconductor memory device according to claim 1, wherein a cell current flowing from a drain to a source is monitored to control the amount of charges accumulated in the floating gate. And a nonvolatile semiconductor memory device that detects the end of the erase operation. 14. The non-volatile semiconductor memory device according to claim 1, wherein the amount of charges accumulated in the floating gate is controlled for each memory cell, so that a multi-valued memory cell is provided. A nonvolatile semiconductor memory device for storing data. 15. The nonvolatile semiconductor memory device according to claim 1, wherein the potential of the floating gate is controlled by controlling the potentials of the drain, the source and the control gate, respectively. Storage device. 16. The non-volatile semiconductor memory device according to claim 15, wherein the potential of the floating gate is controlled by controlling the potential of the bit line connected to the drain, the potential of the source line connected to the source, and the control gate. A non-volatile semiconductor memory device which is formed by controlling potentials of word lines connected to each other. 17. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell is a split gate type or a stacked gate type.