JPH09205434A - Atm cell assembling/disassembling method and device therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a cell assembler where data even in one byte are not aborted in the case of transfer of structural data by providing a means assembling AAL1 cells in the received order and varying the length of a payload of the AAL1 cell for each channel number. SOLUTION: A buffer memory 100 storing CBR data S101 at a multi-speed subject to time division multiplex received from an STM network has plural banks 101 divided into an optional size. A buffer write means 102 writes the CBR data 101 at a multi-speed subject to time division multiplex to the banks 101 for each channel. The means 102 has a function of outputting a channel number 108 when cells are stored up to a buffer storage amount at which assembling of the AAL1 cells is attained. An AAL1 cell assembling means 103 assembles the AAL1 cells for each channel in the received order based on the channel number 108 received from the buffer write means 102 and sends the assembled cell S117 to an ATM network.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a network in an asynchronous transfer mode (hereinafter referred to as ATM) and a synchronous transfer mode (Synchronous Transfer Mode).
er Mode: ATM cell assembly / disassembly method and device (Cell Assembly / Disassembly) for interconnecting networks of STM)
assembly: hereinafter referred to as CLAD), in particular, a configuration of a CLAD that converts an STM signal in which constant bit rate (Constant Bit Rate: hereinafter referred to as CBR) data of a multiple speed is time-division multiplexed into an ATM cell, and a voice. The present invention relates to an ATM cell assembling / disassembling method / apparatus for converting a signal, such as a signal, whose quality influences a transfer delay time into an ATM cell.

[0002]

2. Description of the Related Art As a network for uniformly transmitting and receiving low-speed signals such as voice signals to high-speed signals such as image signals, a broadband service integrated digital network (Broadband Inte
grated Services Digital Network: hereinafter referred to as B-ISDN). ATM has been studied in various countries around the world as a technology for realizing this B-ISDN, and the Telecommunication Standardization Sector (International Telecommunication Union-Teleco
mmunication Standardization Secter: hereinafter referred to as ITU-T), various international standard recommendations for realizing B-ISDN are defined.

A current communication network has a configuration in which this ATM network and an existing STM network are mixed, and in order to connect the ATM network and the STM network to each other, CLAD (Cell Asse) is used.
mbly / Disassembly: Cell assembly / disassembly is essential.

The ITU-T stipulates the functions and specifications of an ATM Adaptation Layer (AAL), which is a protocol for converting various signals into ATM cells, and particularly voice signals. CB of etc.
When converting R data into ATM cells, I.3 of ITU-T
It is specified to use AAL type 1 (hereinafter referred to as AAL1) specified in 63. That is, the STM line signal, which is CBR data, is stipulated in the international standard to communicate using the AAL1 when communicating via the ATM network.

FIG. 21 shows the conversion of CBR data and ATM cells using AAL1. CBR data and ATM cells (hereinafter, ATM cells using AAL1 are referred to as AAL1 cells).
It is a figure explaining the conversion of. As shown in the figure, the CBR data 2101 continuously arrives at a fixed bit rate, accumulates CBR data that enables ATM cell assembly, and is converted into a 53-byte AAL1 cell 2102.

The format of this AAL1 cell is shown in FIG.

AAL1 cell is a 5-byte ATM header 2201
And 1-byte AAL1 header 2202 defined by ITU-T I.363, and 1-byte pointer 2204 indicating the start position in the case of structured data that stores the structure of CBR data in one frame, 47 Alternatively, it is composed of a payload 2203 that stores 46 bytes of CBR data. More specifically, the AAL1 header is composed of a sequence number field (SNF) 2209 indicating the assembled order of AAL1 cells and a sequence number protection field (SNPF) 2210 for protecting the SNF2209, and the SNF2209 has a 1-bit length. Convergence sublayer indication (CSI) 2205 and 3-bit sequence number (SN) 2206 indicating the order of cell assembly by repetition numbers 0 to 7, and the SNPF2210 is
3-bit error correction code (CRC) 2207 that protects SNF2209
And 1-bit even parity (P) 2208 for protecting the SNF 2209 and CRC 2207.

The pointer 2204 stores data having a structure between the transmitting side and the receiving side, for example, 6 and 24 bytes of data are stored in one frame (125 microseconds) such as 384 kb / s or 1536 kb / s channel. When transferring structured data that has
It is shown as 11, and is inserted only once when SN2206 is between 0 and 7 and only when SN2206 is an even number.

If, for example, the head of the structured data does not appear between SN2206 and 0-7, a dummy pointer is inserted in the pointer. That is, for structured data,
The CBR data (payload) length in one cell is 47 bytes in the case of a non-pointer format (hereinafter referred to as non-P format) in which no pointer is inserted, and the pointer format in which a pointer is inserted (hereinafter referred to as P format) Either of 46 bytes in case of. If the data is not structured data (hereinafter referred to as unstructured data), the pointer is not inserted, so 1
The CBR data (payload) length in a cell is fixed at 47 bytes.

"The Institute of Electronics, Information and Communication Engineers, SSI 94-188
According to the above, the function of the AAL1 needs to be processed for each channel, and the processing function of the AAL1 needs to be provided for each channel.

However, allocating the processing function of the AAL1 to each channel requires a huge amount of hardware and is uneconomical. When interconnecting an STM network and an ATM network with a relay multiplex line, which is considered as a CLAD application position, multiple processing of AAL1 for each channel makes it possible to reduce the size and cost of the device. Known examples for realizing this AAL1 multiplex processing include "cell disassembling multiplex processing apparatus" disclosed in Japanese Patent Laid-Open No. 6-232893 and "cell assembly multiplex processing apparatus" disclosed in Japanese Patent Laid-Open No. 6-232894. "
There is.

[0012] This relates to an AAL1 cell assembling and disassembling apparatus, and multi-processes and converts time-division-multiplexed CBR data of multiple speed into AAL1 cells, and conversely converts AAL1 cells into time-division-multiplexed CBR data. Regarding the configuration to convert.

In this configuration, the buffer memory is divided into payload lengths of AAL1 cells (hereinafter, one unit of the divided buffer memory is referred to as a bank), and time division multiplexed CBR is performed.
CBR arrives with multiple banks to store data
Data is stored in the bank for each designated virtual channel, and when the CBR data corresponding to the payload length of the AAL1 cell is stored in the bank, the address of the bank is output, and the new bank is newly stored in the unused bank. A cell assembly control unit that stores CBR data and an address output by this cell assembly control unit are input, the CBR data is read from the bank indicated by this address to form a cell and output, and the bank is not used. A cell transmission control unit serving as a bank is provided.

As a result, it becomes possible to manage used banks and unused banks and share the banks with all channels, and it is not necessary to prepare a buffer memory for each channel.

Further, the buffer memory is not fixed for each channel, but the buffer memory is divided into the fixed-length banks and the banks are shared for each channel, so that a plurality of time-division multiplexed speeds can be obtained. Even when converting CBR data of different arbitrary speeds into AAL1 cells, it is not necessary to have a buffer memory having a capacity for storing CBR data of maximum speed for each channel. In other words, with this configuration, it is possible to multiplex-convert time-division multiplexed multi-rate CBR data into AAL1 cells while minimizing the amount of buffer memory used. Can be realized.

On the other hand, the CBR data is mainly a voice signal from a telephone service, and the quality of this voice signal is greatly affected by the propagation delay time. That is, for example, 64kb
When converting voice signals from the / s telephone service into AAL1 cells for communication, the delay time for assembling AAL1 cells is AAL1 cells.
Since it is necessary to store CBR data for the payload length of one cell, 125 (microseconds) x 47 (bytes) = 5.875 (milliseconds).

As a method of reducing the cell assembly delay time, there is a method called partial fill ("ATM Forum
ATMF94-0033R8, Cell Utilization.2.2.2, May 199
Five"). This partial fill, as shown in FIG.
This is a method of shortening the cell assembly delay time by setting the CBR data length (hereinafter referred to as effective data length) stored in the payload in the cell to an arbitrary number of bytes. That is, the effective data length is shortened, and the time for accumulating the above CBR data is shortened.

As another method for reducing the cell assembly delay time, there is a method called composite cell (Unit
ed States Patent Patent Number 5390,175 `` INTER-CEL
L SWITCHING UNIT FOR NARROW BAND ATM NETWORK
S "). In this composite cell, as shown in FIG. 24, the same channel signal with the same transmission destination is stored in the payload of the same cell to shorten the effective data length of each channel and shorten the cell assembly delay time. is there.

That is, both methods are methods of shortening the storage time of the CBR data by reducing the amount of CBR data stored in the payload of the AAL1 cell.

[0020]

First, the first problem will be described.

In the above-described conventional cell assembling / multiplexing processing apparatus, the buffer memory is divided into banks each having a payload length of one AAL cell as one unit, and the plurality of banks are provided to buffer the CBR data of multiple speeds which are time-division multiplexed. I was doing a ring. However, the bank has a fixed-length bank structure, and in the case of the structured data transfer described above, there are two types of payload length, 46 bytes or 47 bytes, depending on whether or not a pointer is inserted. Can not be done.

For example, when the size of the bank is 47 bytes, the cell assembly control unit stores data of the same channel for 47 bytes in the bank and outputs the address of the bank to the cell transmission control unit. The cell transmission control unit starts cell assembly from the input bank address,
If the cell is converted to the structured data PAL format AAL1 cell, the payload length is 46 bytes.
1-byte data remains in the bank. Furthermore, the cell transmission control unit makes the bank an unused bank, even though 1-byte data remains in the bank. In other words, when converting the structured data into the PAL format AAL1 cell, there is a problem that 1 byte of data is always discarded.

Next, the second problem will be described.

As described above, the mainstream of CBR data is a voice signal from a telephone service, and the quality of this voice signal is greatly affected by the propagation delay time. More specifically,
At the location where the existing analog subscriber line is accommodated and the 2-line to 4-line conversion is performed, a reverberation of voice occurs, and if the delay time between terminals is long, the reverberation is perceived as an echo. Further, it is premised that the voice signal of a telephone or the like is communicated in real time, and the condition becomes strict regarding fluctuation of propagation delay time.

Therefore, as described above, in the case of a telephone service of 64 kb / s, it is problematic that the cell assembly delay time is as long as 5.875 (milliseconds), and the above-mentioned method for shortening the cell assembly delay time is a problem. Is being considered.

In the above-mentioned conventional cell assembling multiple processing apparatus, the partial fill can be realized by setting the bank size to an arbitrary number of bytes. However, because this bank is shared by all channels,
Partial fill cannot be applied only to a specific channel. Also, as described above, the partial fill is effective in reducing the cell assembly delay time, but by reducing the effective data length of the AAL1 cell, dummy data (invalid data) is inserted in the rest. , The transmission line cannot be used effectively.

In other words, the partial fill reduces the cell assembly delay time, but cannot effectively use the transmission path. When a channel that says "the delay time is small even if the transmission line cannot be used effectively" and a channel that says "I want to use the transmission line effectively even if the delay time is large" are multiplexed and arrive at the cell assembly and processing unit ,
There is a problem that it cannot handle each channel.

Furthermore, if the partial fill is applied to all the time-division-multiplexed channels, the amount of cells flowing into the transmission path increases, which may cause congestion, which is a problem.

An object of the present invention is to enable assembly of an AAL1 cell without transferring data of 1 byte even with two types of payload length (47/46 bytes) in the case of transferring structured data. It is to provide a cell assembling / disassembling method and apparatus.

Another object of the present invention is to provide ATM for each channel.
It is an object of the present invention to provide an ATM cell assembling / disassembling method and apparatus which enables the effective data length in the payload in one cell to be an arbitrary number of bytes and shortens the delay time in cell assembling.

Still another object of the present invention is to make the effective data length for each channel number an arbitrary number of bytes, thereby flexibly shortening the cell assembly delay time for each channel number. It is to provide a disassembling method and apparatus.

[0032]

In order to solve the first problem, the present invention has the constitution described below.

A plurality of buffer memories (hereinafter referred to as banks) having a size equal to or larger than the payload length of one cell,
When the time division multiplexed CBR data of multiple speeds is written to the bank for each channel number and accumulated up to the buffer accumulation amount that enables the assembly of AAL1 cells,
Buffer writing means for outputting the channel number,
AAL1 for assembling AAL1 cells in the order in which the channel numbers input from the buffer writing means are input
A cell assembling means is provided so that the payload length of the AAL1 cell can be made variable for each channel number.

More specifically, a channel number identification section for identifying a channel number from a time slot number of time division multiplexed CBR data of multiple speed, a write bank number for each channel number, and an address in the bank are managed. A write address management table, a write byte number management table that manages how many bytes of data are stored in each bank for each channel number, and a payload byte number storage table that stores the effective data length of the AAL1 cell for each channel number. A next bank management table that manages a bank number and the number of the next bank as logical chain information, an empty bank queue that stores the number of an unused bank, and various tables and function blocks that control or store data. Buffer write control unit to update and AAL
A cell assembly standby queue that stores the channel numbers accumulated up to the buffer accumulation amount that enables the assembly of one cell in a queue format, and a read address management table that manages the read bank number for each channel number and the address in the bank. , An AAL1 cell assembling section for assembling the AAL1 cell, and a buffer reading control section for controlling the various tables and functional blocks or updating the data.

With this configuration, the buffer write control unit refers to the write byte number management table and the payload byte number storage table, and compares whether the write byte number is equal to or larger than the number of payload bytes that can be assembled in the AAL1 cell. Then, when the number of payload bytes that can be assembled is equal to or larger than the number of payload bytes that can be assembled, the payload length can be made variable for each channel number by assembling the AAL1 cell.

In storing the CBR data in the bank, each bank is fully used by managing a write address and a read address, and a bank number and a subsequent bank number are logically connected. The next bank management table manages the chain information, and the unused bank number manages the number of the unused bank.
It was possible to use it effectively with a minimum amount of buffer.

In order to solve the second problem, the present invention has the following constitution.

With the above-mentioned configuration, the AAL1 cell assembling unit of the AAL1 cell assembling unit is provided with a dummy data generating unit for generating dummy data, and the payload byte number storage table is used to load the payload from the channel number input from the buffer writing unit. Read the number of payload bytes of the fixed bit rate data to be stored in the bank, and read the fixed bit rate data for the number of payload bytes from the bank, and then to the remaining payload, dummy data from the dummy data generator. By providing a means for generating and outputting, the fixed bit rate data of the arbitrary speed is accommodated in an arbitrary number of bytes in the payload of one cell of the ATM cell for each channel number, and dummy data is stored in the rest of the payload. The assembled ATM cells can be assembled.

As another means for solving the problems, in the above-mentioned configuration, in the channel number identifying unit, the fixed bit rate data of different channel numbers having the same destination are assumed to be the same channel number, and the same channel number is used. By writing to the bank, it is possible to assemble an ATM cell that accommodates fixed bit rate data of different channel numbers having the same destination in the payload of one cell of the ATM cell.

[0040]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a cell assembling apparatus according to the present invention and an embodiment for shortening a cell assembly delay time using the same will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of a cell assembling apparatus for realizing the present invention. In the figure, a buffer memory 100 for storing time-division multiplexed multi-rate CBR data S101 input from an STM network is composed of a plurality of banks 101 divided into arbitrary sizes. The buffer writing means 102 is a time division multiplexed CBR data S101 of multiple speed.
Is written in the bank 101 for each channel number, and has a function of outputting the channel number S108 when the buffer storage amount that enables the assembly of AAL1 cells is stored. In addition, the AAL1 cell assembling means 103 uses the channel number S108 input from the buffer writing means 102.
As a result, the AAL1 cells for each channel are assembled in the input order and the AAL1 cell S117 is sent to the ATM network.

Further, the details of each block will be described.

The bank 101 uses a 2-port random access memory so that the write operation and the read operation can be performed asynchronously, and the bank size is set to a power of 2 to facilitate address management. did. For example, FIG. 2 shows a bank configuration. Bank size 64
The byte (26) is used, and the lower 6 bits of the memory address are used as the in-bank address 201. The high-order bit is bank number 202
When writing to the bank, writing is performed in order from the smallest address 201 in the bank, and reading is also performed in order from the smallest address.

When the write side has written up to the last address of the bank (ie, the lower 6 bits are "111111"), the bank number S110 of the unused empty bank is read from the empty bank queue 109 described later, and the same. Write operation to. On the reading side, when the last address is read, the next bank number management table 108 to be described later is displayed.
The next bank number S113 is read, and the same read operation is performed.

Next, details of the buffer writing means 102 will be described.

First, the buffer writing means 102 receives the time division multiplexed CBR data S of multiple speed inputted from the STM network.
From 101, the channel number identifying unit 104 determines the channel number.

The method of discriminating this channel number is shown in FIGS.
This will be described with reference to FIG.

As shown in FIG. 3, the time division multiplexed CBR data S101 is composed of a clock 301 and a frame pulse.
The time slot number 304 is decided for 302,
The channel number 305 is fixed to the time slot number 304 for each call setting. That is, the channel number identification unit 104 associates the time slot number 304 of the time division multiplexed CBR data 303 of the multiple speed with the channel number 305.

The channel number identification section 104 has a structure as shown in FIG. 4, and a time slot number counter 401 for counting a time slot number from a clock S401 and a frame pulse S402, the time slot number S404,
A time slot number / channel number conversion table 402 that correlates channel numbers and outputs S405 is provided.

The time slot number / channel number conversion table 402 has a table structure as shown in FIG. 5, and is set by the host device which performs call connection control for each call and input from the time slot number counter 401. Channel number 5 with time slot number 501 as address
Output 02.

Next, the channel number S102 output from the channel number identification unit 104 is stored in the buffer write control unit 110.
The buffer write control unit 110 reads the write address S103 of the bank 101 of the channel number from the write address management table 105.

FIG. 6 shows the write address management table 10
5 shows the table structure. The write address management table 105 uses the channel number 601 as an address and stores the write address 602 of the bank 101 in the data.

That is, the buffer write controller 110
Reads the write address S103 of the bank 101 using the channel number S102 output from the channel number identification unit 104 as an address, and writes the CBR data at that address. In the buffer write control unit 110,
When the in-bank address to be written to the bank 101 is the final address, the empty bank number S110 is read from the empty bank queue 109, and the start address of the bank number is written and updated in the write address management table 105. Further, the updated bank number S109 is set in the next bank number management table 108 using the previous bank number as an address.
Write.

FIG. 7 shows the structure of the empty bank queue 109. The empty bank queue 109 is composed of a first-in first-out (FIFO) type memory, and stores the bank number 701 of the empty bank in the data.

Further, FIG. 8 shows the next bank number management table.
The structure of 108 is shown. The next bank number management table 108 uses the previous bank number 801 as an address, and stores the number 802 of the next subsequent bank in the data.

At the same time as the write operation to the bank 101, the buffer write control unit 110 inputs the channel number S102 to the write byte number management table 106 and the payload byte number storage table 107, and corresponds to the corresponding channel from each. The read data S107 and S106 are read out.

FIG. 9 shows the write byte count management table 10.
The structure of 6 is shown. The write byte count management table 106 is
The number of bytes of CBR data written in the bank of the channel number 901, using the channel number 901 as the address 902
Is stored.

FIG. 10 shows the structure of the payload byte number storage table 107. The payload byte number storage table 107 uses the channel number 1001 as an address, and stores the CBR data length (effective data length) 1002 stored in the payload in one cell of the channel number as data. The buffer write control unit 110 writes the CBR data to the bank based on the write address S103 read from the write address management table 105, and at the same time, writes the write byte number 902 read from the write byte number management table 106. Add 1 byte. Further, the number of payload bytes 1002 read from the payload byte number storage table 107 is compared with the number of write bytes 902 plus 1 byte, and if the number of write bytes plus 1 byte is equal to or greater than the number of payload bytes, The channel number S108 is output, the number of write bytes is subtracted by the number of payload bytes, and the number of write bytes is again written in the write byte number management table 106.
The write byte count 902 is updated. If the number of write bytes is less than the number of payload bytes, the write byte number management table 106 is updated by writing the write byte number 902 that is one byte larger. The above is the operation example of the buffer writing means.

The write operation to the bank 101 described above will be described with reference to the time chart of FIG. The buffer writing means 102 has a clock 1107, a frame pulse 1108, and CBR data 1 at the timings shown in FIG.
109 is input, and the buffer writing means 102 operates each unit by the system clock 1106 having a speed four times as fast as the clock.

First, at timing 1 1101, the time slot number counter 401 counts from the clock 1107 and the frame pulse 1108 to obtain the time slot number.
Judge 1110.

At timing 2 1102, the timing number / channel number conversion table 402 determines the channel number 1111 from the time slot number 1110. The channel number 1111 is input to the buffer write control unit 110.

At timing 3 1103, the buffer write control unit 110 uses the write address management table 105, the write byte number management table 106, and the payload byte number management table 107 to determine the write address 1112, the write byte number 1113, and the payload byte number. Read 1114.

Next, at timing 4 1104, the buffer write controller 110 writes 1120 the CBR data 1109 to the bank 101, adds 1 to the write address 1112, and at the next timing 1 1105, writes address management table 105. Written on 1119, updated.

If the write address 1112 read at the timing 3 1103 is the final address in the bank, the empty bank queue 109 is reached at the timing 4 1104.
The empty bank number 1117 is read out, and at the next timing 1 1105, the start address of the empty bank 1117 is written in the write address management table 105.
9, update.

Further, in the next bank number management table 108, writing 1118 is performed with the bank number for which the writing has been performed as an address and the empty bank number 1117 for which the reading has been performed in the data. Also, the buffer write control unit 110 adds 1 to the number of write bytes 1113 read at the timing 3 1103 to obtain the number of payload bytes 1114.
It is determined whether the number of written bytes is equal to or more than the number of payload bytes by comparing with.

When the number of written bytes is equal to or greater than the number of payload bytes, at timing 4 1104, the channel number 1115 is written in the cell assembly waiting queue 111 of the AAL1 cell assembly means 103, and the number 1 is written in the written byte number management table 106. The value obtained by subtracting the payload byte number from the added write byte number is written 1116 as the write byte number and updated.

If the number of written bytes is less than the number of payload bytes, the written byte number management table
A value obtained by adding 1 to the number of written bytes is written in 106 and updated by 1116.

Next, the details of the AAL1 cell assembling means 103 will be described with reference to FIG.

First, the buffer read control unit 114 determines the channel number S that can be transmitted from the cell assembly standby queue 111.
112 is read out, and the cell assembly instruction S116 of the channel number is sent to the AAL1 cell assembly section 113. Further, the header of the AAL1 cell of the channel number is read from the header information storage table 115 and input to the AAL1 cell assembling unit 113 for S118.

FIG. 12 shows the structure of the header information storage table 115.

The header information storage table 115 uses the channel number 1201 as an address, and data of 5 bytes of ATM.
The header 1202 is stored. Also, the buffer reading control unit
114 reads the read address of the channel number from the read address management table 112, and at the same time, reads the payload byte number of the channel number from the payload byte number storage table 107. As shown in FIG. 13, the read address management table 112 has a channel number 130
Address 1 and data is bank 1 of that channel number
The read address 1302 of 01 is stored. The buffer read control unit 114 reads the data of the relevant channel from the bank 101 by the number of the payload bytes, from the address. Further, at this time, when it becomes the last address of the in-bank address, the next bank number S113 is read from the next bank number management table 108, and the bank number for which the reading is completed is set as the empty bank S114, and the empty bank queue is set. Ten
Output to 9.

Further, the AAL1 cell assembling section 113 has the AAL read from the bank 101 by the buffer reading control section 114.
An AAL1 header, a pointer, and dummy data are inserted into one cell, if necessary, and if no data is stored in the cell assembly waiting queue at the cell transmission timing, an empty cell is generated and inserted.

FIG. 14 shows the structure of the AAL1 cell assembly unit 113.

The AAL1 cell assembling section 113 has a sequence for managing an AAL1 header generating section 1409 for generating an AAL1 header, a pointer generating section 1402 for generating a pointer, and a sequence number (SN) included in the AAL1 header for each channel. A number table 1408, a down counter unit 1401 that counts an offset value for generating a pointer, a down counter table 1404 that manages the counter value of the down counter for each channel, and a block length of structured data for each channel. A block length management table 1403 that manages each, a pointer history table 1407 that manages a history of whether a pointer has been inserted for each channel, a dummy pointer generation unit 1405 that generates a dummy pointer instead of the pointer, Empty cell generation unit 14 for generating empty cells
10 and an output control unit 1406 that controls the various blocks.

The detailed operation will be described.

First, when the input channel number S1404 is unstructured data, the down counter unit 1301, the down counter table 1404, the block length management table 1403, the pointer history table 1407, the dummy pointer generation unit 1405,
The pointer generator 1402 does not operate.

The channel number S1404 input from the buffer read control unit 114 is output S1416 from the output control unit 1406 to the sequence number table 1408, and the sequence number table 1408 outputs S1416 the SN of the corresponding channel number to the output control unit 1406. .

Thereafter, the output control unit 1406 outputs S1419 the SN and CSI to the AAL1 header generation unit 1409, and at the same time, writes the next SN to the sequence number table 1408 S141.
6, update.

The AAL1 header generator 1409 has an output controller 140
The error detection code (CRC) and parity (P) are calculated from the SN and CSI from 6 to generate the AAL1 header, and the AAL1 header is generated.
It is sent at the insertion timing of one header.

FIG. 15 shows the sequence number table 1408.
Is shown. The sequence number table 1408 has a channel number as an address, and stores the next sequence number for each channel number in the data.

When the channel number is structured data, the input channel number S1404 is input to the down counter table 1404, the block length management table 1403, and the output control unit 1405. Down counter table 14
05 outputs the down counter value of the relevant channel number S140
Then, the block length management table 1403 outputs S1406 the block length of the channel number. Down counter 140
4 has a function of counting the offset value of the head position of the structured data, when the channel top signal S1402 indicating the head of the structured data is received, the block of the channel read from the block length management table 1403 Length S140
6 is loaded into the counter, and the down counter is operated in the payload portion of the AAL1 cell based on the cell top signal S1403 indicating the head of the AAL1 cell. In other words, the down counter unit 1401 performs counting processing commonly for all channels,
Down counter table 1404 and block length management table
1403 stores data for each channel, reads data from each table for each channel number, performs loading or counting, and when the count for one AAL1 cell is completed, writes the data again to each table S1406 ,
S1407 is updated.

FIG. 16 shows the configuration of the down counter table 1404, and FIG. 17 shows the configuration of the block length management table 1403 1403.
Is shown.

The down counter table 1404 uses the channel number 1601 as an address and stores the down counter value 1602 for each channel in the data. Block length management table
The 1403 uses the channel number 1701 as an address and stores the block length 1702 for each channel in the data.

The operation of the down counter 1401 when the channel number is structured data will be described with reference to a time chart in FIG.

In FIG. 18, as an example, the channel number is "A" 18
In 04, it is assumed that the block length 1808 is a 24-byte 1.5 Mb / s channel, the AAL1 cell has an even sequence number in the AAL1 header, and a pointer is inserted.

The cell top signal 1802 indicating the beginning of the cell is used as a trigger to set the down counter value 18 of the channel number A 1804.
07 reads down counter table 1404. The read down counter value (4) 1804 is loaded 1806 into the down counter 1401 and this down counter value (4) 1804 is inserted as a pointer at the position of the pointer 1801 of the AAL1 cell.

Further, the down counter 1401 keeps the counter enable 1803 asserted (that is, AAL
(Payload part of 1 cell) is counted, and when the channel top 1805 is input, the block length (24) 1808 of the block length management table 1403 is set to the down counter 1401.
To load.

The last byte 1810 of the AAL1 cell (ie 5
After counting up to 3 bytes), the down counter value (6) 1811 is written to the down counter table 1404. The above operation is performed for each input AAL1 cell (for each channel).

As described above, the pointer is inserted once between the sequence numbers 0 to 7 and when the sequence number is even. Output control unit 1406
Is a pointer history table that stores the history of whether or not the pointer was inserted for each channel, while reading the sequence number of the channel number for assembling the AAL1 cell from the sequence number table 1408.
S1415 read from 1407.

Here, if the insertion of the pointer for the channel number has not been done and the sequence number is an even number, when the value of the down counter table 1404 is loaded into the down counter 1401, if the down counter value is 94 or less, Insert a pointer. When the down counter value is 94 or less, the pointer is inserted because if the payload length of AAL1 cell is 47 bytes, the even sequence number is every 2 cells, so double the payload length. This is because it is necessary to insert a pointer for the following down counter values.

When the pointer is inserted, the pointer history table 1407 is set to the pointer insertion completion, and when the sequence number becomes 7, the pointer history is updated to the pointer insertion not made. FIG. 19 shows the structure of the pointer history table 1407. The pointer history table 1407 has a channel number as an address, and the data stores a flag indicating whether or not the pointer insertion for each channel number is completed.

The above is a description of the cell assembling apparatus, and in particular,
It is an embodiment of AAL1 cell assembly when the time division multiplexed CBR data is unstructured data and structured data.

Next, an embodiment for reducing the cell assembly delay time will be described.

As a method of shortening the cell assembly delay time, as described above, the partial fill that makes the effective data length stored in the payload in one cell an arbitrary number of bytes and the channel signal having the same transmission destination are used. Is stored in the payload of the same cell.

First, an embodiment of partial fill will be described.

The basic configuration is the same as that shown in FIG. 1, and the effective data length of the partial fill for each channel is stored in the payload byte number storage table 107. As a result, the buffer writing unit 102 can operate similarly to the buffer writing operation described above.

Further, in the AAL1 cell assembling means 103,
The AAL1 cell assembly unit 113 is configured as shown in FIG.

A dummy data generation unit 2001 for generating dummy data is added, and a signal line S2002 for inputting the number of bytes of partial fill is added to the output control unit. The effective data length of the partial fill is determined by the buffer read control unit 114.
Is read from the payload byte number storage table 107, and input to the S111 and AAL1 cell assembling unit 113 at S116. The buffer read control unit 114 reads the data corresponding to the number of partial fill bytes from the bank 101, and the AAL1 cell assembling unit 113.
The AAL1 cell assembling unit 113 sends dummy data from the dummy data generating unit 2001, following the data.

As a result, it is possible to assemble an AAL1 cell in which the valid data has an arbitrary number of bytes in the payload of one cell of the AAL1 cell and the remaining payload contains dummy data.

Furthermore, by reducing the effective data length in the payload of one AAL1 cell, the time for accumulating the fixed bit rate data for the effective data length in the buffer memory is shortened, so that the delay for assembling the AAL1 cell is delayed. It is possible to shorten the time.

Next, an embodiment of the composite cell will be described.

The basic configuration is the same as that of FIG. 1, and assuming that different channel numbers having the same destination are the same channel number, the time slot number / channel number conversion of the channel number identifying unit 104 of FIG. 4 is performed. It is realized by setting the table 402.

That is, by assuming different channel numbers having the same destination as the same channel number, the buffer writing means 102 writes CBR data of different channel numbers in the same bank 101.

The AAL1 cell assembling means 103 operates the AAL as usual.
By assembling 1 cell, 1 of AAL1 cell is obtained.
Assembling of an AAL1 cell in which fixed bit rate data of different channel numbers having the same destination are accommodated in the payload of the cell is realized.

Therefore, by accommodating fixed bit rate data of different channel numbers having the same destination in the payload of one cell of AAL1 cell, the time for accumulating fixed bit rate data for each channel in the buffer memory is shortened. Therefore, the delay time for assembling the AAL1 cell can be shortened.

[0106]

According to the present invention, it is possible to assemble time division multiplexed multi-rate CBR data into an AAL1 cell, and particularly, regardless of structured data or unstructured data, the payload length of the AAL1 cell. It is possible to assemble it to AAL1 cell even when is variable.

Further, according to the present invention, even when the cell assembly delay time of a telephone service or the like affects the quality, by making the effective data length of the AAL1 cell arbitrary, the AAL1 cell can be generated without deterioration of the quality. Can be assembled.

Further, according to the present invention, the effective data length of the AAL1 cell described above can be arbitrarily set for each channel, so that the cell assembly delay time can be shortened flexibly for each channel. It will be possible.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing a configuration of a multiple access cell conversion device of the present invention.

FIG. 2 is a configuration diagram showing a configuration example of a bank of the multiplex multiple cell conversion device of the present invention.

FIG. 3 is a timing chart showing an example of CBR data input to a channel number identification unit of the multiplex cell conversion device of the present invention.

FIG. 4 is a block diagram showing a configuration of a channel number identification unit of the multiplex cell conversion device of the present invention.

FIG. 5 is a table configuration diagram showing a configuration of a time slot number / channel number conversion table of the multiplex cell conversion device of the present invention.

FIG. 6 is a table configuration diagram showing a configuration of a write address management table of the multiplex cell conversion device of the present invention.

FIG. 7 is a configuration diagram showing a configuration of an empty bank queue of the multiplex cell conversion device of the present invention.

FIG. 8 is a table configuration diagram showing a configuration of a next bank number management table of the multiplex cell conversion device of the present invention.

FIG. 9 is a table configuration diagram showing a configuration of a write byte count management table of the multiplex cell conversion device of the present invention.

FIG. 10 is a table configuration diagram showing a configuration of a payload byte number management table of the multiplex cell conversion device of the present invention.

FIG. 11 is a timing chart showing the write operation to the bank of the buffer write means of the multiplex multiple cell device of the present invention.

FIG. 12 is a table configuration diagram showing a configuration of a header information storage table of the multiplex cell conversion device of the present invention.

FIG. 13 is a table configuration diagram showing the configuration of a read address management table of the multiplex cell conversion device of the present invention.

FIG. 14 is a block configuration diagram showing a configuration of an AAL1 cell assembling unit of the multiple access cell conversion device of the present invention.

FIG. 15 is a table configuration diagram showing a configuration of a sequence number table of the multiple access cell conversion device of the present invention.

FIG. 16 is a table configuration diagram showing a configuration of a down counter table of the multiple access cell conversion device of the present invention.

FIG. 17 is a table configuration diagram showing the configuration of a block length management table of the multiple access cell conversion device of the present invention.

FIG. 18 is a timing chart showing the detailed operation of the AAL1 cell assembling unit of the multiplex multiple cell conversion device of the present invention.

FIG. 19 is a table configuration diagram showing the configuration of a pointer history table of the multiplex multiple cell conversion device of the present invention.

FIG. 20 is a block configuration diagram showing another configuration of the AAL1 cell assembling unit of the multiple access cell conversion device of the present invention.

FIG. 21 shows CBR data and A of the multiplex cell conversion device of the present invention.
The figure which shows the mode of conversion with a TM cell.

FIG. 22 is a format diagram showing the format of an AAL1 cell of the multiplex multiple cell conversion device of the present invention.

FIG. 23 is a format diagram showing a format of a partial fill of the multiplex multiple cell conversion device of the present invention.

FIG. 24 is a format diagram showing a format of a composite cell of the multiplex cell conversion device of the present invention.

[Explanation of symbols]

101 ... Bank, 102 ... Buffer writing means, 103 ... AA
L1 cell assembling means, 104 ... Channel number identification unit, 105 ... Write address management table, 106 ... Write byte number management table, 107 ... Payload byte number management table, 108 ... Next bank number Management table, 109 ... Empty bank queue, 110 ... Buffer write control unit, 111 ... Cell assembly waiting queue, 112 ... Read address management table, 113 ... AAL1 cell assembly unit, 114 ... ..Buffer read control unit, 115 ... Header information storage table, S101 ... CBR data, S102 ... Channel number, S103, S104 ... Write address, S105 ... Read address, S106 ..Payload byte number, S107 ... Write byte number, S108 ... Channel number, S109 ... Next bank number, S110 ... Empty bank number, S1
11 ... Payload byte number, S112 ... Channel number, S113
・ ・ ・ Next bank number, S114 ... Empty bank number, S115 ... Read address, S116 ... Channel number, S117 ... AAL1 cell, S118 ... ATM header data, S119 ... Channel Number two
01-in-bank address, 202-bank number, 301-clock, 302-frame pulse, 303-CBR data, 304
... Time slot, 305 ... Channel number, 401 ... Time slot number counter, 402 ... Time slot number /
Channel number conversion table, S401 ... Clock, S402 ...
Frame pulse, S403 ... CBR data, S404 ... time slot number, S405 ... channel number, 501 ... time slot number, 502 ... channel number, 601 ... channel number,
602 ... Write address, 701 ... Unused bank number, 80
1 ... Bank number, 802 ... Next bank number, 901 ... Channel number, 902 ... Write byte count, 1001 ... Channel number, 1002 ... Payload byte count, 1101 ... Timing
1, 1102 ・ ・ ・ Timing 2, 1103 ・ ・ ・ Timing 3, 1104 ・ ・ ・
Timing 4, 1105 ... Timing 1, 1106 ... System clock, 1107 ... Clock, 1108 ... Frame pulse, 11
09 ・ ・ ・ CBR data, 1110 ・ ・ ・ Time slot number, 1111 ・ ・ ・
Channel number, 1112 ... Write address, 1113 ... Write byte count, 1114 ... Payload byte count, 1115 ... Channel number, 1116 ... Write byte count, 1117 ... Unused bank number, 1118 ... Next bank number, 1119 ... Write address, 1120 ... CBR data, 1201 ... Channel number, 120
2 ... Header information, 1401 ... Down counter, 1402 ... Pointer generation unit, 1403 ... Block length management table, 1404 ...
Down counter table, 1405 ... Dummy pointer generation unit, 1406 ... Output control unit, 1407 ... Pointer history table, 1408 ... Sequence number table, 1409 ... AAL1
Header generation unit, 1410 ... Empty cell generation unit, S1401 ... AAL1 cell data, S1402 ... Channel top signal, S1403 ... Cell top signal, S1404 ... Channel number, S1405 ... Bank reading Dashi instruction signal, S1406 ... Block length, S1407 ... Down counter value, S1408 ... Pointer generation instruction signal, S1409, S1
410 ・ ・ ・ Channel number, S1411 ・ ・ ・ Pointer data, S1412 ・
..Dummy pointer data, S1413 ... Select signal, S141
4 ... Down counter value, S1415 ... Pointer history, S1416
..Sequence number, S1417 ... AAL1 cell data, S141
8 ... Empty cell generation instruction signal, S1419 ... AAL1 header generation instruction signal, S1420 ... Empty cell data, S1421 ... AAL1 header data, S1422 ... Select signal, S1423 ... AAL1 cell data ,
1501 ... Channel number, 1502 ... Sequence number, 1601 ...
・ Channel number, 1602 ・ ・ ・ Down counter value, 1701 ・ ・ ・ Channel number, 1702 ・ ・ ・ Block length, 1801 ・ ・ ・ Pointer, 18
02 ... cell top signal, 1803 ... counter enable signal, 1804 ... channel number, 1805 ... channel top signal, 1806 ... down counter value load, 1808 ... block length, 1809 ...・ Block length load, 1810 ... 53 bytes, 1811
... Down counter value, 1812 ... Down counter value write, 1901 ... Channel number, 1902 ... Pointer history, 2001
... Dummy data generation unit, S2001 ... Dummy data generation instruction signal, S2002 ... Payload byte number, 2101 ... CBR data, 2102 ... AAL1 cell, 2201 ... ATM header, 2202 ...・ AAL1
Header, 2203 ... Payload, 2204 ... Pointer, 2205 ...
・ Convergence sublayer display, 2206 ... Sequence number, 2207 ... Error correction code, 2208 ... Even parity, 22
09 ... Sequence number field, 2210 ... Sequence number protection field, 2211 ... Offset value, 2301 ... Effective data length, 2302 ... Dummy data,

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Kenichi Oka 180 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi Communication Systems Co., Ltd.

Claims (11)

[Claims] 1. An ATM cell assembling / disassembling apparatus for converting each of a plurality of types of fixed bit rate data of arbitrary types (hereinafter, referred to as multiple speeds) which are time-division multiplexed into an ATM cell (Asynchronous Transfer Mode Cell). A buffer memory that stores the fixed bit rate data for each channel number in a bank whose inside is divided into an arbitrary size, and writes to the bank for each channel number,
When the fixed bit rate data of the storage amount that enables the assembling of M cells is accumulated in the buffer memory, a writing unit that outputs the channel number, and the channel number input from the writing unit, An ATM cell assembling / disassembling apparatus having an AAL1 cell assembling means for assembling ATM cells for respective channel numbers in the order of input. 2. The ATM cell assembling / disassembling apparatus according to claim 1, wherein the buffer memory is a 2-port random access memory, and the bank size of the buffer memory is a power of 2. Decomposing device. 3. The ATM cell assembling / disassembling apparatus according to claim 1, wherein the write control unit performs writing and reading to / from a bank of the buffer memory in an ascending order of addresses. 4. The ATM cell assembling / disassembling apparatus according to claim 1, wherein the channel number is fixed and fixed for each call setting with respect to a time slot number defined for the fixed bit rate data. ATM cell assembling and disassembling device. 5. The ATM cell assembling / disassembling apparatus according to claim 1, further comprising: a next bank number management table for managing chain information in which the banks storing the constant bit rate data for each channel number are logically connected. An empty bank queue that manages unused bank numbers of the plurality of banks, reads data from the bank based on the data of the next bank management table, and when the read is the final address of the bank, An ATM cell assembling / disassembling apparatus, comprising: a read control unit for outputting the bank number to the empty bank queue as an unused bank. 6. The ATM cell assembling / disassembling apparatus according to claim 1, wherein a write byte number management table for managing an accumulated amount of the fixed bit rate data stored in the bank for each channel number, and an ATM cell payload. And a payload byte number storage table that stores the number of bytes of the fixed bit rate data stored for each channel number, the write control unit, the write unit, the write byte number management table, the payload byte The data of the number storage table are compared, and if the data of the write byte number management table is larger than the data of the payload byte number storage table, it is determined that cell assembly is possible, and the channel number is set in the AAL1 cell assembly means. An ATM cell assembling / disassembling device characterized by outputting. 7. The cell assembling apparatus according to claim 6, wherein the AAL1 cell assembling means accommodates the multi-rate fixed bit rate data as a variable number of bytes in a payload of one cell of an ATM cell for each channel number. An ATM cell assembling / disassembling device, which assembles the above-mentioned ATM cells. 8. The ATM cell assembling / disassembling apparatus according to claim 6, wherein the AAL1 cell assembling means stores the fixed bit rate data to be stored in the payload from the payload byte number storage table based on the channel number input by the writing means. A read control unit for reading the number of payload bytes and reading the fixed bit rate data for the number of read payload bytes from the bank, and dummy data corresponding to the difference between the payload data and the data read from the bank An ATM cell assembling / disassembling apparatus, comprising: a dummy data generating unit for generating and outputting. 9. The AT according to any one of claims 1 to 8.
In the M cell assembling / disassembling apparatus, the writing means writes the fixed bit rate data of different channel numbers having the same destination in the same bank, and stores the fixed bit rate data of a storage amount capable of assembling ATM cells. When stored, the channel number is output to the AAL1 cell assembling means, and the AAL1 cell assembling means assembles ATM cells in the order of input from the channel number input by the writing means. An ATM cell assembling / disassembling device characterized by: 10. The ATM cell assembling / disassembling apparatus according to claim 9, wherein the AAL1 cell assembling means has the same destination in the payload of one ATM cell from the channel number inputted by the writing means. An ATM cell assembling / disassembling apparatus, which assembles ATM cells containing the fixed bit rate data of different channel numbers. 11. An ATM cell (Asynchronous Transfer Mode Cell) is provided for each of a plurality of types of fixed bit rate data of arbitrary speeds (hereinafter referred to as multiple speeds) that are time-division multiplexed.
In the ATM cell assembling / disassembling method, the fixed bit rate data is stored in banks divided into arbitrary sizes for each channel number, and the fixed bit rate data having a storage amount capable of assembling ATM cells is stored. When stored in the bank, the channel number is output, and an ATM cell for each channel number is assembled in the input order from the channel number.
Cell assembly and disassembly method.