JPH09204204A - Method for checking ladder sequence circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To check whether or not correct logic is constituted by checking the presence of a specified input element, absence of an output element and absence of internal logic so as to recognize the contradiction of logic in a combined ladder sequence circuit. SOLUTION: A sequencer 10 controls the operation of a production machine. I/O 12 mediates the exchange of signals between the sequencer 10 and the input/ output elements. The look indiator 14 of a check NG block look-displays its check result. Then, the sequencer 10 itself checks a ladder sequence circuit. That is, the contradiction of logic in the combined ladder sequence circuit is recognized by respectively checking presence of the input logical element which is normally in the on-state in spite of a change in the on/off state of a contact, presence of the input logical element which is normally in the off- state in spite of a change in the on/off state of the contact, absence of the output element which is turned on/off by internal logic and absence of internal logic which turns on/off the output element.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention, for example, allows a program to be created by combining existing modularized programs (ladder sequence circuits), or after modifying an existing program. The present invention relates to a method for checking a ladder sequence circuit that checks whether or not it is correct.

[0002]

2. Description of the Related Art A sequencer is used to control a small-scale production machine to a large-scale production machine. Input elements such as various sensors and switches and output elements such as motors and solenoids are connected to this sequencer. In a large-scale production machine, the number of input elements and output elements becomes enormous.

Generally, a sequencer includes a ladder sequence circuit that associates an input element with an output element. This ladder sequence circuit is generally created by a designer inputting one element at a time while operating an input device, or by combining ladder sequence circuits that are modularized and stored in existing equipment.

[0004]

When creating a new sequence circuit, for a relatively small-scale production machine,
It is possible to build a ladder sequence circuit by inputting one element at a time while looking at the ladder diagram created in advance, but in a large-scale production machine, since the number of input / output elements is enormous as described above, Since the ladder sequence circuit also becomes complicated, and therefore the method of inputting one element at a time is inefficient, in such a case, as shown in FIG. A simple ladder sequence circuit. That is, a ladder sequence circuit is created by a method of taking out modules from the standard ladder sequence 1 and the standard ladder sequence 2 stored in two types of equipment and synthesizing the extracted modules.

According to such a method, it is certainly possible to efficiently create a ladder sequence circuit,
Since the ladder sequence circuit is assembled simply by the operation of synthesis, the ladder sequence circuit after synthesis contains logic inconsistency or logic duplication occurs, which causes the machine to make unintended movements or runaway. Or, on the contrary, it may become stuck or the operation speed may decrease. In addition, such a problem may be a problem even when a large-scale production machine is modified.

In order to avoid such a problem in advance, it is necessary to complete the assembled ladder sequence circuit. It is necessary to debug on a desk or actually operate the production machine to obtain a desired movement. Although it is adjusted so that it will be done, it is difficult for humans to perform complete debugging because all are done by humans. Also, when I try to do a full debug,
It takes a long time, and the merit of the module synthesis that easily builds the ladder sequence circuit is halved. Note that such a problem also occurs when a large-scale change is made to the existing ladder sequence circuit.

The present invention has been made in order to solve such a conventional problem, and provides a method of checking a ladder sequence circuit for checking whether or not the ladder sequence circuit after creation constitutes a correct logic. For the purpose of provision.

[0008]

The present invention for achieving the above object is constituted by the following means.

In the first aspect of the present invention, the logic contradiction of the assembled ladder sequence circuit is remedied by the existence of the input logic element which is always on even if the on / off state of the contact changes, and the contact The presence of input logic elements that are always off even if the on / off state changes, the absence of output elements that are turned on and off by internal logic, and the absence of internal logic that turns output elements on and off, respectively. It is a method of checking a ladder sequence circuit characterized by recognizing by checking.

By performing the above checks, it becomes possible to surely know the existence of a logic contradiction and the existence of unnecessary internal logic.

According to a second aspect of the invention, a ladder sequence circuit of a unit block is extracted from the assembled ladder sequence circuit, parallel logic is extracted from the extracted ladder sequence circuit, and the extracted parallel logic is extracted. It is a method of checking a ladder sequence circuit, characterized in that whether or not there is an inverse logic exists, and if there is an inverse logic, the fact that there is a logic contradiction that is always on is displayed.

By performing this check, the existence of contradictory parallel logic can be known.

The invention according to claim 3 extracts the ladder sequence circuit of the unit block from the assembled ladder sequence circuit, extracts the serial logic from the extracted ladder sequence circuit, and reverses the extracted serial logic. It is a method of checking a ladder sequence circuit, which checks whether or not a logic exists and, if there is an inverse logic, displays that there is a logic contradiction that is always off.

By performing this check, the existence of contradictory serial logic can be known.

According to a fourth aspect of the present invention, the ladder sequence circuit of the unit block is extracted from the assembled ladder sequence circuit, the internal logic included in the extracted ladder sequence circuit is extracted, and the extracted internal logic is extracted. Check for the presence of output elements that are turned on and off by
A method for checking a ladder sequence circuit is characterized in that when the output element does not exist, it is displayed that an inappropriate logic exists.

By making this check, it can be known that there is no output element corresponding to the internal logic.

According to a fifth aspect of the present invention, the ladder sequence circuit of the unit block is extracted from the assembled ladder sequence circuit, the output element included in the extracted ladder sequence circuit is extracted, and the extracted output element is extracted. Is a method for checking a ladder sequence circuit, wherein the existence of internal logic for turning on and off is checked, and if the internal logic does not exist, it is displayed that an inappropriate logic exists.

By performing this check, it can be known that the internal logic corresponding to the output element does not exist.

According to a sixth aspect of the present invention, one block of the ladder sequence circuit is extracted from the assembled ladder sequence circuit, the internal logic and the output element included in the extracted ladder sequence circuit are extracted, and While checking the existence of the output element which is turned on and off by the extracted internal logic, the existence of the internal logic which turns on and off the extracted output element is checked, and the output element does not exist,
When the internal logic does not exist, the ladder sequence circuit check method is characterized in that only the internal logic indicates that there is a logic defect.

By this check, it can be known that there is a logic defect in the internal logic.

[0021]

According to the method of checking the ladder sequence circuit of the present invention having the above-described structure, the following effects can be obtained.

(1) Effects common to the inventions described in claims 1 to 6 By checking the ladder sequence circuit by the method described in each claim, logic contradiction or unnecessary It becomes easy to discover the existence of such internal logic, and debug work can be performed efficiently.

(2) Effects peculiar to the respective inventions described in claims 1 to 6 In the invention described in claim 1, a contradictory logic is searched out from the entire ladder sequence circuit. Can be performed relatively easily, and the efficiency of debugging work can be improved.

According to the second aspect of the invention, the existence of contradictory parallel logic can be known.

According to the third aspect of the invention, the existence of contradictory serial logic can be known.

According to the invention described in claim 4, it can be known that there is no output element corresponding to the internal logic.

In the invention described in claim 5, it can be known that the internal logic corresponding to the output element does not exist.

In the invention described in claim 6, it can be known that there is a logic defect in the internal logic.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

The method of the present invention performs the following checks such as always-on check, always-off check, no output logic check, no input logic check, and only internal logic check. It enables you to know the existence of such internal logic.

FIG. 1 is a diagram showing a schematic configuration of an apparatus for executing the method of the present invention.

The sequencer 10 shown in the figure controls the operation of a production machine (not shown) and stores a ladder sequence circuit for controlling the operation. Further, in the present embodiment, the sequencer 10 itself performs the method of the present invention.

The I / O 12 mediates exchange of signals between the sequencer 10 and input / output elements (input elements such as various sensors and switches, output elements such as motors and solenoids).

List display 14 of check NG blocks
Is for inputting the check results performed by the sequencer 10 and displaying the check results in a list.

The sequencer 10 itself checks the ladder sequence circuit according to the present invention. As shown in the flowchart of FIG. 2, this check is always ON check (S1), always OFF check (S2), and no output logic check. (S3), no input logic check (S
4) Only the internal logic is checked (S5), and the check NG block list is displayed (S6) in this order, so that the contradiction of the logic of the ladder sequence circuit and the existence of unnecessary internal logic can be easily known. .

The processing procedure of the above six processing will be described in detail below.

The always-on check process shown in the flowchart of FIG. 3 is an embodiment corresponding to claim 2.

An example of this processing will be described with reference to the ladder sequence circuit of FIG.

The sequencer 10 opens the newly stored file of the ladder sequence circuit to be checked, and extracts one instruction block including the output coil which is an output element. In the circuit of FIG. 10, the block including the output coil [Y000] is taken out (S11). After the block is taken out, the parallel logic in the block is searched (S12), and it is judged whether or not the parallel logic exists (S13). If the parallel logic exists, whether the reverse logic exists in this parallel logic or not. It is determined whether (S14).

In the circuit of FIG. 10, the input logic element [X00
0], [X001], and [X002], and parallel logic composed of [R000] and [R000] exist, it is determined whether there is an inverse logic in these parallel logics. To be done. Parallel logic [R000], [R00
0], one side is the A contact and the other side is the B contact, so that there is an inverse logic, and this parallel logic is always O.
It is the N state, which is a meaningless logic of its existence.

If there is such a parallel logic which is always ON, a message to that effect is displayed (S15). The above processing is performed until the block end is reached (S16).

When the processing for one block is completed, the block NO is incremented (17) and this processing is performed for the next block. The above processing is continuously performed until the processing of the entire ladder sequence circuit is completed (S18).

By the above processing, it is possible to confirm the existence of the parallel logic which is always ON in the ladder sequence circuit of the sequencer 10.

The constant OFF check shown in the flowchart of FIG. 4 is an embodiment corresponding to claim 3.

An example of this processing will be described with reference to the ladder sequence circuit in FIG.

The sequencer 10 opens the newly stored file of the ladder sequence circuit to be checked and extracts one instruction block including the output coil which is an output element. In the circuit of FIG. 11, the block including the output coil [Y000] is taken out (S21). When the block is taken out, the serial logic in the block is searched (S22), and it is judged whether the serial logic exists (S23). If the serial logic exists, whether the same contact exists in this serial logic. It is also determined whether or not the contact is a positive / negative reverse contact (A contact and B contact) (S24, S2).
5).

If the same contact is a positive / negative reverse contact among the existing series contacts, this series logic is always in the OFF state, and therefore it is displayed that it is the logic in the normally OFF state (S).
26). In the circuit of FIG. 11, the input logic element [R00
0], [R000], and [R001] exist, and the same contact point of [R000] and [R000] exists, and since this same contact point is a positive and negative reverse contact point, it is permanently [Y000]. The output coil of does not turn on. This does not hold the logic.

If there is such a serial logic that is always off, a message to that effect is displayed. The above processing is performed until the block end is reached (S27).

When the processing for one block is completed, the block NO is incremented (S28) and this processing is performed for the next block. The above processing is continuously performed until the processing of the entire ladder sequence circuit is completed (S29).

By the above processing, it is possible to confirm the existence of the serial logic which is always in the OFF state in the ladder sequence circuit of the sequencer 10.

The output no logic check shown in the flowchart of FIG. 5 is an embodiment corresponding to claim 4.

An example of this processing will be described with reference to the ladder sequence circuit of FIG.

The sequencer 10 opens the newly stored file of the ladder sequence circuit to be checked and extracts one instruction block including the output coil which is an output element. In the circuit of FIG. 12, first, the block including the output coil [R000] is taken out (S31). When the block is taken out, it is determined whether the output coil is the internal arithmetic coil (S3
2) If the coil is an internal calculation coil, a recursive function process (process for determining whether or not the logic formed by the internal calculation coil is inappropriate) is performed (S3).
3). Since it is not necessary to perform processing unless it is the internal arithmetic coil, the block NO is incremented (S36),
Do this for the next block. The above processing is
The processing is continuously performed until the processing of the entire ladder sequence circuit is completed (S37).

As a result of the recursive function processing, the check is N
If it is G, a check NG is recorded (S3).
4, S35).

If it is determined in step S32 that the output is the internal arithmetic coil, the recursive function process of FIG. 6 is performed and the number of the retrieved coil is stored (S4).
1). In the circuit of FIG. 12, R000 is stored first. Next, another block is taken out from the head of the sequence circuit (S42), and it is determined whether or not there is a storage contact having the same number as the stored search coil number (S43). If the memory contact is not used, increment the block NO (S47),
Do this for the next block. The above processing is
The processing is continuously performed until the processing of the entire ladder sequence circuit is completed (S48).

If the memory contact is used, then it is determined whether the output coil is the Y coil (coil other than the internal calculation coil) (S44). In the circuit of FIG. 12, since the storage contact of R000 exists in the block of the internal arithmetic coil R100, this R100 is stored again as the search coil number, and the above processing is performed.

When a block in which the output coil connected to the memory contact is the Y coil is found by repeating the above-mentioned processing, the internal operation coil turns ON,
Since there is an output coil to be turned off, the logic is appropriate and it is stored that the result of the check is OK, and the process ends (S45, S46).

If the memory contact corresponding to the internal operation coil is not found despite the search up to the sequence end, the internal logic is inadequate, so the check is NG (S49).

In the circuit of FIG. 12, since there is no memory contact corresponding to the internal arithmetic coil of R200, the check is NG.

The no input logic check shown in the flowchart of FIG. 7 is an embodiment corresponding to claim 5.

An example of this processing will be described with reference to the ladder sequence circuit of FIG.

The sequencer 10 opens the newly stored file of the ladder sequence circuit to be checked and extracts one instruction block including the output coil which is an output element. In the circuit of FIG. 13, first, the block including the output coil [R001] is taken out (S51). When the block is taken out, its output coil is the Y coil (output coil other than the internal calculation coil)
Is determined (S52), and if it is an output coil, a recursive function process (process for determining whether or not the logic configured by the internal operation coil is inappropriate) is performed (S53). . If it is not a Y coil, there is no need to perform processing, so the block NO is incremented (S56) and this processing is performed for the next block.
The above processing is continuously performed until the processing for the entire ladder sequence circuit is completed (S57).

As a result of the recursive function processing, the check is N
If it is G, a check NG is recorded (S5).
4, S55).

If it is determined in step S52 that the output is the Y coil, the recursive function process of FIG. 8 is performed and the number of the search contact is stored (S61). In the circuit of FIG. 13, R000 is stored first. Next, the internal coil is taken out from the head of the sequence circuit (S62), and whether or not there is an X contact (a contact such as a Y coil or a limit switch) in a block having a memory contact having the same number as the stored retrieval coil number. Is determined (S63).

If the X contact exists in the block, the next internal coil is searched (S64, S66), and if the next coil does not exist, the check is NG (S67, S68). On the other hand, if there is an X contact, it is stored that the memory contact check is OK (S65).

By the above process, it is possible to find the existence of the inadequacy of the internal logic that the memory contact exists but the corresponding internal operation coil does not exist. That is, in the circuit of FIG. 13, it can be found that the internal arithmetic coil R000 corresponding to the memory contact R000 does not exist. If the internal arithmetic coil R000 does not exist, the memory contact is kept open forever, so this ladder sequence circuit does not operate.

The flowchart for checking only the internal logic shown in FIG. 9 is an embodiment corresponding to claim 6.

The sequencer 10 opens the newly stored file of the ladder sequence circuit to be checked, and extracts one instruction block including the output coil which is an output element. In the circuit of FIG. 14, first, the block including the output coil [R100] is taken out (S71). When the block is taken out, it is judged whether the output coil is the internal arithmetic coil (S7).
2) If it is an internal arithmetic coil, it is further determined whether or not the result of the above output logic check is NG (S73). When the output logic check is NG, it is determined whether or not the result of the input logic check is NG (S74). If the result is NG, it is recorded that the internal logic check is NG (S75). In other words, since there is a logic defect only in the internal logic, this defect is recorded.

The above processing is continuously performed until the processing of the entire ladder sequence circuit is completed (S
76, S77).

The sequencer 10 which has completed the above processing,
The result is displayed on the list display 14 of the check NG block.

The operator looks at this display and debugs the new ladder sequence program stored in the sequencer 10. Since the display 14 shows which logic inadequacy exists in which block, the debugging work can be performed very efficiently.

The above always ON check, always OF
The F-check, the output-logic-free check, the input-logic-free check, and the internal logic-only check can be effective even if each is performed independently, but preferably, all the processes are preferably performed.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of an apparatus for executing the method of the present invention.

FIG. 2 is a main flow chart of the method of the present invention.

FIG. 3 is a flowchart showing an always-on check process.

FIG. 4 is a flowchart showing an always-off check process.

FIG. 5 is a flowchart showing a check process without output logic.

FIG. 6 is a flowchart showing a recursive function process for checking no output logic.

FIG. 7 is a flowchart showing a check process without input logic.

FIG. 8 is a flowchart showing a recursive function process of checking for no input logic.

FIG. 9 is a flowchart showing a check process for internal logic only.

FIG. 10 is a diagram for explaining the always-on check process.

FIG. 11 is a diagram which is used to describe a normally-off check process.

FIG. 12 is a diagram for explaining the output logic-less check process.

FIG. 13 is a diagram which is used for explaining a check process without input logic.

FIG. 14 is a diagram provided for explaining a check process only for internal logic.

FIG. 15 is a diagram for explaining a conventional method of creating a ladder sequence circuit.

[Explanation of symbols]

 10 ... Sequencer, 12 ... I / O, 14 ... Check NG block list display.

Claims (6)

[Claims] 1. The logic inadequacy of the assembled ladder sequence circuit is determined by the existence of an input logic element which is always in the ON state even if the ON / OFF state of the contact changes, and the ON / OFF state of the contact changes. Recognize by checking the existence of input logic elements that are always off, the absence of output elements that are turned on and off by internal logic, and the absence of internal logic that turns output elements on and off. A method for checking a ladder sequence circuit, which is characterized in that 2. A ladder sequence circuit of a unit block is extracted from the assembled ladder sequence circuit, parallel logic is extracted from the extracted ladder sequence circuit, and whether or not inverse logic exists in the extracted parallel logic. The method for checking a ladder sequence circuit is characterized in that if there is an inverse logic, the fact that there is a logic contradiction that is always on is displayed. 3. A ladder sequence circuit of a unit block is extracted from the assembled ladder sequence circuit, serial logic is extracted from the extracted ladder sequence circuit, and whether or not inverse logic exists in the extracted serial logic. The method for checking a ladder sequence circuit is characterized in that if there is reverse logic, it is displayed that there is a logic contradiction that is always off. 4. A ladder sequence circuit of a unit block is extracted from the assembled ladder sequence circuit, internal logic included in the extracted ladder sequence circuit is extracted, and turned on and off by the extracted internal logic. A method for checking a ladder sequence circuit, which comprises checking the existence of an output element, and displaying the existence of inappropriate logic when the output element does not exist. 5. An internal circuit for extracting a ladder sequence circuit of a unit block from the assembled ladder sequence circuit, extracting output elements included in the extracted ladder sequence circuit, and turning on / off the extracted output element. A method for checking a ladder sequence circuit, characterized by checking the existence of logic and, if the internal logic does not exist, displaying that an inappropriate logic exists. 6. A ladder sequence circuit of a unit block is extracted from the assembled ladder sequence circuit, an internal logic and an output element included in the extracted ladder sequence circuit are extracted, and turned on by the extracted internal logic. , Check the existence of the output element that is turned off, while checking the existence of the internal logic that turns on and off the extracted output element, and if the output element does not exist and the internal logic does not exist, the internal A method for checking a ladder sequence circuit, wherein the fact that there is a logic defect is displayed only in the logic.