JPH09204154A - Digital device and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a segment driver, etc., capable of transmitting an enable signal between packages at a high speed. SOLUTION: This device is equipped with a 2nd 240-bit shift register SR constituted by coupling, for example, 12 segment drivers SDV1-SDV12 including, for example, 1st 20-bit shift registers SR transmitting enable signals according to a 1st clock signal CL2I substantially in series. Then an enable signal EIO2B is transmitted between, for example, the adjacent segment drivers SDV1 and SDV2 according to a 2nd clock signal F7QB which has a frequency a half as high as, for example, the 1st clock signal CL2I, and an enable signal EIO2B outputted from the segment driver SDV1 as the adjacent precedent stage to the segment driver SDV2 as the following stage is generated in synchronism with, for example, the 19-bit output of the 1st shift register SR.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital device and a semiconductor device, and more particularly to a technique which is particularly effective when used for a dot matrix type liquid crystal display device and a segment driver constituting a Y driver thereof.

[0002]

2. Description of the Related Art There is a dot matrix type liquid crystal display device using a liquid crystal panel, and there is a personal computer equipped with such a liquid crystal display device.
Further, there is a segment driver which constitutes a Y driver of a liquid crystal display device and drives a Y electrode, that is, a segment electrode of a liquid crystal panel. The liquid crystal panel is, for example, 1920
It has a relatively large number of segment electrodes. Further, the segment driver has a drive output terminal of 160 channels, for example, and by connecting 12 of them in series, a Y driver corresponding to the liquid crystal panel can be constructed.

[0003]

The segment driver is provided with, for example, 160-bit data latches provided corresponding to the drive output terminals, and the display data is input to these data latches serially in units of, for example, 8 bits. Done. Therefore, the segment driver includes, for example, a 20-bit shift register that shifts / transmits the enable signal in accordance with a predetermined clock signal, and the display data is fetched into the data latch by eight pieces according to the enable signal shift-transmitted in the shift register. It is controlled in units. Needless to say, the enable signal is sequentially transmitted to, for example, twelve segment drivers forming the Y driver, whereby 1920
A shift register of 240 bits in total that can correspond to the segment is configured.

However, while the speed of a personal computer including a liquid crystal display device is increasing and the frequency of its clock signal is increasing, the following problems occur in the above conventional liquid crystal display device. It became clear. That is, the Y driver of the liquid crystal display device includes, for example, 12 segment drivers, and the 240-bit shift register in which the shift registers of these segment drivers are connected in series as described above. In addition, each segment driver transmits and receives a shift signal, that is, an enable signal according to a clock signal having the same frequency as the shift clock of the shift register, and the transmitted and received enable signal is external wiring between adjacent segment drivers, that is, between packages. As a result, a relatively large transmission delay occurs. Therefore, as the frequency of the clock signal becomes higher, it becomes more difficult to take over the enable signal between the adjacent segment drivers, which restricts the speedup of the liquid crystal display device and thus the personal computer including the same.

An object of the present invention is to provide a segment driver or the like which can transmit an enable signal between packages at high speed. Another object of the present invention is
An object is to increase the speed of a liquid crystal display device or the like including a plurality of segment drivers, and to increase the speed of a personal computer or the like including the same.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0007]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, b segment drivers, which are included in a personal computer or the like and each include an a-bit first shift register for transmitting an enable signal in accordance with a first clock signal, are substantially connected in series to form an a × b-bit second. In a liquid crystal display device or the like provided with the shift register of FIG. 1, the enable signal is transmitted between adjacent segment drivers according to a second clock signal whose frequency is, for example, 1 / c of the first clock signal, and The enable signal output from the preceding segment driver to the succeeding segment driver is formed in synchronization with the a-c + 1-th bit output signal of the first shift register included in the preceding segment driver.

According to the above means, the enable signal is transmitted and received between the segment drivers, which are apt to cause a relatively large delay, that is, between the packages, slowly and surely according to the second clock signal having a frequency of 1 / c. Therefore, the frequency of the first clock signal can be correspondingly increased and the transmission speed of the enable signal can be increased. As a result, it is possible to increase the speed of the liquid crystal display device and the like, and to increase the speed of the personal computer and the like including the same.

[0009]

1 is a block diagram of an embodiment of a liquid crystal display device (digital device) to which the present invention is applied. An outline of the configuration and operation of the liquid crystal display device of this embodiment will be described first with reference to FIG. The liquid crystal display device of this embodiment is not particularly limited, but is included in a predetermined personal computer and used as its display device.

In FIG. 1, the liquid crystal display device of this embodiment has a flat panel type liquid crystal panel LCDP as its basic constituent element. The liquid crystal panel LCDP has 48
480 X electrodes that are arranged in a matrix of 0 × 1920 dots and are drawn to the left, that is, the common electrode com
And 1920 Y electrodes, that is, segment electrodes seg, drawn downward. The common electrodes of the liquid crystal panel LCDP are respectively coupled to the corresponding drive output terminals of the X driver XD, and the segment electrodes thereof are respectively coupled to the corresponding drive output terminals of the Y driver YD.

The X driver XD is supplied with predetermined liquid crystal drive voltages V1, V6, V5 and V2 from the liquid crystal drive voltage generation circuit LDVG, and the liquid crystal display control circuit LC.
TL to frame signal FLM, alternating signal M, display control signal DESPB (here, for so-called inverted signals that are selectively brought to a low level when they are enabled, B is added to the end of their names. The same applies hereinafter) and the clock signal CL1. The Y driver YD is supplied with liquid crystal drive voltages V1, V3, V4 and V2 from the liquid crystal drive voltage generation circuit LDVG, and the AC signal M, the display control signal DESPB, and the clock signals CL1 and CL2 from the liquid crystal display control circuit LCTL. Also, display data D0 to D7 are supplied. Further, the liquid crystal drive voltage generation circuit LDVG receives power supply voltages VCD and VCD from a power supply circuit (not shown) of the personal computer.
CC and the ground potential GND are supplied, and the liquid crystal display control circuit LCTL is coupled to an image memory (not shown).

Here, the power supply voltage VCC is a positive power supply voltage having a relatively small absolute value such as + 5V, and is mainly used as an operating power supply for a logic circuit which constitutes each part of the liquid crystal display device. The power supply voltage VCD is a positive power supply voltage having a relatively large absolute value such as + 40V, and is a basic voltage for generating the drive power supply voltages V1 to V6 of the liquid crystal panel LCDP. On the other hand, the frame signal FLM is a shift input signal for sequentially driving the common electrodes of the liquid crystal panel LCDP with one frame as a cycle. The clock signal CL1 is used as a shift clock for the frame signal FLM, and is also used as a shift input signal for setting the shift signal in the Y decoder YD.
The clock signal CL2 is used as a shift clock of the enable signal in the Y decoder YD, and is used as a clock signal for fetching the display data D0 to D7 corresponding to each segment electrode of the liquid crystal panel LCDP. Further, the alternating signal M is an alternating signal for inverting the drive voltage of the liquid crystal panel LCDP for each frame and averaging the voltage, and the display control signal DESPB selectively stops the display of the liquid crystal panel LCDP. It is used as a control signal for

Next, the liquid crystal drive voltages V1 to V6 are generated by dividing the potential between the power supply voltage VCD and the ground potential GND, and these liquid crystal drive voltages are selectively selected according to the corresponding display data and the alternating signal M. By combining the above, the predetermined potential required for the display of the liquid crystal panel LCDP is selectively formed. The liquid crystal drive voltage V
1, V6 and V3 are potentials close to the power supply voltage VCD and have a predetermined potential difference from each other, and liquid crystal drive voltages V4, V5 and V2 are potentials close to the ground potential GND and have a predetermined potential difference from each other. It

The liquid crystal drive voltage generation circuit LDVG of the liquid crystal display device is provided with a power supply voltage VC supplied from a power supply circuit.
Based on D and VCC and the ground potential GND, predetermined liquid crystal drive voltages V1 to V6 are formed, and X drivers XD and Y are formed.
Supply to the driver YD. In addition, the liquid crystal display control circuit LCTL uses the frame signal F based on a clock signal and an image synchronization signal supplied from an image memory (not shown).
LM, alternating signal M, display control signal DESPB, display data D0 to D7 and clock signals CL1 and CL2
Are formed and supplied to the X driver XD and the Y driver YD. Further, the X driver XD selectively selects the potential of the common electrode drive signal at its drive output terminal according to the frame signal FLM, the alternating signal M, the display control signal DESPB and the clock signal CL1 supplied from the liquid crystal display control circuit LCTL. Drive voltage V1, V6, V
5 or V2, the Y driver YD selectively selects the potential of the segment electrode drive signal at its drive output terminal according to the alternating signal M, the display control signal DESPB, the display data D0 to D7 and the clock signals CL1 and CL2. Let V1, V3, V4 or V2.

FIG. 2 is a block diagram of an embodiment of the Y driver YD included in the liquid crystal display device of FIG. An outline of the configuration and operation of the Y driver YD included in the liquid crystal display device of FIG. 1 will be described with reference to FIG.

In FIG. 2, the Y driver YD includes b segment drivers SDV1 to SDV12 (semiconductor devices) each having 160 drive output terminals. The liquid crystal drive voltages V1, V3, V4 and V2 are commonly supplied to these segment drivers, and the alternating signal M and the display control signal DESP are supplied.
B, display data D0 to D7 and clock signal CL1
And CL2 are commonly supplied. Further, these segment drivers are sequentially coupled via the enable signal output terminal EIO2B and the enable signal input terminal EIO1B, and are substantially coupled in series. The enable signal input terminal EIO1B of the segment driver SDV1 is
The enable signal output terminal EIO2B of the segment driver SDV12, which is constantly coupled to the ground potential GND, is
It is opened.

Segment drivers SDV1 to SDV12
Is, as will be described later, a shift register SR of a bit, that is, 20 bits, and a total of a × d, that is, 1 provided by d bits, that is, 8 bits corresponding to each drive output terminal
Data latches LA and LB each including 60 unit circuits, a level shifter LS, and a liquid crystal drive circuit LD are provided. Among these, a shift signal of logic "1", that is, an enable signal, is set in the first bit of the shift register SR of the segment driver SDV1 in synchronization with the substantial clock signal CL1, and the internal clock signal CL2I, that is, the substantial clock. In accordance with the signal CL2, the shift registers SR of the segment drivers SDV1 to SDV12, that is, a total of a × b, that is, a 240-bit shift register (second shift register) composed of these shift registers SR are sequentially shifted and transmitted. Then, along with the movement of the enable signal, the d-bit, that is, 8-bit display data D0 to D7 is transferred to the segment drivers SDV1 to
Total a × b × d consisting of SDV12 data latches LA
That is, the data latches of a total of 1920 bits are sequentially taken in and then transmitted in parallel to the corresponding data latches LB according to the substantial clock signal CL1. These display data have their direct current level changed by a predetermined level by the corresponding unit circuit of the level shifter LS, and then the alternating signal M by the corresponding unit circuit of the liquid crystal drive circuit LD.
And drive output signals according to the liquid crystal drive voltages V1, V3, V4 and V2, and segment drive signals Y1 to Y19
20 is supplied to the corresponding segment electrode of the liquid crystal panel LCDP.

FIG. 3 is a block diagram showing an embodiment of the segment driver SDV1 included in the Y driver YD shown in FIG. Based on the figure, the segment drivers SDV1 to SDV1 included in the Y driver YD of FIG.
An outline of the configuration and operation of No. 2 will be described. The circuit elements forming each block in FIG. 3 are formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. In the following description regarding the segment driver, the segment drivers SDV1 to SDV12 will be described by taking the segment driver SDV1 as an example.

In FIG. 3, the segment driver SDV
Reference numeral 1 includes a segment driver control unit SDVC for controlling the operation of each unit and a 20-bit shift register SR (first shift register). An internal clock signal CL2I (first clock signal) is supplied as a shift clock from the segment driver control unit SDVC to the flip-flops of each bit of the shift register SR. Further, the shift input signal ECLE is supplied from the segment driver control section SDVC to the flip-flop which is the first bit of the shift register SR, and the output signal SR of the flip-flop which is the 17th bit thereof is supplied.
17 is supplied to the segment driver control unit SDVC. The flip-flops forming each bit of the shift register SR are master-slave flip-flops including the flip-flops shown below.
Further, the internal clock signal CL2I is, as described later,
The shift input signal ECLE is formed based on the clock signal CL2, and the shift input signal ECLE is formed based on the clock signal CL1 and the enable input signal EIO1B.

The segment driver control unit SDVC includes
Further, clock signals CL1 and CL2 are supplied. Further, the segment driver control unit SDVC is coupled to the enable signal input terminal EIO1B on the left side thereof,
The right side thereof is coupled to the enable signal output terminal EIO2B. Segment drivers SDV1 to SDV11
The enable signal output terminal EIO2B is sequentially coupled to the enable signal input terminals EIO1B of the subsequent segment drivers SDV2 to SDV12 as described above.
In addition, the enable signal input terminal EIO1B of the segment driver SDV1 is constantly coupled to the ground potential GND, and the enable output terminal EIO2B of the segment driver SDV12 is constantly opened.

The segment driver control section SDVC receives an enable signal input terminal E from the segment driver in the preceding stage.
Enable input signal EIO input via IO1B
Based on 1B and the clock signals CL1 and CL2 supplied from the liquid crystal display control circuit LCTL, the internal clock signal CL2I, the shift input signal ECLE and the clear control signal CLE are selectively formed at predetermined timings. The enable output signal EI is received in response to the 17th bit output signal SR17 of the shift register SR.
O2B is selectively formed at a predetermined timing and is output to the segment driver SDV2 in the subsequent stage. The specific configuration and operation of the segment driver control unit SDVC will be described in detail later.

On the other hand, a shift signal of logic "1" is set to the first bit of the shift register SR in response to the high level of the shift input signal ECLE, and this shift signal is
It is shifted / transmitted in the shift register SR in synchronization with the falling edge of the internal clock signal CL2I. As will be described later, the output signals SR1 to SR of the shift register SR
Reference numeral 20 denotes an internal clock signal CL2I and corresponding unit data latches ULA1 to ULA2 of the data latch LA.
0, and based on this, the display data D0 to D7 are sequentially fetched in 8-bit units. Further, the 17th bit output signal SR17 of the shift register SR is supplied to the segment driver control section SDVC and is used for generating an enable output signal EIO2B described later.

The segment driver SDV1 further includes
20 unit data latches ULA1 to ULA2 each
0 or ULB1 to ULB20 in a two-stage data latch LA and LB, and similarly, 20 unit level shifters ULS1 to ULS20 or level shifter L including unit liquid crystal drive circuits ULD1 to ULD20.
S and a liquid crystal drive circuit LD. In addition, the unit data latches ULA1 to ULA1 that form the data latches LA and LB.
The ULA20 and ULB1 to ULB20 each include eight unit circuits, and the unit level shifters ULS1 to ULS that form the level shifter LS and the liquid crystal drive circuit LD.
20 and unit liquid crystal drive circuits ULD1 to ULD20
Also includes eight unit circuits each. Data latch LA
The unit data latches ULA1 to ULA20 are commonly supplied with 8-bit display data D0 to D7 and output signals S of corresponding bits of the shift register SR.
R1 to SR20 are respectively supplied, and the internal clock signal CL2I is further supplied from the segment driver control unit SDVC.
Are commonly supplied. Further, the unit data latches ULB1 to ULB20 of the data latch LB include the data latch L
An 8-bit output signal is supplied from each of the corresponding unit data latches ULA1 to ULA20 of A, and
The display control signal DESPB is commonly supplied, and further, the clear control signal CLE is commonly supplied from the segment driver controller SDVC.

Here, in the unit data latches ULA1 to ULA20 of the data latch LA, when the output signals SR1 to SR20 of the corresponding bits of the shift register SR are set to high level and the internal clock signal CL2I is set to high level, The corresponding 8-bit display data D0 to D7 supplied from the liquid crystal display control circuit LCTL
Sequentially captured and held in individual unit circuits. Further, each unit data latch ULB1 to ULB20 of the data latch LB
Is a unit data latch UL corresponding to the data latch LA.
The 8-bit display data held in A1 to ULA20 is fetched in parallel according to the clear control signal CLE and held. Further, the unit level shifters ULS1 to ULS20 of the level shifter LS are held in the corresponding unit data latches ULB0 to ULB20 of the data latch LB.
After changing the direct current level of the bit display data by a predetermined level, it is transmitted to the corresponding unit liquid crystal drive circuits ULD1 to ULD20 of the liquid crystal drive circuit LD, and the unit liquid crystal drive circuits ULD1 to ULD20 of the liquid crystal drive circuit LD causes the level shifter LS. Corresponding unit level shifters ULS1 to ULS2
A predetermined drive output signal is selectively formed based on the display data supplied from 0, the alternating signal M, and the liquid crystal drive voltages V1, V3, V4, and V2, and the segment drive signals Y1 to Y160 are used as the liquid crystal panel LCDP. Of the corresponding segment electrode. The display control signal DES
When PB is at low level, segment drive signal Y
1 to Y160 are all set to the liquid crystal drive voltage V2.

FIG. 4 shows the segment driver SD of FIG.
A circuit diagram of an embodiment of the segment driver control unit SDVC included in V1 is shown. In addition, in FIG.
2 is a partial circuit diagram for explaining the transmission path of the enable signal in the Y driver YD, and FIG. 6 is a signal waveform diagram of one embodiment of the Y driver YD in FIG. Further, FIG. 7 shows a partial circuit diagram for explaining the transmission path of the enable signal in the Y driver of the liquid crystal display device developed by the inventors of the present invention prior to the present invention, and FIG. The signal waveform diagram of the Y driver of FIG. 7 is shown. Based on these drawings, a specific configuration and operation of the segment driver control unit SDVC included in the segment driver SDV1 of FIG. 3 and characteristics of the segment driver and the liquid crystal display device of the present embodiment will be described.

In FIG. 4, the segment driver control unit SDVC includes an enable signal input circuit ESIC including a flip-flop F1 and flip-flops F2 and F3.
And an enable signal output circuit ESOC including. Further, an automatic stop circuit A including flip-flops F4 to F6
A clear control circuit CLEG including an STC and a clock divider circuit CL2D including a flip-flop F7, and a flip-flop F8, and a NOR gate N
O2 and NAND gates NA4 and NA
And an internal clock generation circuit CL2G including 5.

A power supply voltage VC is applied to a data input terminal D of a flip-flop F8 which constitutes the clear control circuit CLEG.
C, that is, a high level is constantly supplied, and an inverted signal of the clock signal CL2 is supplied to the inverted reset input terminal RB via the inverters V9 to VB. The non-inverted clock input terminal T has inverters VI and VJ
The clock signal CL1 is supplied via the inverter VK, and the inverted signal is supplied to the inverted clock input terminal TB via the inverter VK. The non-inverted output signal F8Q of the flip-flop F8 (here, the non-inverted output signal of the flip-flop F8 and the like is denoted by Q after the symbol F7, and its inverted output signal is denoted by QB. The same applies hereinafter) is supplied to the data latch LB as a clear control signal CLE. In addition, the inverted output signal F8QB
Is supplied to one input terminal of the NAND gate NA1 forming the enable signal output circuit ESOC as the inversion clear control signal CLEB, and also constitutes the automatic stop circuit ASTC as the inversion delay clear control signal CEDB after passing through the inverters VL and VM. Flip-flop F6
Inversion set input terminal SB, enable signal input circuit E
It is supplied to one input terminal of the NOR gate NO1 that constitutes the SIC and the inverting set input terminal SB of the flip-flop F7 that constitutes the clock frequency dividing circuit CL2D.

Here, as shown in FIG. 6, the clock signal CL1 is temporarily set to the high level at the beginning of switching the common electrodes, that is, at the beginning of the horizontal scanning, and the clock signal CL2 is set to the low level of the clock signal CL1. At least 192 after a predetermined time has passed after being returned to
Repeated 0 times and set to high level. Clear control circuit C
The flip-flop F8 of the LEG has a clock signal CL1.
Is set to the reset state, and the first rising edge of the clock signal CL2 is received to return to the reset state. Needless to say, when the flip-flop F8 is set, its non-inverted output signal F
8Q, that is, the clear control signal CLE is at high level,
The inverted output signal F8QB, that is, the inverted clear control signal C
LEB and the inverted delay clear control signal CEDB are set to the low level like the ground potential GND. In the enable signal output circuit ESOC which will be described later, the NAND gate NA is provided while the inverted delay clear control signal CEDB is at the low level.
The output signal of 1, that is, the shift input signal ECLE is temporarily set to the high level. In addition, the segment driver SDV
In 1 to SDV12, the shift signal of logic "1" is set in the flip-flop of the first bit of the shift register SR in response to the high level of the shift input signal ECLE, and the output signal SR1 thereof is set to the high level. Then, the internal clock signal CL of all segment drivers
Since 2I is fixed at the low level, the display data is not fetched into the data latch LA.

Next, the output signal AST of the automatic stop circuit ASTC, which will be described later, is supplied to one input terminal of the NAND gate NA4 constituting the internal clock generation circuit CL2G, and the enable input signal EIO1 is supplied to the other input terminal.
An inverted signal of the B inverter V1, that is, a non-inverted enable input signal EIO1 is supplied. The output signal of the NAND gate NA4 is supplied to one input terminal of the NOR gate NO2, and the inverted output signal F1QB of the flip-flop F1 of the enable signal input circuit ESIC described later is supplied to the other input terminal. NOR gate NO2
Of the NAND gate NA5 is supplied to one input terminal of the NAND gate NA5, and the other input terminal of the NAND gate NA5 is supplied with the clock signal CL2 via the inverters V9 to VC.
Is supplied. The output signal of the NAND gate NA5 becomes the internal clock signal CL2I after passing through the inverter V3. As will be described later, the enable signal input circuit ESIC
The inverted output signal F1QB of the flip-flop F1 is set to a high level at the beginning of horizontal scanning, and then the low level of the enable output signal EIO2B of the preceding segment driver and the twentieth falling edge of the internal clock signal CL2I. In response to this, the output signal AST of the automatic stop circuit ASTC is reset to the high level at the beginning of the horizontal scanning, and then becomes the low level in response to the 21st falling edge of the internal clock signal CL2I. .

As a result, the internal clock signal CL2I
As shown in FIG. 6, the automatic stop circuit AST is set after the inverted output signal F1QB of the flip-flop F1 of the corresponding enable signal input circuit ESIC is set to the low level.
An internal clock signal CL2 formed in each segment driver is formed substantially in synchronization with the clock signal CL2 until the output signal AST of C becomes low level.
The number of I pulses is 21, which is one more than the number of bits of the shift register SR. As described above, the internal clock signal CL2I is supplied to the shift register SR and the data latch LA.
And in synchronization with this, the shift register SR shifts / transmits the shift signal and the data latch LA fetches the display data D0 to D7.

On the other hand, as described above, the inverted delay clear control signal CEDB is supplied to the inverted set input terminal SB of the flip-flop F7 constituting the clock frequency dividing circuit CL2D, and its inverted output is supplied to the data input terminal D. Signal F
7QB is supplied. Further, the non-inverted clock input terminal T of the flip-flop F7 receives a clock signal CL2 at one input terminal thereof via the inverters V9 and VA and a NAND gate at the other input terminal thereof for receiving the output signal AST of the automatic stop circuit ASTC. The inverted signal of the output signal of NA3 is supplied by the inverter V7, and the inverted signal of the inverter V8 is supplied to the inverted clock input terminal TB. Non-inverted output signal F of flip-flop F7
7Q is supplied to the inverted clock input terminal TB of the flip-flop F1 forming the enable signal input circuit ESIC, and the inverted output signal F7QB is supplied to its non-inverted clock input terminal T. As described above, the inversion delay clear control signal CEDB is temporarily set to the low level at the beginning of the horizontal scanning, and the output signal AST of the automatic stop circuit ASTC is the internal clock signal C as described later.
Upon receiving the 21st falling edge of L2I, it is set to low level.

As a result, the flip-flop F7 constituting the clock frequency dividing circuit CL2D is set to the set state by setting the inverted delay clear control signal CEDB at the inverted set input terminal SB to the low level immediately after the start of the horizontal scanning. After that, the state is alternately inverted in synchronization with the rising edge of the output signal of the NAND gate NA3, that is, the falling edge of the clock signal CL2.
Therefore, the inverted output signal F7Q of the flip-flop F7
As shown in FIG. 6, B is first set to a low level immediately after the start of horizontal scanning, and then 2 of the clock signal CL2.
A second clock signal is obtained by inverting the clock signal CL2 at a cycle twice as long and dividing the frequency of the clock signal CL2 by a factor of c, that is, a half. The output signal of the inverter V7 supplied to the non-inverted and inverted clock input terminals of the flip-flop F7 is fixed to the low level by setting the output signal AST of the automatic stop circuit ASTC to the low level, whereby the inverted output of the flip-flop F7. The signal F7QB also remains fixed at the high level.

Next, at the data input terminal D of the flip-flop F1 forming the enable signal input circuit ESIC, an inverted signal of the enable input signal EIO1B by the inverter V1, that is, a non-inverted enable input signal EIO1.
Are supplied to the non-inverted clock input terminal T and the inverted clock input terminal TB, and the inverted output signal F7QB and the non-inverted output signal F7Q of the flip-flop F7 of the clock frequency dividing circuit CL2D are respectively supplied. The reset input terminal R of the flip-flop F1 is supplied with the inverted signal of the non-inverted enable input signal EIO1 from the inverter V2, and the set input terminal S is supplied with the output signal of the NOR gate NO1. The output signal of the inverter V2 is supplied to one input terminal of the NOR gate NO1, and the inverted delay clear control signal CEDB is supplied to the other input terminal.
Is supplied. Inverted output signal F of flip-flop F1
1QB is supplied to one input terminal of the NOR gate NO2 of the internal clock generation circuit CL2G. The non-inversion enable input signal EIO1 is the enable signal output circuit ESO.
It is also supplied to one input terminal of the NAND gate NA1 of C and the NAND gate NA4 of the internal clock generation circuit CL2G.

As a result, the flip-flop F1 receives the rising edge of the non-inverted output signal F7Q of the flip-flop F7, that is, the inverted output, when the non-inverted enable input signal EIO1 supplied to the data input terminal D is at the high level. When the non-inversion enable input signal EIO1 is set to the low level by receiving the falling edge of the signal F7QB and the non-inversion enable input signal EIO1 is set to the low level, it is selectively set to the reset state under the same timing condition. Needless to say, the inverted output signal F1QB of the flip-flop F1 is
In the set state, it is set to the low level such as the ground potential GND, and in the reset state, it is set to the high level such as the power supply voltage VCC.

In the segment driver SDV1,
As described above, since the enable input terminal EIO1B is constantly coupled to the ground potential GND, the flip-flop F1 is constantly set to the inverted output signal F thereof.
1QB remains low level as shown in FIG. Further, in the segment driver SDV2 at the next stage, the flip-flop F1 is operated by the enable input signal EI.
O1B, that is, the high level of the enable output signal EIO2B of the segment driver SDV1 of the previous stage is received, and the reset state is obtained. The set state is set in synchronization with the first falling edge of.

As described above, the enable signal input circuit E
The inverted and non-inverted output signals of the flip-flop F7 of the clock divider circuit CL2D supplied to the non-inverted and inverted clock input terminals of the flip-flop F1 of the SIC are formed by dividing the clock signal CL2 by one half. . Further, the enable output signal EIO2B of the previous stage viewed from the segment driver SDV2, that is, the segment driver SDV1 is the segment driver S, as will be described later.
The 18th falling edge of the internal clock signal CL2I of DV1, that is, the 19th of the shift register SR
Although it is changed to the low level in synchronization with the bit output signal SR19, this change in the low level is transmitted to the segment driver SDV2 via the external wiring, and therefore, as shown by the hatched portion in FIG. 6, a relatively large transmission delay. May occur. However, in the enable signal input circuit ESIC of the segment driver SDV2, the enable output signal EIO2B, that is, the enable input signal EIO1B is used.
Is slowly discriminated by the first rising edge of the inverted output signal F7QB of the flip-flop F7 having a half frequency of the clock signal CL2, that is, a period twice that of the clock signal CL2, and the inverted output signal F1QB of the flip-flop F1 is The low level is changed at the first falling edge. As a result, the segment driver SDV
Even if a relatively large signal delay occurs in the low level change of the enable output signal EIO2B of 1, it is possible to accurately identify this, and thereby to speed up the clock signal CL2, that is, the cycle time of the liquid crystal display device.

Next, the output signal of the NAND gate NA2 is supplied to the data input terminal D of the flip-flop F2 constituting the enable signal output circuit ESOC, and the shift input signal ECLE is supplied to the reset input terminal R. . Further, the output signal of the inverter V3, that is, the internal clock signal CL2 is connected to the non-inverted clock input terminal T.
I is supplied, and the inverted signal by the inverter V4 is supplied to the inverted clock input terminal TB. The 17th bit output signal SR17 of the shift register SR is supplied to one input terminal of the NAND gate NA2, and the inverted output signal F2QB of the flip-flop F2 is supplied to the other input terminal.

On the other hand, the non-inverted output signal F2Q of the preceding flip-flop F2 is supplied to the data input terminal D of the flip-flop F3 of the enable signal output circuit ESOC, and the output signal of the inverter VM is supplied to the inverted reset input terminal RB. That is, the inverted delay clear control signal CEDB is supplied. Further, the non-inverted clock input terminal T is supplied with an inverted signal of the output signal of the NAND gate NA5 by the inverter V5, that is, a substantial internal clock signal CL2I, and the inverted clock input terminal TB thereof is supplied with the inverted signal by the inverter V6. Supplied. As a result, the flip-flops F2 and F3 function as a shift register of substantially 2 bits. Non-inverted output signal F3Q of flip-flop F3, that is, non-inverted enable output signal EIO2
Is supplied to the data input terminal D of the flip-flop F4 of the automatic stop circuit ASTC via the inverter VH and, after passing through the predetermined output buffer OB, is supplied to the segment driver of the next stage as the enable output signal EIO2B.

As described above, the shift input signal ECLE
Is temporarily set to a high level at the beginning of horizontal scanning, and the inverted delay clear control signal CEDB, which is a substantially inverted signal thereof, is temporarily set to a low level under substantially the same timing condition. Further, as apparent from the above description, the output signal SR of the 17th bit of the shift register SR
17 is temporarily set to a high level from the 16th falling edge of the internal clock signal CL2I to the 17th falling edge. Therefore, after first receiving the high level of the shift input signal ECLE and the low level of the inverted delay clear control signal CEDB, the flip-flops F2 and F3 of the enable signal output circuit ESOC are reset, and then the seventeenth bit of the shift register SR. The flip-flop F2 is set in response to the high level of the output signal SR17 and the 17th falling edge of the internal clock signal CL2I, and the flip-flop F2 is received to the 18th falling edge of the internal clock signal CL2I. F3 is set. As a result, as shown in FIG. 6, the non-inverted output signal F3Q of the flip-flop F3, that is, the enable output signal EIO2B of the segment driver SDV1 which is the inverted signal thereof is set to the high level at the beginning of the horizontal scanning and then
In synchronization with the eighteenth falling edge of the internal clock signal CL2I, in other words, the shift register SR
A-c + 1-th bit of the output signal S of the 19th bit
It is formed in synchronization with R19.

Finally, an inverted signal of the non-inverted enable output signal EIO2 output from the enable signal output circuit ESOC by the inverter VH is supplied to the data input terminal D of the flip-flop F4 forming the automatic stop circuit ASTC. . The non-inverting output signal F4Q of the flip-flop F4 is supplied to the data input terminal D of the flip-flop F5, and the non-inverting output signal F5Q of the flip-flop F5 is supplied to the data input terminal D of the flip-flop F6. . The inverted delay clear control signal CEDB is commonly supplied to the inverted set input terminals SB of the flip-flops F4 to F6. Further, the non-inverted clock input terminal T of these flip-flops has a substantial internal clock signal CL2I via the inverters VD to VF.
Are commonly supplied, and an inverted signal from the inverter VG is commonly supplied to the inverted clock input terminal TB. Non-inverted output signal F6Q of flip-flop F6
Becomes the output signal AST of the automatic stop circuit ASTC as it is.

As a result, the flip-flops F4 to F6 of the automatic stop circuit ASTC have the internal clock signal CL2I.
The first bit, that is, the flip-flop F4, functions as a 3-bit shift register that performs a shift operation in accordance with the first internal clock signal CL2I after the non-inversion enable output signal EIO2 is set to the high level, that is, the nineteenth internal clock signal CL2I. It is set in synchronization with the falling edge. In addition, the second-stage flip-flop F5
Is set to the 20th falling edge of the internal clock signal CL2I, and the final stage flip-flop F6 is set to the 21st falling edge thereof. As a result, the automatic stop circuit A
As shown in FIG. 6, the output signal AST of the STC is reset to a high level at the beginning of the horizontal scanning, and then receives the 21st falling edge of the corresponding internal clock signal CL2I to attain the low level. It is said that In the internal clock generation circuit CL2G, as described above, the generation of the internal clock signal CL2I is stopped in response to the low level change of the output signal AST of the automatic stop circuit ASTC, and the frequency division circuit CL2D also stops its frequency division operation. .

By the way, in the liquid crystal display device developed by the present inventors prior to the present invention, as shown in FIG. 7, the generation of the enable output signal EIO2B by the enable signal output circuit ESOC is performed by the shift register S.
Based on the output signal SR18 of the 18th bit of R,
For example, the enable input signal EIO by the enable signal input circuit ESIC of the segment driver SDV2 in the next stage
1B is taken in by a substantial clock signal CL2 having the same frequency as the shift clock of the shift register SR.
It is performed according to. Therefore, as shown by hatching in FIG. 8, the segment drivers SDV1 and SDV2 are
Enable output signal E transmitted through external wiring between
IO2B, that is, the enable signal input circuit ESI of the segment driver SDV2 when a relatively large transmission delay occurs in the low level change of the enable input signal EIO1B.
In the flip-flop F1 of C, the level determination timing by the master latch is within the transmission delay time, so that it is difficult to normally identify a low level change, which speeds up the liquid crystal display device and thus the personal computer including the same. Results in being constrained.

However, in the Y driver YD of the liquid crystal display device of this embodiment, as shown in FIG. 5, the enable signal output circuit ESOC generates the enable output signal EIO2B, the 17th bit of the shift register SR. And the enable output signal EIO2 from the enable signal input circuit ESIC of the segment driver SDV2 at the next stage.
B, that is, the capture of the enable input signal EIO1B,
It is slowly performed according to the inverted output signal F7QB and the non-inverted output signal F7Q of the flip-flop F7 of the clock frequency dividing circuit CL2D having the frequency of the half of the clock signal CL2. Therefore, as shown by hatching in FIG. 6, even when a relatively large transmission delay occurs in the low level change of the enable input signal EIO1B transmitted through the external wiring, the enable signal input of the segment driver SDV2 is input. Flip-flop F1 of the circuit ESIC
Since the level determination timing by the master latch is outside the transmission delay time, this low level change can be normally identified and its malfunction can be prevented. As a result, the frequency of the clock signal CL2 is correspondingly increased,
Since the transmission speed of the enable signal can be increased,
It is possible to increase the speed of a liquid crystal display device and to increase the speed of a personal computer including the same.

The operational effects obtained from the above embodiments are as follows. That is, (1) a × b bits which are substantially serially connected with b segment drivers which are included in a personal computer or the like and each include an a-bit first shift register which transmits an enable signal according to a first clock signal. In the liquid crystal display device or the like including the second shift register, the enable signal is transmitted between the adjacent segment drivers according to the second clock signal whose frequency is 1 / c of the first clock signal. , The enable signal output from the adjacent segment driver in the subsequent stage to the segment driver in the subsequent stage
By forming the shift register in synchronization with the output signal of the (a-c + 1) th bit of the shift register, the transfer of the enable signal between the segment drivers, that is, the packages, in which a relatively large delay is likely to occur, has a frequency of 1 / c. Second
The effect that it can be performed slowly and reliably according to the clock signal of (2) According to the above item (1), there is an effect that the frequency of the first clock signal is correspondingly increased and the transmission speed of the enable signal can be increased. (3) According to the above items (1) and (2), it is possible to obtain an effect that the cycle time of the liquid crystal display device or the like can be shortened and the machine cycle of a personal computer or the like including the liquid crystal display device can be accelerated. To be

The invention made by the inventor of the present invention has been specifically described above based on the embodiments. However, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the liquid crystal display device may include a pair of Y decoders provided above and below the liquid crystal panel LCDP. In this case, the segment driver forming the Y decoder needs to have a function of selectively switching the shift direction. Liquid crystal panel LCDP
Can have any matrix structure, and the combination of the liquid crystal driving voltages is also arbitrary. The input unit of the display data to the Y decoder YD can be, for example, 4 bits, and the block configuration of the liquid crystal display device, the names and combinations of its internal signals, etc. can adopt various embodiments.

In FIG. 2, the Y decoder YD can include an arbitrary number of segment drivers according to the matrix configuration of the liquid crystal panel LCDP. Further, the number of bits of the second shift register configured by substantially connecting the b segment drivers in series does not necessarily have to match the number of segment electrodes of the liquid crystal panel LCDP. The block configuration of the Y decoder YD is just an example, and is not restricted by this embodiment. In FIG. 3, segment drivers SDV1 to SDV12
Can take any block configuration. In FIG. 4, the circuit configuration of the segment driver control unit SDVC can take various embodiments as long as the basic logical condition does not change. In FIG. 6, the specific time relationship between each clock signal and internal signal is not restricted by these embodiments.

In the above description, the case where the invention made by the present inventor is mainly applied to the liquid crystal display device of the personal computer which is the background field of application and the segment driver constituting the same has been described, but the invention is limited thereto. However, the present invention can be applied to, for example, a similar liquid crystal display device used in various systems or a segment driver formed by itself. INDUSTRIAL APPLICABILITY The present invention can be widely applied to at least a semiconductor device including a shift register serially coupled between packages and a digital device including a shift register configured by serially coupling a plurality of such semiconductor devices.

[0048]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, b segment drivers, which are included in a personal computer or the like and each include an a-bit first shift register for transmitting an enable signal in accordance with a first clock signal, are substantially connected in series to form an a × b-bit second. In a liquid crystal display device or the like provided with the shift register of FIG. 1, the enable signal is transmitted between adjacent segment drivers according to a second clock signal whose frequency is, for example, 1 / c of the first clock signal, and By forming the enable signal output from the preceding segment driver to the succeeding segment driver in synchronization with the output signal of the (a-c + 1) th bit of the first shift register included in the preceding segment driver, Between segment drivers that are prone to large delays Since the enable signal can be transferred between the packages slowly and reliably according to the second clock signal having a frequency of 1 / c, the frequency of the first clock signal is correspondingly increased to enable the enable signal. The signal transmission speed can be increased. As a result, the cycle time of a liquid crystal display device or the like can be shortened, and the machine cycle of a personal computer or the like including it can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a liquid crystal display device to which the present invention is applied.

FIG. 2 is a block diagram showing an embodiment of a Y driver included in the liquid crystal display device of FIG.

3 is a block diagram showing an embodiment of a segment driver included in the Y driver of FIG.

4 is a circuit diagram showing an embodiment of a segment driver control unit included in the segment driver of FIG.

5 is a partial circuit diagram for explaining a transmission path of an enable signal in the Y driver of FIG.

FIG. 6 is a signal waveform diagram showing an embodiment of the Y driver of FIG.

FIG. 7 is a partial circuit diagram showing a transmission path of an enable signal in a Y driver of a liquid crystal display device developed by the inventors of the present application prior to the present invention.

8 is a signal waveform diagram showing an example of the Y driver of FIG.

[Explanation of symbols]

LCDP ... Liquid crystal panel, XD ... X driver, YD ...
... Y driver, LCTL ... Liquid crystal display control circuit, LDVG ... Liquid crystal drive voltage generation circuit, V1-V6 ...
... liquid crystal drive voltage, FLM ... frame signal, M ... alternating signal, DESPB ... display control signal, D0 to D7 ...
Display data, CL1 to CL2 ... Clock signal, VC
D, VCC ... Power supply voltage, GND ... Ground potential. SDV
1-SDV12 ... Segment driver, EIO1B ...
... Enable input signal, EIO2B ... Enable output signal, Y1 to Y1920 ... Segment drive signal. SD
VC ... Segment driver control unit, SR ... Shift register, SR1-SR20 ... Unit shift register (output signal), LA, LB ... Data latch, ULA1-U
LA20, ULB1 to ULB20 ... Unit data latch, LS ... Level shifter, ULS0 to ULS20 ...
Unit level shifter, LD ... Liquid crystal drive circuit, ULD1 ~
ULD20: Unit liquid crystal drive circuit. CLEG ... Clear control circuit, CL2G ... Internal clock generation circuit, CL2
D: clock divider circuit, ESIC ... enable signal input circuit, ESOC ... enable signal output circuit, AS
TC: automatic stop circuit, F1 to F8 ... flip-flops, NA1 to NA5 ... NAND gate, N
O1-NO2 ... NOR gate, V1-VN ...
… Inverter.

Front Page Continuation (72) Inventor Makoto Kimura 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hitachi Ltd. Semiconductor Division

Claims (5)

[Claims] 1. A substantially a semiconductor device in which b semiconductor devices each including an a-bit first shift register transmitting a shift signal according to a first clock signal are substantially connected in series.
A second shift register of × b bits is provided, and transmission of the shift signal between adjacent semiconductor devices is performed by the first shift register.
A second clock signal having a frequency lower than that of the second clock signal. 2. The second clock signal has a frequency which is 1 / c of the frequency of the first clock signal, and is output from an adjacent semiconductor device in the preceding stage to a semiconductor device in the succeeding stage. The generated shift signal is substantially the a-c + th of the first shift register of the semiconductor device of the previous stage.
2. The digital device according to claim 1, wherein the digital device is formed in synchronization with a 1-bit output signal. 3. The digital device is a liquid crystal display device, and the semiconductor device is a segment driver which includes a data latch of a × d bits and constitutes a Y driver of the liquid crystal display device, wherein the shift is performed. 3. The signal according to claim 1, wherein the signal is an enable signal for sequentially fetching display data by d bits into a total of a × b × d bit data latches included in the b segment drivers. Digital device. 4. An a-bit first shift register for transmitting a shift signal according to a first clock signal, each of which is substantially serially coupled to a similar first shift register of another b-1 semiconductor device. To substantially form a second shift register of a × b bits,
And an enable signal output circuit that forms the shift signal for the adjacent semiconductor device in the subsequent stage in synchronization with the output signal of the (a-c + 1) th bit of the first shift register, and outputs from the adjacent semiconductor device in the preceding stage. And a enable signal input circuit which takes in the shift signal according to a second clock signal whose frequency is 1 / c of the frequency of the first clock signal. 5. The semiconductor device includes a data latch of a.times.d bits and Y of a liquid crystal display device.
A segment driver constituting a driver, wherein the shift signal is an enable signal for sequentially fetching display data by d bits into a data latch of a total of a × b × d bits of the segment drivers included in b semiconductor devices. The semiconductor device according to claim 4, wherein the semiconductor device is present.