JPH09200774A - Image encoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To select a predictor having high predictive accuracy and to efficiently compress image data in comparatively simple configuration. SOLUTION: Predictors 1a-1c predict the value of a concerned picture element based on the values of surrounding picture elements and calculate predictive errors Da-Dc later. Based on information showing the predictor applying the minimum predictive error to the concerned picture element and information showing the predictor used for the preceding picture element, a priority setting part 5 sets priority by counting the number of times of selection as the optimum predictor for each of predictors 1a-1c. Based on the priority, a multiplexer 6 selects any one predictor. A predictor information latch 7 latches the information showing this selected predictor and applies the information for a multiplexer 3 to select the predictor to be used for the concerned picture element. As a result, the multiplexer 3 outputs a predictive error D corresponding to the optimum predictor much more used for picture elements in the past to an encoder part 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image coding apparatus for efficiently compressing image data.

[0002]

2. Description of the Related Art Conventionally, there is a predictive coding method as one of the methods for efficiently compressing image data with a simple structure. When this predictive coding method is applied to binary image data,
The predicted value of the pixel of interest obtained from the peripheral pixel data of the pixel of interest is compared with the value of the actual pixel of interest, and the bit for which the prediction is correct is set to "0", and the bit for which prediction is incorrect is replaced with "1". By doing so, the number of consecutive occurrences of "0" bits is increased, and by performing run-length encoding on the original image data (binary), compared with direct run-length encoding, the encoding is performed. It improves the efficiency of conversion. At this time, if a plurality of predictors are provided in advance and the value of the pixel of interest is predicted while adaptively switching the predictors according to the state of the image, the coding efficiency can be further improved.

The above-described predictive coding system is not limited to binary image data, but can be used for compression of multi-valued images. For example, Japanese Unexamined Patent Publication No. 3-273762 discloses a technique that includes a plurality of predictors and uses a predictor that has a minimum absolute value of a prediction error among coded pixels as a predictor for a pixel of interest. ing. In this way, according to the method of determining the predictor for the pixel of interest currently to be encoded using the encoded pixel,
Since the predictor used at the time of encoding can be determined from the decoded pixel, it is not necessary to superimpose and leave the selection history of the predictor on the code data.

[0004]

By the way, as described above, in the predictive coding method in which a plurality of predictors are adaptively switched, it is necessary to select a predictor with the highest prediction accuracy. Will be important in improving.
In reviewing this point, in the conventional image encoding device and method, it is clearly disclosed which predictor should be selected when a plurality of predictors have the same prediction error. It has not been. A method may be considered in which priorities are set in advance for a plurality of predictors, and when the prediction errors are equal, selection is performed according to the priorities, but since the correlation between pixels changes depending on the image, the priority order of the predictors also changes. There is a need. Therefore, in the conventional image coding apparatus and method, there is a problem that a predictor with high prediction accuracy cannot be actually selected.

The present invention has been made in view of the above-mentioned circumstances, and provides an image coding apparatus capable of selecting a predictor having high prediction accuracy and efficiently compressing image data with a relatively simple structure. The purpose is to do.

[0006]

In order to solve the above-mentioned problems, according to the invention of claim 1, the value of the pixel of interest of the input image is predicted from the values of its peripheral pixels based on different parameters. A plurality of prediction units, a prediction error calculation unit that calculates a prediction error that is a difference between the value of the pixel of interest predicted by the plurality of prediction units, and the actual value of the pixel of interest; For each of the plurality of prediction units, based on the prediction selection unit that selects one prediction unit from among the plurality of prediction units based on the priority of, and the selection state of any prediction unit by the prediction selection unit. It is characterized by comprising priority setting means for setting a priority and coding means for coding the value of the pixel of interest based on the prediction value predicted by the prediction means selected by the prediction selection means. To.

[0007] According to the second aspect of the present invention, the first aspect is provided.
In the image coding apparatus described above, the priority setting means sets a high priority to a prediction means selected continuously by the prediction selection means at least twice or more.

[0008] According to the third aspect of the present invention, the first aspect of the present invention.
In the image coding apparatus according to the description, the priority setting unit sets the priority based on the number of times that the same prediction unit is not continuously selected by the prediction selection unit, and the number of times for all prediction units is a predetermined number. The number of times is reset when it reaches.

Further, according to the invention described in claim 4, according to claim 1,
In the image coding apparatus according to the description, the priority setting unit sets the priority based on the number of times that the same prediction unit is not continuously selected by the prediction selection unit, and the number of times for all prediction units is a predetermined number. When reaching, the number of times for the plurality of prediction means is reduced at an equal rate.

According to the invention of claim 5, claim 1
In the image coding apparatus described above, the priority setting unit sets the priority based on the number of times that the same prediction unit is not continuously selected by the prediction selection unit, and the number of times for any one prediction unit is predetermined. When the number of times reaches the number of times, the number of times for all of the plurality of prediction means is reduced at an equal rate.

According to the present invention, the prediction error calculating means is
A plurality of prediction means calculates a prediction error that is a difference between the value of the pixel of interest predicted based on different parameters and the actual value of the pixel of interest. The prediction selection means selects one prediction means from among the plurality of prediction means based on the predetermined dynamically changing priority set by the priority setting means. The priority setting means sets the priority for each of the plurality of prediction means based on the selection state of any prediction means by the prediction selection means. Therefore, the priority set in the predictor is updated at every encoding. The encoding means encodes the value of the pixel of interest based on the prediction value predicted by the prediction means selected by the prediction selection means. Therefore, with a relatively simple configuration, it is possible to select a predictor with high prediction accuracy, and it is possible to efficiently compress image data.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will now be described with reference to the drawings. A. Configuration of Embodiment A-1. Block Configuration of Image Processing Device FIG. 1 is a block diagram showing the configuration of an image encoding device according to an embodiment of the present invention. In the figure, the predictors 1a, 1
b and 1c have different prediction functions, and the prediction value P for the pixel signal X of the pixel of interest to be coded using the respective prediction functions with respect to the input image data.
a, Pb, Pc are calculated, prediction errors Da, Db, Dc for the pixel value of interest are calculated, and the prediction error evaluation unit 2
a, 2b, 2c and the multiplexer 3.

Here, FIGS. 2A, 2B and 2C are
FIG. 3 is a conceptual diagram showing an operation example of obtaining a predicted value by each of the predictors 1a, 1b, 1c described above. The predictor 1a is shown in FIG.
As shown in (a), the pixel value X of the immediately preceding pixel x on the same scanning line is set as the predicted value Pa of the target pixel. Next, the predictor 1b
As shown in FIG. 2B, the pixel value Y of the pixel y at the same position on the scan line immediately above is set as the predicted value Pb of the target pixel. The predictors 1a and 1b use the value of the pixel adjacent to the pixel of interest as the prediction value, and can be used for both multi-valued images and binary images. Also, the predictor 1c
As shown in FIG. 2C, the average value of the pixel value X of the pixel x and the pixel value Y of the pixel y closest to the target pixel is set as the predicted value Pc of the target pixel. In this case, the predictor 1c
Is a predictor assuming a multi-valued image, but the predicted value Pc of the target pixel is calculated by calculating the logical product (AND) of the pixel value X of the reference pixel x and the pixel value Y of the pixel y. Then, it can be used as a predictor assuming a binary image.

In the predictors 1a, 1b and 1c described above, the prediction error for binary image data is calculated by an exclusive OR operation of the pixel value of interest and the prediction value, and the prediction error for multi-valued image data is It is calculated by calculating the difference between the pixel value of interest and the predicted value. In the present embodiment, three predictors are described as an example, but the number of predictors is not limited to this, and generally N predictors may be used. Even for multi-valued image data, 2 pixels per pixel
If the information is quantized to have an information amount of about 4 bits, a multi-valued prediction error may be calculated by performing an exclusive OR operation for each corresponding bit.

Next, returning to FIG. 1, the prediction error evaluation unit 2a,
Reference numerals 2b and 2c are arithmetic units of the same configuration provided in association with the predictors 1a, 1b and 1c, respectively, and prediction errors Da, Db and D from the corresponding predictors 1a, 1b and 1c.
The magnitude of c is calculated and supplied to the minimum prediction error detection unit 4 as the prediction error evaluation values Ea, Eb, Ec. The configuration of the prediction error evaluation units 2a, 2b, 2c differs depending on the calculation method of the prediction error, that is, whether the original image data is binary image data or multi-valued image data. For example, in the case of binary image data, that is, when the prediction error is calculated by exclusive OR, the size of the prediction error is the prediction error bit included in a plurality of prediction errors collected for each predetermined bit. Since it is calculated by the total number of (bits that are “1” by exclusive OR), the prediction error evaluation unit 2
a, 2b, and 2c are composed of a counter circuit that counts the number of mispredicted bits, and the output is the prediction error evaluation value E.
a, Eb, and Ec are count values of the prediction errors Da, Db, and Dc, respectively. On the other hand, in the case of multi-valued image data,
That is, when the prediction error is calculated from the difference, the magnitude of the prediction error may be obtained by calculating the absolute value of the prediction error. Therefore, the prediction error evaluation units 2a, 2b, and 2c are the absolute values of the prediction error. The prediction error evaluation values Ea, Eb, Ec, which are output from the value calculation circuit, are absolute values of the prediction errors Da, Db, Dc, respectively.

Next, the multiplexer 3 operates in accordance with the information output from the predictor information latch 7 which will be described later.
3 sets of prediction errors Da, D which are outputs of a, 1b, 1c
One prediction error to be encoded is selected from b and Dc and is output as the final prediction error D. As described below,
The output of the predictor information latch 7 is information indicating the optimum predictor selected in the pixel coded before the current pixel of interest to be coded, so that the multiplexer 3 predicts the prediction error in the coded pixel. The prediction error by the predictor having the smallest value, that is, the predictor that is highly likely to be optimal for the current pixel of interest is selected.

Next, the minimum prediction error detection unit 4 calculates each prediction error Da, calculated by the predictors 1a, 1b, 1c.
Three prediction error evaluation values Ea, which indicate the magnitudes of Db and Dc,
Of Eb and Ec, all flag bits corresponding to the predictor that gives the smallest prediction error are asserted and output. In the present embodiment, since the predictors 1a, 1b, 1c are provided, the 3-bit flag F corresponding to each predictor is output. When there are a plurality of predictors having the same magnitude of prediction error, a plurality of flag bits are asserted. For example, when both the predictors 1a and 1c give the minimum prediction error, the flag F is set to "1,
0,1 "and both the predictors 1b and 1c give the minimum prediction error, the flag F is" 0,1,1 ".
Becomes

Next, the priority determining section 5 outputs selection information indicating the predictor selected for the current pixel of interest, which is the output of the multiplexer 6, and the output of the predictor information latch 7, that is, the current attention. Among the predictors 1a, 1b, 1c, which predictor is preferentially selected for the next pixel of interest based on the selection information indicating the predictor selected for the coded pixel before the pixel. The priority order indicating whether or not to do is determined, and the selection order information S indicating the predictor to be selected is output. When a plurality of predictors among the predictors 1a, 1b, 1c have the same priority, which predictor should be preferentially selected among them is determined according to a preset fixed priority. To do. Details of the priority order determination unit 5 will be described later.

Next, the multiplexer 6 determines which of the flag bits of the flag F output by the minimum prediction error detection unit 4 is the only bit that should be asserted, in accordance with the priority information S given from the priority determination unit 5. decide. That is, one predictor to be finally used for the next pixel of interest is determined from the predictors 1a, 1b, and 1c according to the 3-bit state output from the multiplexer 6. In other words, the output of the multiplexer 6 is the prediction error Da, D calculated by the predictors 1a, 1b, 1c.
As a result of evaluating b and Dc, the information is information indicating which is the optimum predictor. Specifically, for example, when the predictor 1a is selected by the priority order determining unit 5, the output is "1, 0, 0", and the predictor 1b is selected by the priority order determining unit 5. In this case, “0,1,0”, when the predictor 1c is selected by the priority order determination unit 5,
It becomes "0, 0, 1". In addition, the multiplexer 6 has
In addition to the priority information, initial predictor selection information indicating which predictor to use at the start of the encoding process is supplied,
At the start of encoding, a predetermined predictor is selected by the initial predictor selection information.

The predictor information latch 7 is a multiplexer 6
Is a 3-bit latch circuit for temporarily storing the output of the multiplexer 6, latches the data supplied from the multiplexer 6 (information indicating the predictor selected for the current pixel of interest), and the multiplexer 3 and the priority determination unit 5 Supply to. Therefore, the output of the predictor information latch 7 indicates which predictor was selected (optimum) for the coded pixel before the pixel of interest currently being coded. . For example, when image data is input pixel by pixel and a prediction value is calculated for the input image data, the output of the predictor information latch 7 is the pixel immediately preceding the pixel of interest currently being encoded. , The predictor with the smallest prediction error is shown. In addition, when the prediction is performed by grouping a plurality of pixels of the binary image data into a group, the predictor having the smallest prediction error with respect to the group immediately before the group including the pixel of interest currently being encoded. Is shown.

The coding unit 8 uses a coding method such as Huffman coding, run-length coding, or arithmetic coding to predict the prediction error D (Da, D) for the target pixel output from the multiplexer 3.
b or Dc) is encoded.

As described above, the difference between this embodiment and the prior art is that the priority order determining section 5 is provided, and the priority order determining section 5 adds the prediction accuracy of each predictor to the magnitude of the prediction error.
The optimum predictor for encoding the pixel of interest is selected from a plurality of predictors based on past selection information. The configuration of the priority order determination unit will be described below.

A-2. Configuration of Priority Order Determination Unit FIG. 3 is a block diagram showing an example of the configuration of the priority order determination unit of the image encoding device according to the present embodiment. In the figure,
Sar, Sbr, and Scr are predictors 1a, 1b, and
This is the output of the multiplexer 6 corresponding to 1c. Also,
Sap, Sbp, and Scp are predictors 1a, 1b, and
This is information indicating the output of the predictor information latch 7 for 1c, that is, the predictor that is optimum for the coded pixel before the current pixel to be coded.

As described above, the output of the multiplexer 6 is the predictors 1a, 1b, 1c at the current pixel of interest.
Of the prediction errors Da, Db, Dc calculated by
This is information indicating the predictor that gives the smallest prediction error. The output of the predictor information latch 7 is information indicating which predictor is selected for the current pixel of interest, and at the same time is information indicating the predictor having the smallest prediction error in the immediately preceding pixel. .

The AND gates 11a, 11b and 11c are
The outputs Sar, Sbr, Scr of the multiplexer 6, respectively.
And the outputs Sap, Sbp, Scp of the predictor information latch 7 are calculated, and the calculation results are obtained by the counters 12a, 12
b, 12c. That is, each AND gate 11
In a, 11b, and 11c, "1" is output only when both input bits are "1". The fact that both bits are “1” indicates that the currently selected predictor was the predictor that gave the smallest prediction error even in the immediately preceding pixel. That is, the outputs of the AND gates 11a, 11b, and 11c are predictors (multiplexer 6) to which the predictor selected for the current pixel of interest (output of the predictor information latch 7) gives the smallest prediction error even in the immediately preceding pixel. Output), and when both match and the output of the corresponding AND gate is “1”, it means that the optimum predictor for the current pixel of interest is selected. Become.

The counters 12a, 12b, 12c are the ANs.
It is provided corresponding to each of the D gates 11a, 11b, 11c, and counts the number of times that the output of each AND gate 11a, 11b, 11c becomes "1", and counts the count value S respectively.
It is supplied to the comparator 13 as UMa, SUMb, and SUMc. Therefore, the count values SUMa, SUMb, and SUMc in the counters 12a, 12b, and 12c indicate the number of times selected as the predictor to be used for each predictor 1a, 1b, and 1c. The number of times that the predictor that
It can be said that the prediction accuracy is high. In other words, if the predictor that gives the smallest prediction error for the current pixel of interest does not match the predictor for the coded pixels before the pixel of interest, the count value of the corresponding counter should not increase. become.

The comparator 13 is a count value SUM of the counters 12a, 12b, 12c provided corresponding to each predictor.
a, SUMb, and SUMc are compared, and the predictors 1a, 1b, and 1c are prioritized so that the count values become higher in ascending order. Count value SUMa, SUMb, S
When the UMc match, the priority order is determined according to a preset fixed priority order, and any one of the match values may be used as a predictor for the next pixel.

B. Next, the operation of this embodiment will be described. First, in the input image data, the prediction values Pa to Pc for the pixel signal X of the target pixel are calculated by the predictors 1a to 1c having different prediction functions in units of pixels (or groups), and then the target pixel value Prediction errors Da, Db, Dc are calculated. In the multiplexer 3, the predictor information latch 7
Any of the prediction errors Da to Dc is selected and encoded according to the information output from the above, that is, the information indicating the optimum predictor selected in the pixel encoded before the current encoded pixel of interest. The prediction error D is supplied to the encoding unit 8. The encoding unit 8 encodes the prediction error D output from the multiplexer 3 by a predetermined encoding method.

On the other hand, the magnitudes of the prediction errors Da to Dc are obtained by the prediction error evaluation units 2a to 2c,
The minimum prediction error detection unit 4 as the prediction error evaluation values Ea to Ec
Is supplied to. In the minimum prediction error detection unit 4, three prediction error evaluation values Ea to indicating the magnitudes of the prediction errors Da to Dc.
Of Ec, all flag bits corresponding to the predictor that gave the smallest prediction error are asserted and output. At this time,
The multiplexer 6 is supplied with priority information S indicating the predictor selected for the immediately preceding pixel from the priority determination unit 5. Therefore, in the multiplexer 6, according to the priority order information S, which flag bit of each flag bit of the flag F output by the minimum prediction error detection unit 4 is to be asserted is determined.

In the priority order determining section 5, the multiplexer 6
Based on the information indicating the predictor that gives the smallest prediction error to the current pixel of interest and the information indicating the optimum predictor used for the immediately preceding pixel output from the predictor information latch 7. Among the predictors 1a to 1c, the priority order indicating which predictor should be preferentially selected for the next pixel of interest is determined, and the selection order information S indicating the predictor to be selected is output.

Specifically, in the priority order determining section 5, first, the AND gates 11a to 11c determine the logical product of the outputs Sar, Sbr, Scr of the multiplexer 6 and the outputs Sap, Sbp, Scp of the predictor information latch 7. Is calculated. Then, the counters 12a to 12c cause each AN to operate.
The number of times that the output of the D gates 11a to 11c becomes "1" is counted, and the count values SUMa, SUMb, SUM are respectively counted.
It is supplied to the comparator 13 as c. Therefore, the count values SUMa, SUMb, in the counters 12a to 12c,
The SUMc indicates the number of times selected as the optimum predictor for each of the predictors 1a to 1c, and it can be said that the larger the count value, the higher the prediction accuracy. Further, the count value is
It is counted up only when the predictor selected for the immediately preceding pixel and the predictor giving the smallest prediction error at the current pixel of interest match. In the comparator 13, the counters 12a ...
The count values SUMa, SUMb, and SUMc of 12c are compared, and the priority order information S for each of the predictors 1a to 1c is set so that the count values become higher in ascending order. As described above, the fact that the count value is large indicates that the number of times of selection as the optimum predictor is large and the predictor with high prediction accuracy is selected. Therefore, the predictor information latch 7 has information indicating the optimum predictor selected for the immediately preceding pixel at that time, and the prediction error calculated by the optimum predictor is finally encoded from the multiplexer 3. Will be output as the prediction error D to be converted.

As described above, in the present embodiment, in the priority setting unit 5, the predictor selected for the immediately preceding pixel (the optimum predictor at that time) produces the smallest prediction error for the current pixel of interest. If it is the same as the given predictor, it is set to have a higher priority for the predictor, and the predictor to be used when encoding the next pixel is determined according to the dynamically changing priority. Therefore, with a relatively simple configuration, you can select a predictor with high prediction accuracy,
It is possible to efficiently compress image data while minimizing deterioration of image quality.

C. Modification of this embodiment C-1. First Modified Example (a) Configuration of Priority Determining Unit 5 and Multiplexer 6 According to First Modified Example Next, with reference to FIG. 4, for a modified example in which the priority determining unit 5 and the multiplexer 6 described above are combined in the same block. Explain. The parts corresponding to those in FIG. 3 are designated by the same reference numerals and the description thereof will be omitted. In the figure, AND gate 1
4a, 14b and 14c are counters 12a, 12b and 12 which constitute the priority order determination unit 5 in FIG.
The logical product of the count value of each c and the flag F (each bit is represented as Fa, Fb, Fc) having a bit corresponding to each predictor 1a, 1b, 1c which is the output of the minimum prediction error detection unit 4 is calculated. Then, the calculation result is supplied to the comparator 15. At this time, since the flag bit of the predictor determined to give the minimum value by the minimum prediction error detector 4 is asserted, the count value of the counter corresponding to the predictor is the corresponding AN.
It is directly supplied to the comparator 15 via the D gate. On the other hand, since the flag bit of the predictor determined not to give the minimum value by the minimum prediction error detection unit 4 remains negated, the count value of the counter corresponding to the predictor is
Since it does not pass through the corresponding AND gate, "0" is supplied to the comparator 15.

The comparator 15 includes the predictors 1a, 1b and 1c.
The maximum value of the count values of the counters 12a, 12b, 12c corresponding to is determined, and only the output bit corresponding to the input having the maximum value is asserted. Therefore, the only bit to be asserted from the 3-bit flag F output from the minimum prediction error detection unit 4 is determined according to the information selected more in the past, in other words, according to the priority order related to the prediction accuracy. become.

(B) Priority order determination unit 5 according to the first modification
And the operation of the multiplexer 6 According to the priority order determination unit 5 according to the second modification described above,
The AND gates 11a to 11c calculate the logical product of the signals Sar, Sbr, Scr output from the comparator 15 and the signals Sap, Sbp, Scp output by the predictor information latch 7. Therefore, the AND gates 11a ...
As described above, the output of 11c indicates that the predictor that gives the minimum prediction error to the immediately preceding pixel is the predictor that also gives the minimum prediction error to the current pixel of interest. . Therefore, the counters 12a to 12c count the number of times that the predictor having the smallest prediction error in the immediately preceding pixel was the optimum predictor for the current pixel of interest.

In the AND gates 14a to 14c, the flag bits Fa to F of the flag F from the minimum prediction error detector 4 are inputted.
According to c, the count value of each counter 12a-12c is passed. That is, the count value of the counter corresponding to the predictor determined to give the minimum value is directly supplied to the comparator 15 via the corresponding AND gate, while it is supplied to the predictor determined not to give the minimum value. Since the count value of the corresponding counter does not pass through the corresponding AND gate, “0” is supplied to the comparator 15.

The comparator 15 determines the maximum value of the count values of the counters 12a to 12c corresponding to the predictors 1a to 1c, asserts only the output bit corresponding to the input having the maximum value, and makes the final prediction. The error D is supplied to the multiplexer 3 for selecting. As a result, the prediction error calculated by the optimum predictor for the pixel of interest is supplied to the encoding unit 8 as the prediction error D to be encoded.

As described above, in the second modification, the above-mentioned priority determining section 5 and the multiplexer 6 are integrated in the same block, so that the circuit structure can be simplified.

C-2. Second Modification By the way, as shown in FIG. 3, when the number of times that the selected predictor is optimum is counted for each predictor and the prediction accuracy is estimated from the count value, the optimum predictor continues to be selected. As long as it is necessary to count the number of times, the counter 12
a, 12b, and 12c will have to be composed of large-scale counter circuits. If you use a large number of predictors,
The number of large-scale counter circuits must be increased accordingly.

When the predictor having the smallest prediction error in the immediately preceding pixel is used as the predictor of the pixel of interest as in the present embodiment, the number of times that the predictor is continuously selected even immediately after switching the predictor. That is, it is considered that the prediction accuracy of the predictor increases as the number of times the predictor is continuously selected at least twice or more. In the following, a method of deciding the priority order based on the number of times of continuous selection will be described in order not to increase the scale of the counter circuit.

(A) Priority order determination unit 5 according to the second modification
Configuration of FIG. 5 shows the configuration of the priority order determination unit 5 that determines the priority order of each predictor by detecting the number of times the same predictor is selected immediately after switching the predictors, as described above. It is a circuit diagram. In the figure, a D-type flip-flop 21
a, 21b, 21c and AND circuits 22a, 22b,
22c generates rising differential signals of Sar, Sbr, and Scr. In addition, the D-type flip-flops 23a, 2
3b and 23c delay the rising differential signal by one sample clock to generate signals Sap ', Sbp' and Sc.
Output as p '. That is, in the second modified example, instead of the outputs Sap, Sbp, Scp of the predictor information latch 7, signals Sap ′, Sb delayed by one sample clock by the D-type flip-flops 23a, 23b, 23c.
p ′ and Scp ′ are used. AND circuits 24a, 24
b. 24 c calculates the logical product of the signals Sar and Sap ′, Sbr and Sbp ′, Scr and Scp ′, and supplies the calculation results to the counters 25 a, 25 b and 25 c.

The counters 25a, 25b, 25c count the number of times that the outputs of the AND circuits 24a, 24b, 24c become "1", and shift the count value according to a control signal CS1 supplied from a control unit 27 described later. Register 26
a, 26b, 26c and the comparator 28. The shift registers 26a, 26b, 26c take in the respective count values output by the counters 25a, 25b, 25c according to a control signal CS1 supplied from a control unit 27 described later, and then shift left by a predetermined number of bits (= m). Then, the result is re-supplied to the counters 25a, 25b, 25c by the control signal CS1 supplied from the control unit 27.

The control unit 27 includes counters 25a, 25b,
It is detected that a carry occurs in any of 25c,
At that time, the count values of the counters 25a, 25b, 25c are set to the shift registers 26a, 26b, 26 of the next stage.
Incorporate into c.

(B) Priority order determination unit 5 according to the second modification
According to the priority order determination unit 5 according to the second modification described above,
After the rising differential signals of Sar, Sbr, and Scr are generated by the D-type flip-flops 21a to 21c and the AND circuits 22a to 22c, the rising differential signals are further added to the D-type flip-flops 23a to 23a. 23c to delay the signal S
ap ', Sbp', and Scp 'are generated. Next, AND
The signals Sar and Sb are output by the circuits 24a to 24c.
The logical product of r, Scr and the signals Sap ′, Sbp ′, Scp ′ is calculated. As a result, AND circuits 24a-24
The output of c indicates that the predictor that gave the smallest predicted pixel in the immediately preceding pixel is the predictor that also gave the smallest prediction error for the current pixel of interest. Therefore, the counters 25a to 25c count the number of times that the predictor having the smallest prediction error in the immediately preceding pixel was the optimum predictor for the current pixel of interest.

When a carry occurs in any of the counters 25a to 25c, the control unit 27 detects the carry and the control signal CS1 outputs the control signal CS1.
25c and shift registers 26a to 26c. The shift registers 26a to 26c use the control signal CS1.
Is supplied, the count values of the counters 25a to 25c are fetched and left-shifted by a predetermined number of bits (= m). Thereafter, the shifted count value is counted by the counters 25a to
Reloaded to 25c.

In this way, when a carry occurs in any counter, it can be reduced by 1/2 m together with the count values of the other counters 25a to 25c. Therefore, without increasing the number of bits of the counters 25a to 25c,
With a small-scale circuit configuration, the optimum predictor for the target pixel can be selected from the plurality of predictors each time.

The comparator 28 determines the maximum value of the count values of the counters 25a to 25c corresponding to the predictors 1a to 1c, asserts only the output bit corresponding to the input having the maximum value, and makes the final prediction. The error D is supplied to the multiplexer 3 for selecting. As a result, the prediction error calculated by the optimum predictor for the pixel of interest is supplied to the encoding unit 8 as the prediction error D to be encoded.

As described above, in the second modified example, immediately after switching the predictor, the number of times that the predictor is continuously selected, that is, the number of times when the predictor is continuously selected at least twice or more is set. In order to determine the priority order based on the above, when one of the counters 25a to 25c becomes a full count and a carry occurs, the counters 25a to 25c
Since the count value of 5c is shifted to the left by a predetermined number of bits (= m) and reduced by 1/2 m, the counter 25
It can be realized with a small-scale circuit configuration without increasing the number of bits of a to 25c.

In the configuration shown in FIG. 5, the counter 25
Although it is possible to configure the counters 25a to 25c with a small number of bits by dividing the count value by a to 25c into a small value, the counter minimum count value at the time when a carry occurrence is detected by an arbitrary counter is set. The values obtained by subtracting the obtained values from all the counters are counted by the counters 25 a to 2
It may be reloaded to 5c and used as the next counter initial value.

C-3. Third Modified Example In the above-described embodiment, the prediction accuracy of an arbitrary predictor is evaluated based on the number of times that the predictor is continuously selected. The predictor that gives the smallest prediction error may count the number of times that it is not the optimum predictor for the current pixel of interest, and lower the priority of the predictor with the larger count value. . In the following, a method will be described in which the number of times that is not the optimum predictor is counted, and the predictor having a larger count value lowers its priority.

(A) Priority order determination unit 5 according to the third modification
Configuration of FIG. 6 is a circuit diagram showing the configuration of the priority order determination unit 5 that counts the number of times that it is not the optimum predictor and determines the priority order based on the count value, as described above. In the figure, D-type flip-flops 31a, 31b, 31c and NAND circuits 32a, 32b, 32c generate rising differential signals of the signals Sar, Sbr, Scr from the multiplexer 6. In addition, the D-type flip-flop 33
a, 33b and 33c delay the rising differential signal by one sample clock to generate signals Sap ′, Sbp ′,
Output as Scp '. NOR circuits 34a, 34b,
34c are signals Sar and Sap ', Sbr and Sb, respectively.
A negative logical product of p ', Scr and Scp' is calculated, and the calculation result is supplied to the counters 35a, 35b, 35c.
Therefore, the outputs of the NOR circuits 34a, 34b, and 34c give the smallest prediction error to the immediately preceding pixel when both signals are "0", and give the smallest prediction error to the current pixel of interest. It becomes "1" when the predictor is not present.

The outputs of the NOR circuits 34a, 34b, 34c of the counters 35a, 35b, 35c are "1", respectively.
When the count value reaches the full count state, the count operation is stopped and a carry is supplied to the NAND circuit 36. In this way, the counters 35a, 35b, 35c are
When the count reaches the full count, the counting operation is stopped. When the count values of all the counters reach the full count, the priority of the predictor cannot be dynamically changed thereafter. Therefore, all the counters 35a, 35b, 3
NAN for calculating the negative logical product of the negative logical outputs of the carry of each counter when the count value of 5c reaches the full count
A D circuit 36 is provided. The NAND circuit 36 detects the full count by calculating the negative logical product of the carry output from each of the counters 35a, 35b, 35c, and detects the counters 35a, 35b, 3 according to the calculation result.
5c is designed to be reset. As a result, the counters 35a, 35b, and 35c are again in the NOR circuit 34.
It becomes possible to count "1" output by a, 34b, 34c.

Next, unlike the above-described embodiment and modification, the comparator 37 is set such that the predictor corresponding to the counter having a larger count value has a lower priority. That is, the larger the count value in the counter, the more the prediction error by the predictor corresponding to the counter is not the smallest (optimal).

(B) Priority order determination unit 5 according to the third modification
According to the priority order determination unit 5 according to the third modification described above,
After the rising differential signals of Sar, Sbr, and Scr are generated by the D-type flip-flops 31a to 31c and the NAND circuits 32a to 32c, the rising differential signals are further delayed by one sample clock cycle D-type flip-flops 33a to 33c. Let the signal Sa
p ', Sbp', Scp 'are generated. Next, by the NOR circuits 34a to 34c, the signals Sar, Sbr,
A negative logical product of Scr and the signals Sap ′, Sbp ′, Scp ′ is calculated. As a result, the NOR circuits 34a to 34c
The output of indicates that the minimum prediction error was not given to the current pixel of interest, even though the minimum prediction error was given to the immediately preceding pixel. Therefore, the counter 35
In a to 35c, the number of times that the predictor with the smallest prediction error in the immediately preceding pixel is not the optimum predictor for the current pixel of interest is counted.

When one of the counters 35a to 35c reaches the full count and a carry occurs, the counting operation of the corresponding counter is stopped. At this time, the NAND circuit 36 detects that all of the above carry has occurred, so that the counters 35a to 35c are reset and the counting operations of the counters 35a to 35c are restarted.

In the comparator 37, the priority order is set so that the predictor corresponding to the counter having a larger count value becomes lower. That is, in the comparator 37, the predictors 1a, 1b,
The minimum value of the count values of the counters 35a to 35c corresponding to 1c is determined, only the output bit corresponding to the input having the minimum value is asserted, and the final prediction error D is supplied to the multiplexer 3. As a result, the prediction error calculated by the optimum predictor for the pixel of interest is supplied to the encoding unit 8 as the prediction error D to be encoded.

As described above, in the third modification, the number of times that the predictor that gives the minimum prediction error to the coded pixel is not the optimum predictor for the current pixel of interest. Since the priority order of each predictor is determined by counting and decreasing the priority order of the predictor having a larger count value, the priority order determining unit 5 can be realized with a simpler circuit configuration and the prediction can be performed. A highly accurate predictor can be dynamically selected, and image data can be efficiently compressed.

In the third modified example described above, the priority order of the predictor may be determined by a preset fixed priority order after the time when all the count values reach the full count. Further, the predictor corresponding to the counter whose count value has reached the full count may not be used thereafter.

Further, in the above-mentioned third modification, even when the priority order among a plurality of predictors is set by counting the number of times of prediction failure, the method shown in FIG. It is also possible to detect that a carry has occurred in the counter, and at that time, the output of each of the counters 35a to 35c is equally reduced by the shift means and set as the next counter initial value.

It goes without saying that, in the above-described embodiment and the first to third modifications, each unit may be realized by a program by software.

[0061]

As described above, according to the present invention, it is the difference between the value of the pixel of interest predicted by a plurality of prediction means and the actual value of the pixel of interest based on different parameters. The prediction error is calculated by the prediction error calculating means, then the prediction selecting means selects one predicting means from the plurality of predicting means based on a predetermined priority, and the encoding means selects the predicting selecting means. When the value of the pixel of interest is encoded on the basis of the prediction value predicted by the prediction means selected by the priority setting means, information related to the number of times the prediction selecting means successively selects the same prediction means. Based on the above, the priority that determines the predictor to be used next is set for each predictor, so a predictor with high prediction accuracy can be selected with a relatively simple configuration, and image data can be efficiently used. Advantage that it can be compressed can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an image encoding device according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram showing an operation example of obtaining a prediction value by a predictor of the image encoding device according to the present embodiment.

FIG. 3 is a block diagram showing a configuration example of a priority order determination unit of the image encoding device according to the present embodiment.

FIG. 4 is a circuit diagram showing configurations of a priority order determination unit and a multiplexer according to a first modified example of the present embodiment.

FIG. 5 is a circuit diagram showing a configuration of a priority order determination unit according to a second modification of the present embodiment.

FIG. 6 is a circuit diagram showing a configuration of a priority order determination unit according to a third modification of the present embodiment.

[Explanation of symbols]

1a, 1b, 1c Predictor (plurality of prediction means, prediction error calculation means) 2a, 2b, 2c Prediction error evaluation section 3 Multiplexer 4 Minimum prediction error detection section (prediction selection means) 5 Priority order determination section (priority setting means) ) 6 multiplexer (prediction selection means) 7 predictor information latch 8 encoding unit (encoding means)

Claims (5)

[Claims] 1. A plurality of predicting means for predicting a value of a target pixel of an input image from values of its peripheral pixels based on respective different parameters, and a value of the target pixel predicted by the plurality of predicting means, Prediction error calculation means for calculating a prediction error that is a difference from the actual value of the pixel of interest, and prediction for selecting one prediction means from the plurality of prediction means based on a dynamically changing predetermined priority. Selection means, priority setting means for setting the priority for each of the plurality of prediction means based on a selection state of any prediction means by the prediction selection means, and prediction means selected by the prediction selection means An image coding apparatus, comprising: a coding unit that codes the value of the pixel of interest based on a predicted value predicted. 2. The priority setting means sets the priority of the prediction means selected by the prediction selection means at least twice in succession to a high priority.
The image encoding device according to claim 1. 3. The priority setting means sets the priority based on the number of times that the same prediction means is not continuously selected by the prediction selection means, and when the number of times for all prediction means reaches a predetermined number. The image coding apparatus according to claim 1, wherein the number of times is reset to. 4. The priority setting means sets the priority based on the number of times that the same prediction means is not continuously selected by the prediction selection means, and when the number of times for all the prediction means reaches a predetermined number. 2. The image coding apparatus according to claim 1, wherein the number of times for the plurality of prediction means is reduced by an equal ratio. 5. The priority setting means sets the priority based on the number of times that the same prediction means is not continuously selected by the prediction selection means, and the number of times for any one prediction means reaches a predetermined number. The image coding apparatus according to claim 1, wherein in such a case, the number of times for all of the plurality of prediction units is reduced at an equal rate.