JPH09198900A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a lowering of costs of a dynamic type RAM(random access memory) or the like by reducing the chip size thereof having a wafer burn-in testing function. SOLUTION: In a dynamic type RAM having a wafer burn-in testing function which allows accelerated testing of gate destruction or the like especially for an address selection MOSFET(metal oxide semiconductor field effect transistor) of a memory cell by applying a specified test voltage to all word lines of all memory arrays, a test voltage VWC for wafer burn-in testing to be inputted from the a pad VWC is transmitted through dummy word lines DW0-DW3 provided at peripheral ends of memory arrays MARYL and MARYR of memory mats MAT0, MAT1... while being supplied to the word line to be tested through a word line clear MOSFET N3 and word line latch MOSFET N4-N7. This enables effective utilization of the dummy word lines DW0-DW3 traditionally unused for holding information in substance as supply path of the test voltage VWC thereby curtailing the required number of dedicated supply wires necessary for the transmission of the test voltage VWC.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a dynamic RAM (random access memory) having a wafer burn-in test function, and a technique particularly effective for reducing the chip size thereof.

[0002]

2. Description of the Related Art A memory array including orthogonally arranged word lines and complementary bit lines and dynamic memory cells arranged in a lattice at intersections of the word lines and complementary bit lines is a basic constituent element. There is a dynamic RAM. In a semiconductor memory device such as a dynamic RAM, a MOSFET (metal oxide semiconductor field effect transistor) that is likely to cause gate breakdown or the like by applying a test voltage having a relatively large absolute value to a predetermined portion thereof. Then, a so-called screening test is often performed in which a MOSFET is used as a generic term for an insulated gate field effect transistor) to reduce initial defects after delivery.

[0003]

Prior to the present invention, the inventors of the present invention developed a dynamic RAM having a relatively large storage capacity, and as a part of the screening test, all the word lines of the memory array were 14V
A test voltage of about (volts) is applied all at once, and in particular, a so-called wafer burn-in test for accelerating the gate breakdown of the address selection MOSFET of the memory cell is performed, and the test voltage required for this wafer burn-in test is applied from a predetermined pad. It was decided to supply via dedicated supply wiring. However, as the dynamic RAM becomes larger and larger, it is necessary to newly provide a dedicated supply wiring for applying a test voltage to all word lines of all memory arrays, which increases the chip size of the dynamic RAM and reduces its cost. Cause to interfere.

An object of the present invention is to reduce the chip size of a dynamic RAM having a wafer burn-in test function and reduce its cost.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0006]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, by applying a predetermined test voltage to all word lines of the memory array, a dynamic RA having a wafer burn-in test function capable of performing an accelerated test especially for gate breakdown of the address selection MOSFET of the memory cell.
In M and the like, a test voltage for wafer burn-in test input from a predetermined pad is transmitted through a dummy word line or a dummy bit line provided at the peripheral end of each memory array, and the word line of each memory array is cleared. M
It is supplied to the word line to be tested through the OSFET and the word line latch MOSFET.

According to the above means, the dummy word line or the dummy bit line, which has not been used for holding information substantially in the past, is utilized as the supply path, and is exclusively used for transmitting the test voltage for the wafer burn-in test. The required number of supply wires can be reduced. As a result, the chip size of the dynamic RAM having the wafer burn-in test function can be reduced, and the cost can be reduced.

[0008]

1 is a block diagram of an embodiment of a dynamic RAM (semiconductor memory device) to which the present invention is applied, and FIG. 2 is a board layout diagram of the embodiment. It is shown. Based on these figures, first, the outline of the configuration and operation of the dynamic RAM of this embodiment and the board layout will be described. The circuit elements forming each block in FIG. 1 are not particularly limited, but may be manufactured by a known CMOS (complementary MOS) integrated circuit manufacturing technique.
It is formed on one semiconductor substrate (chip) surface such as single crystal silicon. Further, in the following description regarding the substrate layout of the dynamic RAM, the positional relationship in FIG.

In FIG. 1, the dynamic RAM of this embodiment has a memory array MARY, which occupies most of the surface of a semiconductor substrate, as its basic constituent element. The memory array MARY is not particularly limited, but a total of 1,024 word lines arranged in parallel in the vertical direction in the figure and a total of 4,096 sets arranged in parallel in the horizontal direction in the drawing. And complementary bit lines of. At the intersections of these word lines and complementary bit lines, there are substantially 1,
024 × 4,096 or 4,194,304 dynamic memory cells are arranged in a grid pattern. As a result, the dynamic RAM has a so-called 4 megabit storage capacity.

As shown by the dotted line in the figure, the memory array MARY is further arranged at the peripheral edge of the memory array MARY and is not used for normal information retention, so that process defects at the peripheral edge of the memory array having a large physical step can be prevented. Served to absorb 4
The book includes dummy word lines DW0 to DW3. In this embodiment, the dynamic RAM has a memory cell address selection MO by applying a predetermined test voltage to all the word lines of the memory array MARY at the wafer stage.
It has a wafer burn-in test function for accelerating the gate breakdown of the SFET, and the dummy word lines DW0-D
As will be described later, W3 is also used as a part of the test signal wiring for transmitting the test voltage for the wafer burn-in test, that is, the test voltage supply path. Memory array MARY
For the specific configuration and wafer burn-in test of
Details will be described later.

Substantially 1, which constitutes the memory array MARY
The 024 word lines are coupled to the X address decoder XD below the word lines, and are alternatively selected. X
The address decoder XD is supplied with 10-bit internal address signals X0 to X9 from the X address buffer XB and an internal control signal XG from the timing generation circuit TG. The X address buffer XB is supplied with the X address signals AX0 to AX9 in a time division manner through the address input terminals A0 to A9, and the timing control circuit TG supplies the internal control signal XL.

The X address buffer XB has an address input terminal A when the dynamic RAM is selected.
X-address signals AX0-A supplied via 0-A9
X9 is fetched and held according to the internal control signal XL, and internal address signals X0 to X9 are formed based on these X address signals and supplied to the X address decoder XD. Further, the X address decoder XD is selectively activated by receiving the high level of the internal control signal XG.
The internal address signals X0 to X9 supplied from the X address buffer XB are decoded to selectively set the corresponding word lines of the memory array MARY to the high level selected state. The specific configuration and operation of the X address decoder XD will be described in detail later.

Next, 4,096 sets of complementary bit lines constituting the memory array MARY are respectively coupled to the corresponding unit circuits of the sense amplifier SA on the left side thereof,
Further, substantially four sets of complementary common data lines CD0 * to CD3 * (here, for example, the non-inverted common data line CD0T and the inverted common data line CD0B are combined and the complementary common data line CD0 * is selected through the sense amplifier SA. In addition, a * is added to the name, and a so-called non-inverted signal or the like that is selectively set to a high level when it is validated is denoted by adding T to the end of the name to validate it. The so-called inverted signal or the like that is selectively set to the low level when the above is connected is represented by adding B to the end of the name, and so on. A bit line selection signal of substantially 1,024 bits is supplied from the Y address decoder YD to the sense amplifier SA, and the timing generation circuit TG is also supplied.
From the internal control signal PA. The Y address decoder YD is supplied with 10-bit internal address signals Y0 to Y9 from the Y address buffer YB and an internal control signal YG from the timing generation circuit TG. Further, the Y address buffer YB receives the Y address signal AY0 via the address input terminals A0 to A9.
.About.AY9 are supplied in a time division manner, and an internal control signal YL is supplied from the timing generation circuit TG.

The sense amplifier SA is a memory array MAR.
Substantially 4,09 provided corresponding to each complementary bit line of Y
Each of these unit circuits includes six unit circuits, each unit circuit including a pair of CMOS inverters cross-coupled and a pair of N-channel type switch MOSFs.
Including ET. Of these, each unit amplifier circuit has a drive MO that is selectively turned on in accordance with the internal control signal PA.
The power supply voltage VCC and the ground potential VSS are selectively supplied from the SFET through the common source line. Further, the gates of the switch MOSFETs are sequentially connected in common by substantially four pairs, and corresponding bit line selection signals are commonly supplied.

As a result, the unit amplifier circuits forming each unit circuit of the sense amplifier SA are selectively and simultaneously operated in response to the high level of the internal control signal PA, and the selected word of the memory array MARY is selected. The minute read signals output from the substantially 4,096 memory cells coupled to the lines via the corresponding complementary bit lines are respectively amplified to be a high level or low level binary read signal. Further, the switch MOSFETs forming each unit circuit of the sense amplifier SA are selectively turned on by substantially 4 pairs by setting the corresponding bit line selection signal to a high level, and the corresponding 4 sets of the memory array MARY are selectively turned on. The complementary bit lines and complementary common data lines CD0 * to CD3 * are selectively connected.

On the other hand, the Y address buffer YB fetches and holds the Y address signals AY0 to AY9 supplied via the address input terminals A0 to A9 in accordance with the internal control signal YL, and at the same time, based on these Y address signals. The internal address signals Y0 to Y9 are formed and supplied to the Y address decoder YD. The Y address decoder YD is selectively operated in response to the high level of the internal control signal YG, decodes the internal address signals Y0 to Y9 supplied from the Y address buffer YB, and outputs the corresponding bit line selection signal. Is alternatively set to the high level.

The complementary common data lines CD0 * to CD3 *, to which substantially four pairs of designated complementary bit lines of the memory array MARY are selectively connected, are the data input / output circuits I.
Bound to O. The data input / output circuit IO includes four unit circuits provided corresponding to the complementary common data lines CD0 * to CD3 *, and each of these unit circuits includes a write amplifier, a main amplifier, a data input buffer, and a data output. Including buffer. Of these, the input terminal of the write amplifier of each unit circuit is coupled to the output terminal of the corresponding data input buffer, and the output terminal is coupled to the corresponding complementary common data lines CD0 * to CD3 *. The input terminal of the main amplifier of each unit circuit is
It is coupled to the corresponding complementary common data lines CD0 * to CD3 *, and its output terminal is coupled to the input terminal of the corresponding data output buffer. The input terminal of the data input buffer and the output terminal of the data output buffer of each unit circuit are commonly coupled to the corresponding data input / output terminals D0 to D3. The internal control signal WC is commonly supplied from the timing generation circuit TG to the write amplifier of each unit circuit, and the internal control signal OC is commonly supplied to the data output buffer.

The data input buffer of each unit circuit of the data input / output circuit IO takes in the write data supplied via the data input / output terminals D0 to D3 when the dynamic RAM is in the write mode, and writes the corresponding write data. Transmit to amplifier. At this time, the write amplifier of each unit circuit receives the high level of the internal control signal WC and is selectively put into an operating state, and after converting the write data transmitted from each data input buffer into a predetermined complementary write signal, Writing is performed to the selected four memory cells of the memory array MARY through the complementary common data lines CD0 * to CD3 *.

On the other hand, the main amplifier of each unit circuit of the data input / output circuit IO, when the dynamic RAM is set to the read mode, complements the common data lines CD0 * to CD0 * through the selected four memory cells of the memory array MARY. CD
The read signal output via 3 * is amplified and transmitted to the corresponding data output buffer. At this time, the data output buffer of each unit circuit receives the high level of the internal control signal OC to be selectively operated, and the read signal transmitted from each main amplifier is transferred to the data input / output terminals D0 to D0.
It is sent to the outside of the dynamic RAM via D3.

The timing generation circuit TG selects the above various internal control signals based on the row address strobe signal RASB, the column address strobe signal CASB, the write enable signal WEB and the output enable signal OEB which are supplied from the outside as a start control signal. And are supplied to each part of the dynamic RAM.

The dynamic RAM further has external terminals VCC and VSS for supplying a power supply voltage VCC and a ground potential VSS respectively from an external power supply device, and a predetermined test device from an external test device through a probe card during a wafer burn-in test. Wafer burn-in test test voltage VWC for supplying the wafer burn-in test test voltage VWC. Of these, the power supply voltage VCC is set to an intermediate level positive potential such as + 5V, although not particularly limited. The wafer burn-in test test voltage VWC is set to a positive potential of a relatively large absolute value, such as + 14V, and is supplied to the memory array MARY via the test voltage supply wiring SVWC. In the normal use state after the package assembly is completed, the test voltage supply pad VWC for wafer burn-in test is bonded to the external terminal VSS, and the test voltage supply wiring SVW is bonded.
The ground potential VSS is constantly supplied to C.

By the way, the dynamic type R of this embodiment
As shown in FIG. 2, the AM memory array MARY has a direct peripheral circuit, that is, an X address decoder XD,
It is divided into eight memory mats MAT0 to MAT7 including the sense amplifier SA and the Y address decoder YD, and four memory mats MAT0 to MAT7 are symmetrically arranged with the peripheral circuit PCM arranged in the central portion of the semiconductor substrate CHIP interposed therebetween. These memory mats, as represented by the memory mats MAT0 and MAT1, have a pair of memory arrays MARYL and MARYR, which are formed by dividing the memory array MARY into two and are arranged symmetrically with the Y address decoder YD interposed therebetween.
The X address decoder XD is divided into two and the pair of X address decoders XDL and XDR provided corresponding to the memory arrays MARYL and MARYR and the sense amplifier SA are divided into two and further divided into two according to the conductivity type of the MOSFET. Not shown sense amplifier SAP
L and SANL and SAPR and SANR, respectively.

In this embodiment, the memory mat MAT
0 to MAT7 memory arrays MARYL and M
Each of the ARYRs is, as will be described later, substantially 256 word lines W0 to W arranged parallel to the vertical direction of the drawing.
255 and substantially 1, which are arranged in parallel to the horizontal direction in the figure.
024 pairs of complementary bit lines B0 * to B1023 * and substantially 256 × 1,024 or 262,14 substantially arranged in a grid pattern at intersections of these word lines and complementary bit lines.
Four dummy word lines DW0 to DW including four dynamic memory cells and arranged at the peripheral edge thereof.
3 inclusive. In addition, a sense amplifier S (not shown)
The ANL and SANR are supplied with 512-bit bit line selection signals YS0 to YS511 from the Y address decoder YD, respectively, and are supplied to the memory arrays MARYL and MAR.
1,024 complementary bit lines B0 * to B forming YR
1023 * are selectively connected to two sets of complementary common data lines, each of which corresponds to two sets. These complementary common data lines are actually coupled as they are to the data input / output circuit IO, and are alternatively enabled according to the Y address signal of the least significant bit, that is, the internal address signal Y0.

From these things, the memory array MARY
Each of L and MARYR is assumed to have a storage capacity of so-called 256 kilobits.
Each of T0 to MAT7 has a storage capacity which is twice that, that is, 512 kilobits. In addition, in this embodiment, the memory mats MA arranged symmetrically.
T0 and MAT1, MAT2 and MAT3, MAT4 and MAT5, and MAT6 and MAT7 are logically paired, and 2 from each of these memory mats.
After the pair of complementary bit lines are selectively connected to the data input / output circuit IO, the least significant bit internal address signal Y0
To be selected by. As a result, the dynamic RA
M is a so-called x4 bit memory, and has a so-called 1 megaword x 4 bit address structure.

A peripheral circuit PCU including a predetermined indirect peripheral circuit is provided above the memory mats MAT0 to MAT3.
Is arranged, and the semiconductor substrate CHIP
A predetermined number of pads are arranged along the upper side of the pad. Further, a peripheral circuit PCL including another predetermined indirect peripheral circuit is arranged below the memory mats MAT4 to MAT5, and further below the peripheral circuit PCL along the upper side of the semiconductor substrate CHIP.
A predetermined number of pads including a test voltage supply pad VWC for wafer burn-in test are arranged.

Of the 10-bit X address signal input from the X address buffer XB, that is, the internal address signals X0 to X9, the 8-bit internal address signals X1 to X8 excluding the least significant bit and the most significant bit are memory mats. M
Each X address decoder XDL and X of AT0 to MAT7
The memory array MARY is supplied to each DR in common.
The word lines W0 to W255 forming L or MARYR are selected. Further, the internal address signal X0 of the least significant bit is the two memory mats MAT0 and MAT1, MAT2 and MAT which form a pair as described above.
3, MAT4 and MAT5 and MAT6 and MAT
7, the internal address signal X9 of the most significant bit is used to selectively activate 7 of the two memory mats MAT0 and MAT2, MAT1 and MAT3.
It serves to selectively activate MAT4 and MAT6 and MAT5 and MAT7.

On the other hand, of the 10-bit Y address signal input through the Y address buffer YB, that is, the 9-bit internal address signals Y1 to Y9 excluding the least significant bit among the internal address signals Y0 to Y9, the memory mat MAT.
It is commonly supplied to the Y address decoders YD of 0 to MAT7 and is used for the selection operation of the complementary bit lines B0 * to B1023 * which form the memory array MARYL or MARYR. The least significant bit internal address signal Y0 is
As described above, it is supplied to the data input / output circuit IO and provided to selectively enable the two sets of complementary common data lines.

FIG. 3 is a partial circuit diagram of an embodiment of the memory array MARYL and the sense amplifier SAL included in the memory mats MAT0 to MAT7 of the dynamic RAM of FIG. Further, FIG. 4 shows the memory mats MAT0 to MAT7 of the dynamic RAM of FIG.
2 is a partial circuit diagram of an embodiment of the X address decoder XDL included in FIG. Further, FIG. 5 is a conceptual diagram for explaining the supply path of the test voltage for the wafer burn-in test of the dynamic RAM of FIG. Based on these drawings, the specific configuration of the memory array MARYL of the memory mats MAT0 to MAT7 of the dynamic RAM, the sense amplifiers SAPL and SANL, and the X address decoder XDL and the supply path of the test voltage for the wafer burn-in test will be described with reference to these figures. Also, the features thereof will be described.

As described above, each of the memory mats MAT0 to MAT7 has a pair of memory arrays MARYL and MARYR symmetrically arranged with the Y address decoder YD in between, and X address decoders XDL and XD.
R, sense amplifiers SAPL and SANL and SAP
R and SANR, but memory array MARYR,
X address decoder XDR and sense amplifier SAP
For R and SANR, the memory array MARYL,
X address decoder XDL and sense amplifier SAP
By analogy with the following discussion of L and SANL.
Further, the supply path of the test voltage for the wafer burn-in test will be described by taking the two memory mats MAT0 and MAT1 as an example, but the other memory mats MAT2 to MAT7.
A similar supply route is also prepared for. In the following circuit diagrams, a MOSFET having an arrow on its channel (back gate) portion is a P-channel type MOSFET and is shown separately from an N-channel MOSFET without an arrow.

In FIG. 3, memory mats MAT0 to MAT0-M
The memory array MARYL constituting the AT7 is arranged parallel to the vertical direction of the drawing and is used for substantially holding information.
It includes 56 word lines W0 to W255 and a total of four dummy word lines DW0 to DW3 arranged at the peripheral ends thereof, that is, two dummy word lines DW0 to DW3. Substantially 1, which is arranged parallel to the horizontal direction of the drawing, that is, orthogonal to the word lines W0 to W255 and the dummy word lines DW0 to DW3.
024 sets of complementary bit lines B0 * to B1023 *,
Virtually 256 × 1,024 arranged at the intersections of these word lines and complementary bit lines in a grid pattern and each consisting of one information storage capacitor and one address selection MOSFET.
That is, 262,144 dynamic memory cells are included. Of these, the address selection MOS of 256 memory cells arranged in the same column of the memory array MARYL.
The drains of the FETs have corresponding complementary bit lines B0 * to B
1,023 * non-inverted or inverted signal lines of 1023 * are alternately commonly connected with a predetermined regularity and arranged in the same row.
The gates of the address selection MOSFETs of the four memory cells are commonly coupled to the corresponding word lines W0 to W255, respectively. The memory cells arranged at the intersections of the dummy word lines DW0 to DW3 and the complementary bit lines B0 * to B1023 * are not used for substantially holding information.

Word lines W0 to W255 and dummy word lines DW0 to DW forming the memory array MARYL.
3 is coupled below it to the corresponding X address decoder XDL and is alternatively selected. Also,
Above that, through the corresponding N-channel type word line clear MOSFET N3, the test voltage supply wiring S
Bound to VWC. These word line clear MOSF
The gate of ETN3 is the same as the test voltage supply line SV.
By being commonly coupled to WC, all are in diode form. The test voltage supply wiring SVWC is coupled to the wafer burn-in test test voltage supply pad VWC. Further, the wafer burn-in test test voltage supply pad VWC is supplied with a wafer burn-in test test voltage VWC such as +14 V when the dynamic RAM is brought into the wafer burn-in test state, and package assembly is completed to complete the dynamic type. The ground potential VSS is supplied when the RAM is in a normal use state.

The dynamic RAM is set to the wafer burn-in test state and + 14V is applied to the test voltage supply wiring SVWC.
When the test voltage VWC for wafer burn-in test as described above is supplied, in the memory array MARYL, the word line clear MOSFETs in the diode form are simultaneously turned on, and the word lines W0 to W255 are cleared. The test voltage VWC for wafer burn-in test is simultaneously supplied via the MOSFETs. As a result, the wafer burn-in test test voltage VWC having a larger absolute value than the voltage normally applied is applied to the gates of the address selection MOSFETs of all the memory cells coupled to the word lines W0 to W255. Therefore, for example, the gate breakdown of the address selection MOSFET whose gate breakdown voltage is lowered is induced. As a result, so-called screening is performed, and it is possible to reduce initial defects at the initial stage of delivery of the dynamic RAM. When the dynamic RAM is in a normal use state and the ground potential VSS is supplied to the test voltage supply line SVWC, all the word line clear MOSFETs of the memory array MARYL are turned off, and the word lines W0 to W255 are not affected. Does not work.

On the other hand, the complementary bit lines B0 * to B1023 * forming the memory array MARYL have sense amplifiers S consisting of P-channel MOSFETs on the left side thereof.
A sense amplifier S, which is connected to the corresponding unit circuit of the APL and is composed of an N-channel MOSFET on the right side
It is coupled to the corresponding unit circuit of the ANL.

Here, the sense amplifier SAPL has complementary bit lines B0 * to B1023 * of the memory array MARYL.
1,024 unit circuits are provided correspondingly to each of the unit circuits, and each of these unit circuits has a pair of P-channel MOs whose drains and gates are cross-coupled to each other.
Includes SFETs P1 and P2. The commonly coupled sources of these MOSFETs are commonly coupled to a common source line CSPL, and the common source line CSPL is supplied with a power supply voltage VCC via a P-channel drive MOSFET that receives an inverted signal of the internal control signal PA. Are selectively supplied.

Similarly, the sense amplifier SANL includes complementary bit lines B0 * to B1023 * of the memory array MARYL.
1,024 unit circuits are provided corresponding to each of the unit circuits, and each of these unit circuits has a pair of N-channel MOs whose drains and gates are cross-coupled to each other.
Includes SFETs N1 and N2. The commonly coupled sources of these MOSFETs are commonly coupled to a common source line CSNL, and the common source line CSNL has an N-channel drive MOSFET that receives an internal control signal PA.
The ground potential VSS is selectively supplied via.

As a result, the sense amplifiers SAPL and SPL
MOSFETs P1 and P constituting each unit circuit of ANL
2 and N1 and N2 constitute the so-called latch type unit amplifying circuit. Then, the internal control signal PA is set to the high level and the common source lines CSPL and CSNL are supplied with the power supply voltage VCC and the ground potential VSS, respectively, so that the common source lines CSPL and CSNL are selectively activated.
The corresponding complementary bit lines B0 * to B102 from the 1,024 memory cells coupled to the selected word line of YL
Each minute read signal output via 3 * is amplified to be a high level or low level binary read signal.

Each unit circuit of the sense amplifier SANL further includes a pair of N-channel type switch MOSFETs (not shown) and three N-channel MOSFETs.
And a bit line precharge circuit consisting of
Of these, the switch MOSFETs of each unit circuit are selectively turned on by two pairs by selectively setting the bit line selection signal to a high level, and the memory array MAR.
Two complementary bit lines corresponding to YL and two complementary common data lines (not shown), that is, the data input / output circuit IO are selectively connected. Such a selecting operation is simultaneously performed by four designated memory mats MAT0 to MAT7, and eight sets of complementary bit lines are selectively connected to the data input / output circuit IO. As described above, the result is that it is further selected by the internal address signal Y0, and finally four sets of complementary bit lines and the data input / output circuit IO are connected.

On the other hand, the three N-channel MOSFETs forming the bit line precharge circuit of each unit circuit are, for example, when the dynamic RAM is in the non-selected state,
In response to a high level of an internal control signal PC (not shown), it is selectively turned on, and the non-inverted and inverted signal lines of the corresponding complementary bit lines B0 * to B1023 * of the memory array MARYL are set to a level half the power supply voltage VCC. Precharge to.

Next, the X address decoder XDL forming the memory mats MAT0 to MAT7 has the word lines W0 to W2 of the memory array MARYL as shown in FIG.
There are 256 N-channel type word line latch MOSFETs N8 to NB provided corresponding to 55 and four N-channel type word line latch MOSFETs N4 to N7 provided corresponding to the dummy word lines DW0 to DW3. Including. Of these, the word line latch MOSFET N8-
The drain of NB or the like is coupled to the corresponding word line W0 to W255 of the memory array MARYL, and the source thereof is
The test voltage supply line SVWC is commonly connected. The gates of the four gates are sequentially connected in common, and are connected to the output terminal of the corresponding inverter V1.

The X address decoder XDL further includes 256 N-channel type drive MOSFETs NC to NF provided corresponding to the word lines W0 to W255, the gates of these drive MOSFETs NC to NF, and the input terminal of the inverter V1. And N-channel type cut-off MOSFETs NG to NJ and the like provided respectively. Of these, the sources of the drive MOSFETs NC to NF are commonly connected to the word line drive signal lines WX0 to WX3 every four, and the gates of the cut MOSFETs NG to NJ are commonly connected to the power supply voltage VCC. The commonly coupled sources, that is, the input terminals of the inverter V1 are coupled to the output terminal of the inverter V2 and the gate of the P-channel pull-up MOSFET P4. The source of the pull-up MOSFET P4 is coupled to the power supply voltage VCC, the drain thereof is coupled to the input terminal of the inverter V2, that is, the internal node n1, and the pull-up MOSFET P3 of P-channel type.
Drain and N-channel decoder MOSF
Coupled to the drain of ETNK.

A precharge signal XDP is supplied to the gate of the pull-up MOSFET P3. Further, the gate of the decoder MOSFET NK is supplied with the corresponding predecode signal PX30 and the like, and the source thereof is substantially two N channel type decoders MO which are coupled in series.
It is coupled to the X decoder drive signal line XDGB via SFETs NL and NM. The gate of the decoder MOSFET NL is supplied with the corresponding predecode signal PX50 and the like, and the gate of the decoder MOSFET NM is supplied with the corresponding predecode signal PX70 and the like. As is apparent from FIG. 4, the decoder MOSFET NK is provided commonly to the four word lines. Also, the decoder MOSF
The ETNL is provided in common to the four decoder MOSFETs NK, that is, a total of 16 word lines, and is provided with a decoder MOS.
The FET NM is commonly provided to the four decoder MOSFETs NL, that is, a total of 64 word lines.

The word line drive signals WX0 to WX3 are used.
Is selectively formed by decoding the 2-bit internal address signals X1 and X2, and its effective level is a high level higher than the power supply voltage VCC by at least the threshold voltage of the address selection MOSFET of the memory cell. It is said that Further, the precharge signal XDP is the ground potential V when the dynamic RAM is in the non-selected state.
Low-level like SS, dynamic RAM
Is set to a selected state and the internal control signal XG is set to a high level, so that the internal control signal XG is set to a high level like the power supply voltage VCC. On the other hand, the predecode signals PX30 to PX3
3, PX50 to PX53 and PX70 to PX73
Are 2-bit internal address signals X3 and X, respectively.
By decoding 4, X5 and X6 and X7 and X8, a high level such as the power supply voltage VCC is alternatively set. The X decoder drive signal line XDGB is
When the dynamic RAM is in the non-selected state, it is set to a high level like the power supply voltage VCC, and the dynamic R
Memory mat MAT with AM selected and corresponding
When 0 to MAT7 are activated, they receive the high level of the internal control signal XG and are selectively set to the low level like the ground potential VSS.

When the dynamic RAM is in the non-selected state, the decoder MO in the X address decoder XDL is
The SFETs NK to NM are turned off all at once, and the precharge MOSFET P3 is turned on in response to the low level of the precharge signal XDP. As a result, the internal node n1 to which the input terminal of the inverter V2 is coupled is pulled up to the power supply voltage VCC via the pull-up MOSFET P3, and in response thereto, the output signal of the inverter V2 is set to the low level. Further, the low level of the output signal of the inverter V2 causes the output signal of the inverter V1 to have a high level such as the power supply voltage VCC, whereby the word line latch MOSFETs N8 to NB etc. are simultaneously turned on. As described above, the test voltage supply wiring SVW is used when the dynamic RAM is in a normal use state.
The ground potential VSS is supplied to C. Therefore, the ground potential VSS is supplied to the word lines W0 to W255 of the memory array MARYL via the word line latch MOSFETs N8 to NB in the ON state, and the word lines W0 to W2.
All 55 are in the non-selected state.

On the other hand, when the dynamic RAM is selected and the corresponding memory mats MAT0 to MAT7 are activated, first, the precharge signal X is given at a predetermined timing.
DP is set to a high level like the power supply voltage VCC, and the X decoder drive signal line XDGB is set to a low level like the ground potential VSS. In addition, the predecode signal PX30-
PX33, PX50 to PX53 and PX70 to PX
73 corresponds to 2-bit internal address signals X3 and X
4, X5 and X6 and X7 and X8 are alternatively set to the high level, and then the word line drive signals WX0 to WX0.
WX3 is alternatively set to the effective level according to 2-bit internal address signals X1 and X2. As a result, first, the precharge MOSFET P3 is turned off in response to the high level of the precharge signal XDP. Also,
Predecode signals PX30 to PX33, PX50 to PX
When 53 and PX70 to PX73 are both set to a high level in a corresponding combination, three decoder MOSs are provided.
The FETs NK to NM are simultaneously turned on, and in response to this, the high level of the internal node n1 is lowered to a low level such as the ground potential VSS. Therefore, the output signal of the inverter V2 becomes high level, and the inverter V1
Output signal goes low and the word line latch MO
The SFETs NC to NF are simultaneously turned off. As a result, word lines W0 to W255 of the memory array MARYL
Is selectively transmitted to the effective level of the word line drive signals WX0 to WX3 via the corresponding drive MOSFETs NC to NF, whereby the corresponding word line is selectively set to the selected state.

By the way, the word line latch M whose drain is coupled to the corresponding dummy word lines DW0 to DW3.
The sources and gates of the OSFETs N4 to N7 are commonly connected to the test voltage supply line SVWC to have a diode form. As described above, the test voltage supply wiring SV
Wafer burn-in test test voltage VWC such as + 14V is supplied to WC when the dynamic RAM is in the wafer burn-in test state, and ground potential VSS is supplied when the dynamic RAM is in the normal use state.
Is supplied. Therefore, the word line latch MOSFET
N4 to N7 have no effect on the dummy word lines DW0 to DW3 when the dynamic RAM is in the normal use state, but are turned on all at once when the dynamic RAM is in the wafer burn-in test state. Test voltage supply wiring S
Wafer burn-in test test voltage VWC supplied via VWC corresponds to dummy word lines DW0 to DW3
To communicate.

The wafer burn-in test test voltage VWC transmitted to the dummy word lines DW0 to DW3 is the word line clear MOSF provided at the other end as described above.
It is transmitted to the word lines W0 to W255 of the corresponding memory array MARYL or MARYR all at once via ETN3, and is used for the wafer burn-in test. Further, the memory arrays MARYL and MARYR of the memory mats MAT0 to MAT7 are coupled to each other via the test voltage supply line SVWC and the dummy word lines DW0 to DW3,
As a result, the test voltage VWC for the wafer burn-in test
Is configured. In other words, in the dynamic RAM of this embodiment, the dummy word lines DW0 to DW3 which are not used for substantially holding information in the normal use state are
During the wafer burn-in test, it is also used as a part of the supply path of the wafer burn-in test test voltage VWC, which requires a dedicated supply wiring for distributing the wafer burn-in test test voltage VWC to the memory mats MAT0 to MAT7. The number is greatly reduced. As a result, the chip size of the dynamic RAM can be correspondingly reduced, and its cost can be reduced.

The operational effects obtained from the above embodiments are as follows. That is, (1) by applying a predetermined test voltage to all the word lines of the memory array, in particular, the address selection MOSFE of the memory cell
In a dynamic RAM or the like having a wafer burn-in test function capable of accelerating a gate breakdown of T, a wafer burn-in test test voltage input from a predetermined pad is provided on a dummy word line provided at the peripheral edge of each memory array. And word line clear MOSFET and word line latch MOS of each memory array
By supplying the word line to be tested through the FET, the dummy word line, which has not been used for holding information substantially in the past, is utilized as the supply path, and the test voltage for the wafer burn-in test is supplied. The effect that it can be distributed to each memory mat is obtained. (2) According to the above item (1), it is possible to significantly reduce the required number of dedicated supply wirings required for transmitting the test voltage for wafer burn-in test. (3) According to the above items (1) and (2), the effect that the chip size of the dynamic RAM or the like can be reduced and the cost thereof can be reduced can be obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the number of dummy word lines provided in the memory array MARY can be set arbitrarily. Further, the dynamic RAM may have any storage capacity, and may have any bit configuration such as x1, x8 or x16 bits. In FIG. 2, the substrate layout of the dynamic RAM is not restricted by this embodiment. In FIG. 3, the memory array MARYL
, And each memory array can include any number of redundant elements. In FIG. 4, X address decoder X
The circuit configuration of the X address decoder including the DL can adopt various embodiments provided that the logical conditions are the same. Wafer burn-in test test voltage VWC
The number of pads serving as the supply path is not limited to one, and it is also possible to provide a plurality of paths for the test voltage supply wiring SVWC. When each memory array includes a dummy bit line, this can be used as a part of the supply path of the test voltage supply wiring SVWC, and various uses of the dummy word line and the dummy bit line can be considered.

In the above description, the invention made by the present inventor was mainly applied to the dynamic RAM and its wafer burn-in test, which are the fields of application in the background, but the invention is not limited thereto. For example, the present invention can be applied to various memory integrated circuit devices such as static RAMs, computer systems including the same, and various functional tests thereof. The present invention can be widely applied to a semiconductor memory device that requires a supply path for transmitting at least a predetermined test voltage, and a device or system including such a semiconductor memory device.

[0050]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a dynamic RAM or the like having a wafer burn-in test function capable of accelerating a gate breakdown of an address selection MOSFET of a memory cell by applying a predetermined test voltage to all the word lines of a memory array, a predetermined pad is used. The input test voltage for wafer burn-in test is transmitted through the dummy word line or dummy bit line provided at the peripheral end of each memory array, and also through the word line clear MOSFET and word line latch MOSFET of each memory array. By supplying dummy word lines or dummy bit lines, which have not been used for holding information substantially, as a supply path by transmitting the test voltage for wafer burn-in test. Can reduce the number of dedicated supply wiring required for . As a result, a dynamic RAM having a wafer burn-in test function
It is possible to reduce the chip size such as, and to reduce the cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a substrate layout view showing an embodiment of the dynamic RAM of FIG.

3 is a partial circuit diagram showing an embodiment of a memory array and a sense amplifier included in the dynamic RAM of FIG.

4 is a partial circuit diagram showing an embodiment of an X address decoder included in the dynamic RAM of FIG.

5 is a conceptual diagram showing an embodiment for explaining a supply path of a test voltage for a wafer burn-in test of the dynamic RAM of FIG.

[Explanation of symbols]

MARY ... Memory array, DW0 to DW3 ... Dummy word line, XD ... X address decoder, XB ... X address buffer, SA ... Sense amplifier, YD ... Y address decoder, YB ... Y address buffer, IO …
... data input / output circuit, TG ... timing generation circuit, V
WC ... Wafer burn-in test test voltage supply pad (wafer burn-in test test voltage), SVWC ...
Test voltage supply wiring for wafer burn-in test. CHIP
... Semiconductor substrate (chip), MAT0 to MAT7 ... Memory mat, MARYL, MARYR ... Memory array, XDL, XDR ... X address decoder, PCU,
PCM, PCL ... Peripheral circuit. W0 to W255 ... Word line, B0 * to B1023 * ... Complementary bit line, SAP
L, SANL ... Sense amplifier. WX0 to WX3 ... Word line drive signal, PX30 to PX33, PX50 to PX
53, PX70 to PX73 ... Predecode signal. P1
~ P4 ... P-channel MOSFET, N1-NM ...
N-channel MOSFET, V1 to V2 ... Inverter.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masahiro Sakaguchi, Inventor Masahiro Sakaguchi, 5-20-1 Josuihonmachi, Kodaira-shi, Tokyo Inside Hiritsu Cho-LS Engineering Co., Ltd. (72) Inventor, Kosaku Kodaira, Tokyo 5-20-1, Josuihoncho, Ichi-shi Hitate Cho-LS Engineering Co., Ltd.

Claims (3)

[Claims] 1. A memory array comprising word lines and bit lines arranged orthogonally and memory cells arranged in a grid at intersections of the word lines and bit lines, the memory array being provided at a peripheral edge of the memory array. A semiconductor memory device, wherein a dummy word line or a dummy bit line which is not used for substantially holding information is used as a predetermined test signal wiring among the arranged word lines or bit lines. 2. The dummy word line and the dummy bit line are used as part of a test voltage supply path for transmitting the test voltage during a predetermined wafer burn-in test. Semiconductor memory device. 3. The semiconductor memory device is a dynamic RAM, the memory array includes a word line clear MOSFET and a word line latch MOSFET provided corresponding to the word line, and the test voltage is , The word line clear MOSFET from a predetermined pad
T and the word line latch MOSFET and the dummy word line are supplied, and the ground potential of the circuit is supplied to the pad after the dynamic RAM is assembled. The semiconductor memory device according to claim 1 or 2.