JPH09198899A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory which maintains productivity without drop thereof while having higher reliability by reducing the consumption of current during the testing of stress. SOLUTION: A pad PAD1 exclusively used for a memory cell power source to supply power to a memory cell array 2 and a power source pad PAD2 exclusively used for peripheral circuits to supply power to the peripheral circuits 3 are arranged separated from each other on one semiconductor substrate 1. A boosting circuit 4 supplies a power source voltage supplied from the pad PAD1 to a memory cell array 2 in the normal mode. On the other hand, the circuit applies a boosting voltage to the memory cell array 2 in response to a high level of burn-in enable signal BIE supplied from a cell state judging circuit 5 in the burn-in mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a normal operation mode and a burn-in mode or a test mode.

[0002]

2. Description of the Related Art A memory cell of a semiconductor memory device has a complicated structure under the strictest conditions of design rules because its area determines a chip size. Therefore, it is easily affected by pattern defects due to foreign matter such as dust during the wafer process. Most of the chips with such pattern defects are removed as defective products during the test, but some of the chips with minute memory cell defects are subjected to stress tests such as burn-in that applies temperature and electrical stress for a long time. If you do not perform, it may not be defective. The frequency of defect detection is proportional to stress conditions such as voltage, temperature, and time. That is, the higher the voltage or temperature and the longer the time, the greater the defect detection rate.

FIG. 18 shows the structure of a conventional semiconductor memory device having a static memory cell 21. FIG.
As shown in FIG. 8, this semiconductor memory device has a power supply pad PAD to which a power supply for the static memory cell 21 and a power supply for the peripheral circuit of the static memory cell 21 are connected. The voltage is supplied through the power supply pad PAD.

[0004]

However, as described above, a memory in which power is supplied through the power supply pad PAD to which the power supply for the static memory cell 21 and the power supply for other circuits are connected. In a cell, in order to make the stress condition severe, when trying to raise the applied power supply voltage, it is necessary to raise the power supply voltage of all circuits in the chip, and as a result, the power supply current flowing in the chip is proportional to it. It was supposed to increase.
This means that the number of chips that can be put into burn-in at one time is limited during a stress test (hereinafter also referred to as "burn-in") during mass production of memory cells due to problems such as the maximum chip withstand capacity and production equipment. This, in turn, causes a drop in chip productivity. In other words, if the stress conditions are too strict in order to improve the reliability of the chip performance, the productivity of the chip will be reduced.

The present invention has been made in order to solve the above problems, and its purpose is to reduce the current consumption during burn-in, so that it is not necessary to reduce the productivity, and the reliability is high. It is to provide a semiconductor memory device having.

[0006]

A semiconductor memory device according to a first aspect of the present invention is a semiconductor memory device having a normal mode and a boost mode, wherein a data memory means, a peripheral circuit, and a first semiconductor substrate are provided on one semiconductor substrate. One power supply pad, a booster, and a second power supply pad are provided. Here, the peripheral circuit is for data storage means. Also,
The first power supply pad supplies a voltage to the data storage means. Further, the boosting means outputs the power supply voltage supplied from the first power supply pad to the data storage means in the normal mode, and also outputs the boosted voltage to the data storage means in response to the input boosting signal in the boosting mode. Output.
Further, the second power supply pad supplies a voltage to the peripheral circuit.

A semiconductor memory device according to a second aspect is the semiconductor memory device according to the first aspect, wherein the data storage means includes a static memory cell, and the boosting means includes a switching means and a boosted voltage generating means. And supply a voltage to the static memory cell. Here, the switching means switches from the normal mode to the boost mode in response to the input boost signal. Further, the boosted voltage generation means generates the boosted voltage based on the power supply voltage in the boosting mode. A semiconductor memory device according to a third aspect is the semiconductor memory device according to the first aspect, wherein the data storage means includes a bit line, and the boosting means includes a switching means and a boosted voltage generating means. And
The boosting means supplies a voltage to the bit line. here,
The switching means switches from the normal mode to the boost mode in response to the input boost signal. Further, the boosted voltage generating means generates the boosted voltage based on the power supply voltage in the boosting mode.

A semiconductor memory device according to a fourth aspect is the semiconductor memory device according to the first aspect, wherein the data storage means includes a word line, and the boosting means includes a switching means and a boosted voltage generating means. Including. Then, the boosting means supplies a voltage to the word line. Here, the switching means switches from the normal mode to the boost mode in response to the input boost signal. Further, the boost voltage generation means, in the boost mode,
A boost voltage is generated based on the power supply voltage. A semiconductor memory device according to a fifth aspect is a semiconductor memory device having a normal mode and a test mode, wherein one semiconductor substrate is provided with:
Static memory cells, bit lines, word lines,
It is provided with a peripheral circuit, a first power supply pad, a booster, and a second power supply pad. Here, the first power pad is
Voltages are supplied to the static memory cells, bit lines and word lines. Further, the booster outputs the power supply voltage supplied from the first power supply pad to the static memory cell, the bit line and the word line in the normal mode, and outputs the boosted signal to the input in the test mode. In response, the boosted voltage is output to the static memory cell, the bit line and the word line. Further, the second power supply pad supplies a voltage to the peripheral circuit.

According to another aspect of the semiconductor memory device of the present invention, a first bit line, a second bit line complementary thereto, a first bit line boosting means, a second bit line boosting means, and a driving means. With. Here, the first bit line boosting means supplies a boosted voltage to the first bit line. Also, the second bit line boosting means supplies a boosted voltage to the second bit line. Further, the drive means responds to the input boosting signal so that the boosted voltage is alternately supplied to the first bit line and the second bit line, and the first bit line boosting means and the second bit line. The boosting means is driven.

A semiconductor memory device according to a seventh aspect is the semiconductor memory device according to any one of the first to fifth aspects,
If a fuse is provided and a boosting signal is input, a signal of the first logic level is output to the boosting means if the fuse is blown, while a signal of the second logic level is output if the fuse is not blown. Further comprises a cell state determination means for outputting to the boosting means. The semiconductor memory device according to claim 8 is the semiconductor memory device according to claim 6, further comprising a fuse, which has a first logic level if the fuse is blown when a boosting signal is input. A cell state determining means is further provided for outputting a signal to the boosting means, while outputting a signal of the second logic level to the driving means unless the fuse is blown.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts. [First Embodiment] FIG. 1 is a block diagram showing an overall structure of a semiconductor memory device according to a first embodiment of the present invention.
As shown in FIG. 1, this semiconductor memory device includes a memory cell array 2 for storing data on a semiconductor substrate 1, a peripheral circuit 3 for the memory cell array 2, and a peripheral circuit for supplying a voltage to the peripheral circuit 3. A power supply pad PAD2, a memory cell power supply dedicated pad PAD1 provided separately from the power supply pad PAD2 for the peripheral circuit for supplying a voltage to the memory cell array 2, a write enable signal (/ WE), and an address decode signal AiAj. A burn-in signal generation circuit 6 that generates a burn-in signal BI by being input from the outside, and a memory cell array 2 on the semiconductor substrate 1 when the burn-in signal BI is input.
Is supplied to the memory cell array 2 in the normal mode and the cell state determination circuit 5 which outputs the burn-in enable signal BIE only when the memory cell array 2 is replaced with the redundant memory cell array. On the other hand, the burn-in mode includes a booster circuit 4 that supplies a boosted voltage to the memory cell array 2.

Here, specific configurations of the booster circuit 4 and the memory cell array 2 are shown in FIG. As shown in FIG. 2, the booster circuit 4 includes a switching unit including an inverter INV1, a P-channel MOS transistor PTR1, N-channel MOS transistors NTR1 and NTR3, a booster voltage including a delay circuit 41, a capacitor C1, and an N-channel MOS transistor NTR2. And a generation unit. Here, the switching section outputs the power supply voltage from the memory cell power supply dedicated pad PAD1 in the normal mode, and switches the normal mode to the burn-in mode when the burn-in enable signal BIE is input. Further, the boosted voltage generation unit generates and outputs a boosted voltage in the burn-in mode. In addition, the memory cell array 2 is a static memory cell 2
1 is arranged, and the voltage output from the booster circuit 4 is supplied to the static memory cell 21.

On the other hand, a concrete structure of the burn-in signal generating circuit 6 shown in FIG. 1 is shown in FIG. This burn-in signal generating circuit has been used more frequently than before, and as shown in FIG.
Transistor PTR2, P-channel MOS transistor PTR3 and N-channel MOS transistor NTR
A high voltage detection circuit 44 composed of 4 to 8, a resistor R1, capacitors C2, C3 and C4, inverters INV2 to 7 and N.
OR circuits NOR1 and NOR2 and NAND circuit NAND
1 and delay circuits 42 and 43.

Further, a specific configuration of the cell state discrimination circuit 5 shown in FIG. 1 is shown in FIG. As shown in FIG. 6, the cell state determination circuit includes a fuse 61 connected between the node N1 and the ground node, a capacitor C5 connected in parallel between the power supply node and the node N1, a resistor R2, and a P. The channel MOS transistor PTR4, and the input node is connected to the node N1 and the output node is the P channel MOS.
An inverter INV8 connected to the gate of the transistor PTR4, an inverter INV9 having an input node connected to the output node of the inverter INV8, a drain connected to the output node of the inverter INV9, and the gate inputting the burn-in signal BI. And an N channel MOS transistor NTR9 that is operated.

The operation of the semiconductor memory device shown in FIG. 2 according to the first embodiment of the present invention will be described below.
First, in the normal mode of operation, in this case, the booster circuit 4 is instructed to set the low level burn-in enable signal BI.
E enters. At this time, the P-channel MOS transistor PTR1 and the N-channel MOS transistor NTR3 are turned on, so that the potential of the node B becomes the power supply potential by the voltage supplied from the memory cell power supply dedicated pad PAD1. Therefore, the static memory cell 2
A power supply voltage is supplied to 1.

Next, the operation in the burn-in mode will be described.
This will be described with reference to the timing chart of FIG. A high-level burn-in enable signal BIE shown in FIG. 3A is input to the booster circuit 4. In this case, the inverter I
The low level signal shown in FIG. 3E is supplied to the node C by NV1. Therefore, at this time, P-channel MOS transistor PTR1 and N-channel MOS transistor NTR3 are turned off, and N-channel MOS transistor NTR1 is turned on. Therefore, assuming that the power supply potential is Vcc and the threshold voltage is Vth, the potential of the node A is as shown in FIG.
It is precharged to a potential of (Vcc-Vth). In addition, the input burn-in enable signal BIE is the delay signal BI shown in FIG.
It is delayed for a predetermined period as E '. Then, the delay signal BI
When E'becomes high level, the potential of the node A rises to (2Vcc-Vth) level as shown in FIG. 3B due to the coupling of the capacitor C1. Further, since the N-channel MOS transistor NTR2 is turned on when the potential of the node A becomes high level, the node B
As shown in FIG. 3 (c), the potential of the node has the same behavior as the potential of the node A shown in FIG. 3 (b) from when the high level burn-in enable signal BIE is input. However, the actual maximum potential of the node B is the capacitance C1.
And the load capacity of the node B. As described above, in the burn-in mode, the maximum voltage of (2Vcc-Vth) level is supplied to the static memory cell 21.

Therefore, according to the semiconductor memory device of the present embodiment, at the time of burn-in, only the power supply voltage supplied to the memory cell can be made higher than the voltage supplied to the peripheral circuit, so that the memory cell is highly stressed. The current consumption during burn-in can be reduced. Further, as a result, a large number of chips can be put into the burn-in without being restricted by the magnitude of the current flowing during the burn-in, so that the productivity of the semiconductor memory device having high reliability can be improved. Next, the operation until the burn-in enable signal BIE is input to the booster circuit 4 shown in FIG. 1 will be described.

First, in the burn-in mode, the burn-in signal creating circuit 6 creates and outputs the burn-in signal BI. The operation will be described with reference to the timing chart of FIG. P channel MOS transistor PT
The write enable signal (/ WE) is input to the gate of R2, but as shown in FIGS. 5A and 5C, 100 msec or more has elapsed since the write enable signal (/ WE) became low level. After that, when the decode signal AiAj of the address input to the inverter INV4 changes, a predetermined pulse is output from the inverter INV6 as shown in FIG. 5 (h). This pulse triggers the latch circuit composed of the NOR circuits NOR1 and NOR2, and as shown in FIG.
The delay signal WE 'of the write enable signal (/ WE) is output as the inverted signal BIA. In the burn-in mode, since the delay signal WE 'is at low level, the inverted signal BIA becomes high level, and the N-channel MOS transistor NTR4 is turned on. At this time, as shown in FIG.
As shown in (k), the high level burn-in signal BI is first output from the inverter INV7 when a high voltage exceeding the threshold voltage of the high voltage detection circuit 44 is supplied from the power supply.

Next, the operation of the cell state discrimination circuit 5 shown in FIG. 1 which receives the burn-in signal BI and outputs the burn-in enable signal BIE will be described with reference to FIG. A chip that is determined to be defective in the performance test is replaced with a redundant bit, and the fuse 61 of the cell state determination circuit is also blown. Therefore, in this case, coupling with the power supply potential via the capacitor C5 and resistors R2 and P
The potential of the node N1 becomes high level by the action of the channel MOS transistor PTR4. Therefore, when the high-level burn-in signal BI is input to the gate of the N-channel MOS transistor NTR9 and turned on,
The high level burn-in enable signal BIE is output from the inverter INV9. On the other hand, in the case of a chip determined not to be defective in the performance test, the fuse 61 is not cut off, and the potential of the node N1 is maintained at the ground potential. Therefore, in this case, the N-channel MOS transistor NTR
Even if the high level burn-in signal BI is input to the gate of the transistor 9 and turned on, only the low level burn-in enable signal BIE is output from the inverter INV9.

As described above, since the cell state discrimination circuit 5 outputs the burn-in enable signal BIE of high level only for the chip which is replaced as defective as a result of the performance test, the probability of unstable defect is high. The stress due to burn-in can be added only to the replaced chip, the current consumption during burn-in can be reduced, and the reliability of chip performance can be improved. Since the burn-in mode in the above description is considered to be one of the boosting modes, the same embodiment as the above can be considered also in the test mode in which the stress condition is not particularly severe by increasing the power supply voltage. In this case, the test signal generating circuit shown in FIG. 7 is used instead of the burn-in signal generating circuit 6 of FIG. 1, and the burn-in enable signal BI is used for the booster circuit 4 shown in FIG.
The test enable signal TEE is input instead of E. The test signal generating circuit has the same configuration as the burn-in signal generating circuit 6 shown in FIG. 4, but is different in that the high voltage detecting circuit 44 is not provided. The operation is also similar to that of the burn-in signal generation circuit, as shown in the timing chart of FIG.

Furthermore, an embodiment in which the cell state discrimination circuit in the above description is not used is also conceivable. That is, in this case, the burn-in signal BI is directly input to the booster circuit 4 from the burn-in signal generating circuit 6 in FIG. 1, or the booster circuit 4 is directly supplied from the test signal generating circuit.
The test signal TE is input to. In this embodiment, stress can be applied to all the chips to further improve the reliability of the semiconductor memory device. [Second Embodiment] FIG. 9 is a circuit diagram showing a specific structure of a semiconductor memory device according to a second embodiment of the present invention. The memory cell power supply dedicated pad PAD1, the peripheral circuit power supply pad PAD2 of FIG. The parts of the booster circuit 4 and the memory cell array 2 are specifically shown. As shown in FIG. 9, the semiconductor memory device according to the second embodiment has the same structure as the semiconductor memory device according to the first embodiment shown in FIG. N-channel MOS transistor NTR10 for pulling up the potential
Is connected to the drain of the N channel MOS transistor NTR11 for pulling up the potential of the bit line 92, and the peripheral circuit power supply pad PAD2 and the static memory cell 21 are connected.

The operation of the semiconductor memory device having the above structure is the same as that of the semiconductor memory device according to the first embodiment, and in the normal mode, the power supply voltage is supplied to node B and the operation is high. In the burn-in mode in which the level burn-in enable signal BIE is input to the booster circuit 4, if the power supply voltage is Vcc and the threshold voltage is Vth, the maximum voltage at the node B is (2Vcc-V).
th) level voltage is supplied. Therefore, at the time of burn-in, the N-channel MOS transistor NTR10,
Since the potentials of the bit lines 91 and 92 are pulled up to a high potential via the NTR 11, a stronger voltage than that during normal operation is applied to the access transistors 22 and 23 that form the static memory cell 21.

Therefore, according to the semiconductor memory device of the second embodiment, it is possible to apply high stress only to the access transistors forming the static memory cell, so that the semiconductor memory device having high reliability can be obtained. The current consumption during burn-in can be reduced and the productivity can be increased. In the present embodiment as well, it is considered that the test enable signal TEE is input to the booster circuit 4 shown in FIG. 9 instead of the burn-in enable signal BIE, as in the case of the semiconductor memory device according to the first embodiment. To be It is also possible to directly input the burn-in signal BI or the test signal TE from the burn-in signal generating circuit or the test signal generating circuit described in the first embodiment to the booster circuit 4 shown in FIG.

[Third Embodiment] FIG. 10 is a circuit diagram showing a specific structure of a semiconductor memory device according to a third embodiment of the present invention. The memory cell power supply dedicated pad PAD of FIG.
1, the peripheral circuit power supply pad PAD2, the booster circuit 4, and the memory cell array 2 are specifically shown. As shown in FIG. 10, the semiconductor memory device according to the third embodiment has the same structure as that of the semiconductor memory device according to the first embodiment shown in FIG. 2, but the word line for selecting the word line to be driven. The node B further includes a driver 81, and the node B includes a P channel M included in the word line driver 81.
The source of the OS transistor PTR5 is connected. Further, the power supply pad PAD2 for the peripheral circuit has an N channel MOS transistor NTR1 for pulling up the potentials of the static memory cell 21 and the bit lines 91, 92.
0, the drain of NTR11 is connected. The operation of the semiconductor memory device according to the third embodiment of the present invention is shown in the timing chart of FIG. Here, the booster circuit 4
Operates as in the case of the semiconductor memory device according to the first embodiment, as shown in FIGS. Therefore, the burn-in enable signal B is sent to the booster circuit 4.
When the IE is input, the P-channel MOS transistor PTR5 is turned on, and the N-channel MOS transistor PTR5 is turned on.
When the power supply potential is Vcc and the threshold voltage is Vth when the transistor NTR12 is turned off, FIG.
As shown in 1 (f), the potential of the word line WL is raised to the maximum (2Vcc-Vth) level. As a result, a higher voltage than that during normal operation is applied to the gates of the access transistors 22 and 23 that form the static memory cell 21.

As described above, according to the semiconductor memory device of the third embodiment, high stress can be applied only to the gate of the access transistor forming the memory cell, the current consumption at burn-in can be reduced, and the reliability can be improved. Thus, a semiconductor memory device having the property can be obtained. Note that, also in this embodiment, as in the case of the above-described first embodiment, as shown in FIG.
The burn-in enable signal B is supplied to the booster circuit 4 shown in FIG.
It is conceivable that the test enable signal TEE is input instead of the IE. Also, the burn-in enable signal B
Instead of the IE or the test enable signal TEE, the burn-in signal B is output from the burn-in signal generation circuit or the test signal generation circuit described in the first embodiment.
It is also possible to directly input I or the test signal TE to the booster circuit 4 shown in FIG.

[Fourth Embodiment] FIG. 12 is a circuit diagram showing a specific structure of a semiconductor memory device according to a fourth embodiment of the present invention. The memory cell power supply dedicated pad PAD1 shown in FIG.
The parts of the booster circuit 4 and the memory cell array 2 are specifically shown. As shown in FIG. 12, the semiconductor memory device according to the fourth embodiment has the same structure as the semiconductor memory device according to the first embodiment shown in FIG. 2, but the burn-in signal generation shown in FIG. Since the test signal generation circuit shown in FIG. 7 is provided instead of the circuit 6, the booster circuit 4 receives the high-level test enable signal TEE in the test mode. Further, as shown in FIG. 12, the booster circuit 4 includes the P-channel MOS shown in FIG.
The transistor PTR1 is not used, and the node B has an N-channel MOS transistor NTR1 for raising the potentials of the static memory cell 21 and the bit lines 91, 92.
0, drain of NTR11, and word line driver 8
The source of the P-channel MOS transistor PTR5 which constitutes 1 is connected. The operation of the semiconductor memory device according to the present embodiment is similar to that of the first, second and third embodiments, as shown in the timing chart of FIG. However, the potential of the node B in the normal mode is N channel MO as shown in FIG.
The threshold voltage of the S transistor NTR3 is smaller than the power supply potential.

According to the semiconductor memory device according to the fourth embodiment described above, stress can be applied only to each of the memory cell, the bit line and the word line at the time of testing the chip, and a defect having minute defects cannot be obtained at the mass production test. A stable chip can be easily detected as a defect. [Fifth Embodiment] FIG. 14 is a circuit diagram showing a specific structure of a semiconductor memory device according to a fifth embodiment of the present invention.
As shown in FIG. 14, in the semiconductor memory device according to the fifth embodiment, in addition to the static memory cell 21, a bit line 141, a bit line 142 complementary thereto, and a bit line boosting circuit for boosting the bit line 141 are provided. 14, a bit line boosting circuit 15 for boosting the bit line 142, and a drive circuit 16 for driving the bit line boosting circuits 14, 15 so as to alternately boost both bit lines 141, 142. Here, the bit line booster circuit 14 includes an N-channel MOS transistor NTR13 having a small size and an N-channel MOS transistor NTR1 having a larger size than that.
4 and N channel MOS transistor NTR17. Here, the large N channel MOS transistor NTR14 is connected between the power supply node and the bit line 141, and the small N channel MOS transistor NTR13 has its drain at the power supply node and its source at the N channel MOS transistor NTR17. Is connected to the bit line 141 via. The bit line boosting circuit 15 for boosting the complementary bit line 142 includes an N channel MOS transistor NTR16 having a small size, an N channel MOS transistor NTR15 having a larger size than that, and an N channel MOS transistor NTR1.
8 and has the same configuration as the bit line boosting circuit 14 described above. The drive circuit 16 also includes N-channel MOS transistors NTR19 and NTR20 and an inverter INV.
N-channel MOS transistor NTR19 including 10
Is connected to the gate of the N-channel MOS transistor NTR17,
The source of R20 is an N-channel MOS transistor NTR
Connected to 18 gates. Furthermore, the inverter INV
10 output nodes and N-channel MOS transistor NT
The gate of R20 is connected.

The operation of the semiconductor memory device according to the fifth embodiment of the present invention will now be described with reference to the timing chart of FIG. At the time of burn-in, the high-level burn-in enable signal BIE shown in FIG. 15A is input to the drains of N-channel MOS transistor NTR19 and N-channel MOS transistor NTR20. At this time, the clock signal CLK having the waveform shown in FIG. 15B is inputted from the outside of the chip to the gate of the N-channel MOS transistor NTR19 and the inverter INV10. Where the inverter INV
The clock inversion signal (/ CLK) output by 10 is shown in FIG.
As shown in FIG. 5 (c), it has a waveform obtained by inverting the clock signal CLK in FIG. 15 (b). Therefore, when the clock signal CLK is at the high level, the N-channel MOS transistor NTR19 is turned on, and the high-level burn-in enable signal BIE is input to the gate of the N-channel MOS transistor NTR17, so that the N-channel MOS transistor NTR17 is turned on. . At this time, since the clock inversion signal (/ CLK) is at low level, the N-channel MOS transistor N
TR20 is turned off. From this, the clock signal CLK
Is high level, the bit line 141 is connected to the N-channel MOS transistor NTR13 and the N-channel MOS transistor.
The boosted voltage is supplied through the transistor NTR14,
The complementary bit line 142 is supplied with the boosted voltage only through the large-sized N channel MOS transistor NTR15.

On the other hand, when the clock signal CLK becomes low level, the N-channel MOS transistor NTR1
9 is turned off, and clock inversion signal (/ CLK)
Becomes high level, the N-channel MOS transistor NTR20 is turned on. At this time, N channel MOS
Since the high level burn-in enable signal BIE is input to the gate of the transistor NTR18, the N-channel MOS transistor NTR18 is turned on. As a result, when the clock signal CLK is at the low level, the boosted voltage is supplied to the bit line 141 only through the large-sized N channel MOS transistor NTR14, and the complementary bit line 142 is supplied with the N channel MOS transistors NTR15 and NTR15. Channel MOS transistor NTR
A boosted voltage is supplied via 16.

According to the semiconductor memory device of the fifth embodiment described above, the high stress having different strengths can be alternately applied to the bit line and the complementary bit line in synchronization with the external clock signal. An unstable memory cell can be detected as a defect, and a highly reliable semiconductor memory device can be obtained. Although the semiconductor memory device according to the fifth embodiment described above has a burn-in mode, an embodiment having a test mode is also conceivable as shown in FIG. That is, the semiconductor memory device having this test mode includes the test signal generation circuit shown in FIG. 7, and the test enable signal TE output from the cell state determination circuit shown in FIG.
By inputting E to the drive circuit 16, the same operation as the semiconductor memory device having the burn-in mode is performed as shown in the timing chart of FIG.

According to the semiconductor memory device having this test mode, the stress test can be easily performed even during the normal test in which the power supply voltage is not raised to a high voltage. An embodiment in which the burn-in signal BI generated by the burn-in signal generation circuit or the test signal TE generated by the test signal generation circuit is directly input to the drive circuit 16 at the time of burn-in or test is also conceivable.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of the semiconductor memory device shown in FIG.

FIG. 3 is a timing diagram showing an operation of the circuit shown in FIG.

FIG. 4 is a circuit diagram showing a specific configuration of the burn-in signal generation circuit shown in FIG.

FIG. 5 is a timing diagram showing an operation of the burn-in signal generation circuit shown in FIG.

6 is a circuit diagram showing a specific configuration of the cell state determination circuit shown in FIG.

FIG. 7 is a circuit diagram showing a specific configuration of a test signal generation circuit.

FIG. 8 is a timing diagram showing an operation of the test signal generating circuit shown in FIG.

FIG. 9 is a circuit diagram showing a specific configuration of the semiconductor memory device according to the second embodiment of the present invention.

FIG. 10 is a circuit diagram showing a specific configuration of a semiconductor memory device according to a third embodiment of the present invention.

11 is a timing diagram showing an operation of the circuit shown in FIG.

FIG. 12 is a circuit diagram showing a specific configuration of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 13 is a timing diagram showing an operation of the circuit shown in FIG.

FIG. 14 is a circuit diagram showing a specific configuration of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 15 is a timing diagram showing an operation of the circuit shown in FIG.

FIG. 16 is a circuit diagram showing a specific configuration of a semiconductor memory device according to a fifth embodiment of the present invention having a test mode.

FIG. 17 is a timing diagram showing an operation of the circuit shown in FIG.

FIG. 18 is a diagram showing a configuration of a conventional semiconductor memory device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 semiconductor substrate, 2 memory cell array, 3 peripheral circuit, 4 booster circuit, 5 cell state determination circuit, 6 burn-in signal generation circuit, 14 and 15 bit line booster circuit, 21
Static memory cell, 22, 23 access transistor, 61 fuse, 81 word line driver, 9
1,92,141,142 Bit line, WL word line, PAD1 Memory cell power supply pad, PAD2
Power supply pad for peripheral circuits, BI burn-in signal, BIE
Burn-in enable signal, TE test signal, TE
E Test enable signal, CLK clock signal, I
NV1 to INV10 Inverters, PTR1 to PTR5
P-channel MOS transistor, NTR1 to NTR2
0 N-channel MOS transistor, C1 to C5 capacitance.

Claims (8)

[Claims] 1. A semiconductor memory device having a normal mode and a boost mode, comprising: a semiconductor substrate, a data storage means formed on the semiconductor substrate, and the storage means formed on the semiconductor substrate. A peripheral circuit, a first power supply pad that is formed on the semiconductor substrate and supplies a voltage to the data storage unit, and a first power supply pad that is formed on the semiconductor substrate and is supplied from the first power supply pad in the normal mode. Boosting means for outputting a boosted voltage to the data storing means in response to an input boosting signal in the boosting mode, the boosting means being formed on the semiconductor substrate, A semiconductor memory device comprising: a second power supply pad that supplies a voltage to a peripheral circuit. 2. The data storage means includes a static memory cell, the boosting means switching means for switching from the normal mode to the boosting mode in response to the input boosting signal, and in the boosting mode. 2. The semiconductor memory device according to claim 1, further comprising input boosted voltage generation means for generating the boosted voltage based on the power supply voltage, wherein the boosting means supplies a voltage to the static memory cell. 3. The data storage means includes a bit line, and the boosting means switches the normal mode to the boosting mode in response to the input boosting signal; and in the boosting mode, The semiconductor memory device according to claim 1, further comprising a boosted voltage generating unit that generates the boosted voltage based on the power supply voltage, wherein the boosting unit supplies a voltage to the bit line. 4. The data storage means includes a word line, and the boosting means switches the normal mode to the boosting mode in response to the input boosting signal; and, in the boosting mode, 2. The semiconductor memory device according to claim 1, further comprising a boosted voltage generating unit that generates the boosted voltage based on the power supply voltage, wherein the boosting unit supplies a voltage to the word line. 5. A semiconductor memory device having a normal mode and a test mode, comprising: a semiconductor substrate, a static memory cell formed on the semiconductor substrate, a bit line formed on the semiconductor substrate, A word line formed on a semiconductor substrate; a peripheral circuit for the static memory cell formed on the semiconductor substrate; a static memory cell formed on the semiconductor substrate; a bit line; A first power supply pad that supplies a voltage to a word line; and a power supply voltage that is formed on the semiconductor substrate and is supplied from the first power supply pad in the normal mode to the static memory cell and the bit line. , In response to a boost signal input in the test mode while outputting to the word line, the static And Moriseru, and said bit line, and a boosting means for outputting a boosted voltage to the word line, wherein formed on a semiconductor substrate, a semiconductor memory device and a second power supply pad for supplying a voltage to the peripheral circuit. 6. A first bit line, a second bit line complementary to the first bit line, a first bit line boosting means for supplying a boosted voltage to the first bit line, and Second bit line boosting means for supplying a boosted voltage to the second bit line, and the boosted voltage is alternately supplied to the first bit line and the second bit line in response to an input boosted signal. A semiconductor memory device including the first bit line boosting means and a driving means for driving the second bit line boosting means. 7. A fuse is provided, and when the boosting signal is input, if the fuse is blown, a signal of a first logic level is output to the boosting means, while the fuse is blown. 6. The semiconductor memory device according to claim 1, further comprising a cell state determination unit that outputs a signal of a second logic level to the boosting unit if it is not present. 8. A fuse is provided, and when the boosting signal is input, if the fuse is blown, a signal of a first logic level is output to the boosting means, while the fuse is blown. 7. The semiconductor memory device according to claim 6, further comprising a cell state determination unit that outputs a signal of a second logic level to the drive unit if it is not present.