JP2000113678A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To judge whether the potential of a word line is sufficiently raised or not or sufficiently lowered or not precisely even if a discharge transistor is connected to the word line. SOLUTION: A semiconductor memory device has a row decoder circuit which drives a word line, a quasi row decoder circuit 11 equivalent to the low decoder circuit, a quasi word line 12 driven by the quasi row decoder circuit and a word line voltage detection circuit 13 which detects that the voltages of a plurality of nodes on the word line are higher than a certain voltage when the word line is in a selective state and detects that the voltages of the plurality of nodes are less than the certain voltage when the word line is in a nonselective state by monitoring and latching the voltage states of the plurality of nodes and judges a period during which the word line is put into the selective state and the voltages of the plurality of nodes are elevated to values higher than the certain voltage and then the word line is put into the nonselective state and the voltages of the plurality of nodes are reduced to values less than the certain voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which a word line rises to a certain voltage or more when a word line is selected, and a word line when a word line is deselected. The present invention relates to a word line delay detection circuit that detects that a line has dropped below a certain voltage and determines whether the word line rises above a certain voltage to fall below a certain voltage.

[0002]

2. Description of the Related Art FIG. 10 is a block diagram showing a schematic configuration of a semiconductor memory. In the memory cell array MCA, a plurality of memory cells MC are arranged in a matrix. Of the plurality of memory cells MC, the memory cells MC arranged in the same row are connected to a corresponding one of the plurality of word lines WL, and the memory cells MC arranged in the same column are connected to a plurality of bit lines BL. One of them is connected. The plurality of word lines WL are selectively driven by the output of a row decoder RD, and the plurality of bit lines BL are selected by a column decoder CD.

[0003] By the way, as the capacity of the semiconductor memory increases, the number of cells connected to one word line increases, and a considerable delay occurs in the rise and fall at the root and end of the word line.

Therefore, the rise and fall of the word line are detected by using a pseudo circuit equivalent to the word line and the row decoder, thereby taking into account the delay of the word line due to process variations, and the delay of the word line circuit. The time can be set optimally.

FIG. 11 shows an example of a row decoder and a word line in a semiconductor memory. As shown in FIG. 10, one word line is commonly connected to a plurality of memory cells, and the row decoder selects a specific row in a memory cell array arranged in a matrix. I can do it.

In FIG. 11, a row decoder RD has an inverted signal / RD of a row decoder precharge signal RDPC.
The PMOS transistor TP1 that the PC inputs to the gate and the three series NMOS transistors TN1 to TN1 that the predecoder signals XA, XB, XC input to the gate respectively.
NAND type decoding circuit DE in which TN3 is connected in series
C, a two-stage inverter INV1, INV2, and a transfer gate NM in which the power supply voltage Vcc is input to the gate.
It comprises an OS transistor TN4, an inverter (word line driver) DRV using the boosted voltage Vpp as a power supply, and a PMOS transistor TP2 for feedback.

On word line WL, row decoder R
The part where the wiring distance from D becomes longer in order is the node N1,
The nodes are referred to as a node N2 and a node N3. In this example,
The node N1 is at the root of the word line WL (the portion closest to the row decoder RD), the node N2 is at the middle of the word line WL,
The node N3 is the end of the word line WL (the part farthest from the row decoder RD).

FIG. 12 shows an example of operation waveforms of the circuit of FIG. In other words, the decoding circuit DEC has the / RDP
When C = “L”, the output node is precharged to “H”. Thereafter, the decoding operation is performed when / RDPC = “H”. In this case, the predecode signal X
When all of A, XB and XC are at "H" (= Vcc), the output node becomes "L" (= Vss = 0V) and any of the predecoder signals XA, XB and XC is "L". And the output node remains at "H".

The output signal of the decoding circuit DEC is 2
The data is input to the word line driver DRV via the inverters INV1 and INV2 of the stage and the NMOS transistor TN4 for the transfer gate.

At this time, when the output node of the decode circuit DEC is "L" (selected state), a boosted voltage Vpp higher than Vcc is applied to the word line WL, so that the power supply node of the word line driver DRV and the feedback node are used. PM
Vpp is connected to the source of the OS transistor TP2.

A power supply node of the inverters INV1 and INV2 is connected to Vcc,
By connecting an NMOS transistor TN4 for a transfer gate between the output node b of No. 2 and the input node c of the word line driver DRV and connecting its gate to Vcc, the high voltage of the node c is not transmitted to the node b. I have to.

Next, a specific operation will be described. When the word line WL is selected, all of the predecode signals XA, XB, XC are "H" (= Vcc), the output of the decode circuit DEC is Vss, the output node a of the first-stage inverter circuit INV1 is Vcc, and The output node b of the stage inverter circuit INV2 and the one end node c of the transfer gate NMOS transistor TN4 become Vss, the output of the word line driver DRV becomes Vpp, and the nodes N1, N2, N3 of the word line WL become Vpp. Becomes In this case, the word line WL is connected to the nodes N1, N2, N
Stand up in order of 3.

When the word line WL is not selected, one of the predecoder signals XA, XB and XC is at Vss, the output node a of the first-stage inverter circuit INV1 is at Vss, and the output node b of the next-stage inverter circuit INV2 is at Vcc. Becomes
One end side node c of the transfer gate NMOS transistor TN4 becomes Vpp, and the word line driver DRV
Becomes Vss, and the nodes N1 and N1 of the word line WL
2 and N3 are each at Vss. In this case, the word line W
L falls in the order of nodes N1, N2, and N3.

FIG. 13 shows a conventional example of a word line delay detection circuit for monitoring the delay time of the word line WL in FIG. The word line delay detection circuit shown in FIG. 13 includes a pseudo row decoder 11 corresponding to a part of the row decoder RD (after the first-stage inverter INV2) in FIG.
A pseudo word line 12 equivalent to the word line WL in FIG.
It comprises a word line voltage detection circuit 130 having the node N3 of the pseudo word line 12 as an input.

FIG. 14 shows an example of operation waveforms of the circuit of FIG. Word line voltage detection circuit 130 in FIG.
Is that when the potential of the pseudo word line 12 rises sufficiently, the output signal LCTB goes to the “H” level, and when the potential of the pseudo word line 12 falls sufficiently, the output signal LCTB rises.
TB becomes "L" level.

Therefore, node N of pseudo word line 12
By monitoring the state of No. 3, it can be determined whether the potential of the word line WL in FIG. 11 has risen sufficiently or has fallen sufficiently.

Meanwhile, with the increasing demands for large capacity, high speed, low power consumption, and low cost of memories, new problems have arisen to meet the demands. In other words, in terms of increasing the capacity and reducing the cost, the number of cells driven by one word line increases, whereas when many cells are connected to one word line, the parasitic capacitance C of the word line increases. , The time constant of the parasitic resistance R increases, which is disadvantageous for speeding up.

Further, even if the word line driving capability is simply increased, it is disadvantageous from the viewpoint of low power consumption. In order to realize a high speed without increasing the power of the word line driving, the rising time of the word line voltage, Techniques for shortening the fall time have been considered.

In this method, the resistance of the word line is reduced in process to reduce the CR time constant, and the rising and falling of the word line voltage are made faster. Also, by design,
Root (node N1) and end (node N) of word line WL
A method of adding a discharge transistor to 3) to shorten the fall time of the word line voltage can be considered.

FIG. 15 shows a pseudo word line 12 similar to a word line circuit in which a discharge transistor is connected to a word line.
2 shows a pseudo word line circuit in which a discharging transistor is connected together with a pseudo row decoder 11.

That is, in the circuit shown in FIG. 15, at the root (node N1) and the end (node N3) of the pseudo word line 12, the discharging NMOS transistors T1 and T2 whose gates receive the word line precharge signal RDPC are provided. It is connected.

FIG. 16 shows an example of the operation waveform of the circuit of FIG. In the circuit of FIG. 15, the potential of the node N1 at the root of the pseudo word line 12 and the potential of the node N3 at the end fall almost simultaneously, and the fall of the potential of the intermediate node N2 becomes slower than those of the nodes N1 and N3.

Therefore, when the voltage is monitored at the node N3 as in the conventional example, it is erroneously determined that the word line potential has fallen sufficiently at a timing when the word line potential has not fallen sufficiently. It becomes impossible to set an optimal delay time for the word line system.

[0024]

As described above, the conventional semiconductor memory device determines whether the potential of the word line has risen sufficiently or has fallen sufficiently by monitoring the state of the end of the pseudo word line. In order to respond to demands for large capacity, high speed, low power consumption, and low cost of memory, mistaken determination is made when a discharge transistor that shortens the fall time of the word line voltage is connected to the word line, There has been a problem that an optimal delay time cannot be set.

The present invention has been made to solve the above-mentioned problems. Even when a word line circuit in which a discharge transistor is connected to a word line is used, a plurality of nodes of a pseudo word line equivalent to the word line are used. By monitoring and latching the state of the word line, it is possible to accurately determine whether the potential of the word line has risen sufficiently or has fallen sufficiently, and based on the result of the determination, set an optimal delay time for the actual word line system. It is an object of the present invention to provide a semiconductor memory device capable of performing the following.

[0026]

A semiconductor memory device according to the present invention comprises: a memory cell array in which a plurality of memory cells are arranged in a matrix; a plurality of word lines arranged in a row direction of the memory cell array; A row decoder circuit for driving a line, a pseudo row decoder circuit equivalent to the row decoder circuit, a pseudo word line driven by the pseudo row decoder circuit, and voltage states of a plurality of nodes on the pseudo word line are monitored. By latching
Detecting that a plurality of nodes have risen to a certain voltage or more when the word line is in a selected state and that a plurality of nodes have fallen to a certain voltage or less when the word line is in a non-selected state, A word line voltage detection circuit having a function of determining a period from a time when the word line is in a selected state and rises to a certain voltage or more to a time when the word line is in a non-selection state and falls to a certain voltage or less. I do.

[0027]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a word line delay detection circuit in the semiconductor memory according to the first embodiment.

The semiconductor memory of the first embodiment has a memory cell array in which a plurality of memory cells are arranged in a matrix, and a plurality of word lines arranged in a row direction of the memory cell array, like the conventional semiconductor memory. , A row decoder circuit for driving the word line, and a word line delay detection circuit as shown in FIG.

In the word line delay detection circuit shown in FIG. 1, 11 is a pseudo row decoder circuit equivalent to the row decoder, 12 is a pseudo word line driven by the pseudo row decoder circuit, and 13 is a word line voltage detection circuit. .

The pseudo word line 12 has a gate to which a word line precharge signal RDPC is input corresponding to the root (node N1) and the terminal (node N3), similarly to the pseudo word line circuit shown in FIG. The discharging NMOS transistors T1 and T2 are connected.

The word line voltage detection circuit 13 monitors and latches the states of the plurality of nodes of the pseudo word line 12, so that when the word line is selected, the plurality of nodes of the word line rise to a certain voltage or higher. (When the potential of the word line has risen sufficiently) and when a plurality of nodes of the word line have fallen below a certain voltage when the word line has been deselected (the potential of the word line has fallen sufficiently). And a function of determining a period from when the word line is selected and rises above a certain voltage to when it is not selected and falls below a certain voltage.

In this example, the word line voltage detection circuit 13
Node N3 at or near the end of pseudo word line 12
A first voltage detection circuit having an input signal as an input signal, a second voltage detection circuit having an intermediate node N2 of the pseudo word line 12 as an input signal, and a latch circuit receiving output signals of the two voltage detection circuits. Is provided.

With such a configuration, the word line voltage detection circuit 13 monitors the signals at the node N3 and the intermediate node N2 at or near the end of the pseudo word line 12, so that the potential of the word line is sufficiently raised. It is possible to accurately determine a period until the potential of the word line falls sufficiently. Then, based on the determination result, it is possible to set an optimum delay time for an actual word line system.

FIG. 2 shows an example of an operation waveform of the word line delay detection circuit shown in FIG. Since the pseudo row decoder circuit 11 performs the same operation as the conventional pseudo row decoder circuit, the rising of the pseudo word line 12 is in the order of the nodes N1, N2 and N3, and the falling of the pseudo word line 12 is the node N1 and N3 are almost simultaneous, and node N
2 is the slowest.

In this example, in order to detect the timing at which all the word lines in the cell array sufficiently rise or fall sufficiently, the rising edge of the signal connected to the word line voltage detection circuit 13 is the node N3 of the pseudo word line 12. , And at the time of falling, a signal from the node N2 of the pseudo word line 12 is extracted.

The word line voltage detection circuit 13 latches after separately detecting the signal from the node N3 and the signal from the node N2, so that the word line voltage detection circuit 13 rises after the pseudo word line 12 sufficiently rises, and rises. Generates a signal LCTB that falls after falling sufficiently.

FIG. 3 shows the word line voltage detecting circuit 1 shown in FIG.
3 shows a specific example. First voltage detection circuit 131
Is the first node to which the signal of the first node (in this example, the node N3 at or near the end of the pseudo word line 12) is inputted to detect the rise of the potential of the pseudo word line 12.
, And a level shift circuit 251 connected to the output side of the first Schmitt trigger circuit 21, and two-stage inverters 261 and 271.

The first Schmitt trigger circuit 21 includes:
Two PMOS transistors 211 and 212 and two NMOS transistors 2 are connected between the Vpp node and the Vss node.
13 and 214 are connected in series, and an inverter to which a signal for detecting the rise of the potential of the pseudo word line 12 (the signal of the node N3 in this example) is input to its gate node A, the Vpp node, and The drain and source are connected between the NMOS transistor 213 and the series connection node of the NMOS transistor 214, and the gate thereof is connected to the output node of the inverter (the PMOS transistor 212 and the NMOS transistor NM).
And an NMOS transistor 215 connected to a series connection node of the OS transistor 213).

The second voltage detection circuit 132 receives a signal of a second node (in this example, an intermediate node N2 of the pseudo word line 12) to detect a fall of the potential of the pseudo word line 12. A second Schmitt trigger circuit 22, a level shift circuit 252 connected to the output side of the second Schmitt trigger circuit 22, a two-stage inverter 262,
272.

The second Schmitt trigger circuit 22 includes:
Two PMOS transistors 221 and 222 and two NMOS transistors 2 are connected between the Vpp node and the Vss node.
23 and 224 are connected in series, and an inverter whose gate node C receives a signal (signal of node N2) for detecting the fall of the potential of the pseudo word line 12, and the two PMOS transistors 221 , 222 connected between the source and the drain between the series connection node and the Vss node, the gate of which is connected to the output node of the inverter (the series connection node of the PMOS transistor 222 and the NMOS transistor 223).
And an S transistor 225.

The latch circuit 30 includes one PMOS transistor 301 and two NMOS transistors 302, 3 connected in series between the Vcc node and the Vss node.
03, the PMOS transistor 301 and the NMO
A first inverter 31 having an input node connected to a connection node between the drains of the S transistor 302, a second inverter 32 connected in anti-parallel to the first inverter 31, and an output of the first inverter 31; A third inverter having an input node connected to the node.

The gates of the PMOS transistor 301 and the NMOS transistor 302 whose drains are connected to each other are commonly connected to a first input node B, and the gates of the remaining NMOS transistors 303 are connected to a second input node B. Connected to node D.

The input threshold value of the first Schmitt trigger circuit 21 is set higher than the input threshold value of the second Schmitt trigger circuit 22. In this example, the input threshold value of the first Schmitt trigger circuit 21 is 0. .9 × Vcc, and the input threshold of the second Schmitt trigger circuit 22 is set to 0.1 × Vcc.

With the above configuration, when the potential of the pseudo word line 12 rises, the potential of the pseudo word line 12 becomes "L" level in the order of the node D and the node B, and the portion of the pseudo word line 12 where the potential rises slowly is 0.9.times.Vcc. When the node D and B rise to the same level, both the nodes D and B become "L" level. At this time, the PMOS transistor 301 of the latch circuit 30 is turned on, and the output signal LCTB of the latch circuit 30 becomes "H" level.

On the other hand, when the potential of the pseudo word line 12 falls, the potential of the pseudo word line 12 becomes "H" level in the order of the nodes B and D, and the portion where the potential of the pseudo word line 12 falls slowly falls to 0.1.times.Vcc. At this time, both nodes B and D attain the "H" level, and at this time the N
MOS transistor 303 is turned on, and output signal LCTB of latch circuit 30 attains "L" level.

According to the word line delay detection circuit of the first embodiment, the two voltages of the pseudo word line 12 having different timings of rising and falling of the voltage depending on the location are input to the word line voltage detection circuit 30. The detection signal LCTB is generated by detecting that the voltage of the word line has become equal to or higher than a certain voltage and detecting that the voltage of the word line has become equal to or lower than the certain voltage.

FIG. 4 shows another example of the latch circuit 30 in FIG. In the latch circuit 30a, output nodes of two two-input NAND gates 41 and 42 and one input node thereof are cross-connected, and the other input nodes of the two two-input NAND gates 41 and 42 correspond to each other. Connected to the nodes B and D.

The operation of latch circuit 30a is equivalent to the operation of latch circuit 30 shown in FIG. By the way, in the configuration as shown in FIG.
It is conceivable that the voltage waveform (particularly the falling waveform) of the pseudo word line 12 changes with the change of the power supply voltage Vcc and the process parameter. This will be described in detail below.

FIG. 5 shows the pseudo row decoder 1 shown in FIG.
1 shows a voltage waveform of the pseudo word line 12 according to a change of the power supply voltage Vcc. When Vcc is 5 V and 3 V, there is no change when the voltage of the pseudo word line 12 rises, but when the voltage of the pseudo word line 12 falls, the nodes N1, N2, N3 Fall order changes.

That is, the pseudo word line 12 when Vcc = 5V
When the voltage of the pseudo word line 12 falls when Vcc = 3V, the nodes N1 and N3 are almost at the same time, and the node N2 is delayed. It falls in the order of N2 and N1.

When the output voltage of the word line driver DRV drops and the voltage of the pseudo word line 12 falls, the node N1 starts after the voltage of the pseudo word line 12 starts falling.
Is the threshold voltage Vthp of the PMOS transistor TP2.
Until the input node c of the word line driver DRV
Is Vcc-Vthn (Vthn is the NMOS transistor TN4
(Threshold voltage).

When the voltage of the pseudo word line 12 falls when Vcc = 5V, the potential of the input node c of the word line driver DRV at the start of the fall is Vcc-Vthn = 5.
V−0.5V = 4.5V, and the word line driver DR
V NMOS transistor is fully turned on and the node N1
Falls immediately.

On the other hand, when the voltage of the pseudo word line 12 falls when Vcc = 3 V, the potential of the input node c of the word line driver DRV becomes V at the start of the fall.
cc−Vthn = 3V−0.5V = 2.5V, and the PMOS transistor and NMO of the word line driver DRV
Both the S transistors are turned on, the fall of the node N1 is delayed, and the nodes N3, N2, N
Decrease in order of 1.

At this time, after the node N1 has dropped to Vthp or less, the feedback PMOS transistor TP
2 is turned on, the potential of the input node c of the word line driver DRV is charged to Vpp, the NMOS transistor of the word line driver DRV is turned on, and the node N1 can be completely discharged to Vss.

Further, as described above, the pseudo word line 12
The timing at which the fall of the node N1 is delayed is Vth
There is also a possibility that it will vary depending on p or Vthn. FIG. 6 shows a word line delay detection circuit in a semiconductor memory according to a second embodiment configured to solve the above-described problem.

The word line delay detection circuit of the second embodiment differs from the word line delay detection circuit of the first embodiment described above with reference to FIG. Pseudo row decoder 11, pseudo word line 1
2 and the like have the same configuration, and thus are given the same reference numerals as in FIG.

That is, the word line voltage detection circuit in FIG.
Signals at the nodes N1 and N3 of the pseudo word line 12 are input, and the rise of the pseudo word line voltage is detected at the node N3, and the fall is detected at the node N1.

According to the word line delay detection circuit of the second embodiment described above, two voltages of the pseudo word line 12 having different timings of rising and falling of the voltage depending on the location are input to the word line voltage detection circuit 13. Then, the fact that a plurality of nodes (substantially all places) of the pseudo word line 12 have become equal to or higher than a certain voltage and the plurality of nodes (substantially all places) of the pseudo word line 12 have become equal to or lower than a certain voltage. It is characterized by detecting and generating a detection signal.

In the present embodiment, the rise and fall of the word line voltage are detected at one place on the pseudo word line 12 (the node where the rise of the word line voltage is the slowest and the node where the fall is the slowest). ing.

When the node on the pseudo word line 12 where the rise of the voltage is the slowest and the node where the fall is the slowest change, the voltage rises on the pseudo word line 12 from among three or more nodes. By setting the word line voltage detection circuit so that the timing of the slowest node and the slowest node can be detected, it is possible to set a necessary and sufficient delay time for the actual word line system. become.

In this case, as in a third embodiment described later,
The detection of the rise of the voltage of the pseudo word line 12 may be performed at one place, and the detection of the fall of the voltage of the pseudo word line 12 may be performed at a plurality of places, or the detection of the rise may be performed at a plurality of places. The fall detection may be performed at one point.

FIG. 7 shows a word line delay detecting circuit in a semiconductor memory according to the third embodiment. This word line delay detection circuit differs from the word line delay detection circuit of the first embodiment described with reference to FIG.
The same reference numerals as in the figure are used.

That is, the word line voltage detection circuit 13 shown in FIG.
a, the signals of the nodes N1, N2, and N3 of the pseudo word line are input, and the detection at the time of the rise of the pseudo word line voltage is the first.
As in the embodiment, the detection is performed at the node N3, and the falling detection is performed at the node N1 or N2.

FIG. 8 shows the word line voltage detecting circuit 1 in FIG.
3a shows a specific example. This word line voltage detection circuit differs from the word line voltage detection circuit of the first embodiment described above with reference to FIG. 3 in that a third voltage detection circuit 133 for detecting a fall is added. 30b is the third
3 is different in that it further has an input node F to which the output signal of the voltage detection circuit 133 is input, and the other configuration is the same.

That is, in FIG. 8, reference numeral 131 denotes a first voltage detection circuit for detecting a rise, and 132 denotes a second voltage detection circuit for detecting a fall. The third voltage detection circuit 133 for detecting a falling edge includes a third Schmitt trigger circuit 23 for detecting a falling edge and a level shift circuit 253.
And two stages of inverter circuits 263 and 273.

The third Schmitt trigger circuit 23
Two PMOS transistors 231 and 232 and two NMOS transistors 2 are connected between the Vpp node and the Vss node.
33 and 234 are connected in series, and an inverter whose gate node E receives a signal for detecting the fall of the potential of the pseudo word line 12;
Vss and the series connection node of S transistors 231 and 232
The source and drain are connected between the node and
The PMOS transistor 23 whose gate is connected to the output node of the inverter (a node in which the PMOS transistor 232 and the NMOS transistor 233 are connected in series)
5

The input threshold value of the third Schmitt trigger circuit 23 is equal to the input threshold value of the second Schmitt trigger circuit 22 of the second voltage detection circuit 132 (0.1 × in this example).
Vcc).

The latch circuit 30b is different from the latch circuit 30 of the first embodiment described above with reference to FIG. 3 in that one PMO connected in series between the Vcc node and the Vss node.
The difference is that one NMOS transistor 304 is additionally connected in series to the S transistor 301 and the two NMOS transistors 302 and 303.
The gate of the additionally connected NMOS transistor 304 is connected to the node F, and the output of the third voltage detection circuit 133 is input to the node F.

In this example, a rising detection signal is input to the input node A of the first Schmitt trigger circuit 21 from the node N3 at or near the end of the pseudo word line 12, and the base of the pseudo word line 12 or its vicinity is detected. From the node N1 of the pseudo-word line 1 to the input node C of the second Schmitt trigger circuit 22.
The signal for falling detection from the intermediate node N2 of the second
To the input node E of the Schmitt trigger circuit 23 of FIG.

In the third embodiment as described above, the latch circuit 30b outputs the lower one of the outputs of the two voltage detectors 132 and 133 for detecting the fall, and the potential of the pseudo word line 12. Receives and latches the output which is slower to fall to 0.1 × Vcc, and outputs the output signal LCT.
B falls.

In the third embodiment as described above, even if the slowest node changes to N2 or N1 due to process variation or the like, a sufficient delay time is generated by reliably following the change. can do.

FIG. 9 shows another example of the latch circuit 30b in FIG. The latch circuit 30c includes a two-input NAND gate 91 in which each input node is connected to a second input node D and a third input node F, and two output nodes in which each output node and one input node are cross-connected. The two-input NAND gates 92 and 93,
Are connected to the node B, and the output node of the NAND gate 91 is connected to the other input node of the NAND gate 93.

The operation of latch circuit 30c is equivalent to the operation of latch circuit 30b in FIG. In addition,
Not only the word line of each of the above embodiments, but also a signal line (for example, NAN in a NAND type EEPROM) in which the rise and fall of the voltage have different timings depending on the location.
In the case of detecting a delay of a selection gate line for selectively driving a selection transistor inserted and connected to the bit line side and the source line side of the D-type cell, the word line delay detection circuit of the first embodiment is also used. It is possible to implement according to it.

[0074]

As described above, according to the semiconductor memory device of the present invention, even if the potential rises and falls at the root and the end of the word line due to the increase in the capacity, a delay occurs on the pseudo word line. By detecting signals from a plurality of nodes, it is possible to accurately detect whether the potential of the word line has risen sufficiently or has fallen sufficiently, and to generate a detection signal at an optimal timing.

Further, even when the rise or fall timing of the word line potential changes due to process variations, a detection signal can be generated at an optimal timing, so that process variations can be compensated, device yield can be improved, and reliability can be improved. Can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a word line delay detection circuit in a semiconductor memory according to a first embodiment of the present invention.

FIG. 2 is a waveform chart showing an example of the operation of the word line delay detection circuit shown in FIG.

FIG. 3 is a circuit diagram showing an example of a word line voltage detection circuit in FIG.

FIG. 4 is a circuit diagram showing another example of the latch circuit in FIG. 3;

FIG. 5 is a power supply voltage Vcc of the pseudo row decoder shown in FIG. 1;
FIG. 6 is a diagram showing a voltage waveform of a pseudo word line according to a change in the voltage.

FIG. 6 is a circuit diagram showing a word line delay detection circuit in a semiconductor memory according to a second embodiment of the present invention.

FIG. 7 is a circuit diagram showing a word line delay detection circuit in a semiconductor memory according to a third embodiment of the present invention.

8 is a circuit diagram showing a specific example of a word line voltage detection circuit in FIG.

FIG. 9 is a circuit diagram showing another example of the latch circuit in FIG. 8;

FIG. 10 is a block diagram showing a schematic configuration of a semiconductor memory.

FIG. 11 is a circuit diagram showing an example of a row decoder and a word line in a semiconductor memory.

12 is a waveform chart showing an example of the operation of the circuit in FIG.

13 is a circuit diagram showing a conventional example of a word line delay detection circuit for monitoring a delay time of a word line in FIG.

14 is a waveform chart showing an example of the operation of the circuit in FIG.

FIG. 15 is a circuit diagram showing a pseudo word line in which a discharging transistor is connected to a pseudo word line together with a pseudo row decoder.

16 is a waveform chart showing an example of the operation of the circuit in FIG.

[Explanation of symbols]

 11: pseudo row decoder circuit, 12: pseudo word line, T1, T2: NMOS transistor for discharging, 13: word line voltage detection circuit.

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Takashi Ogiwara 580-1, Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa F-term in the Toshiba Semiconductor System Technology Center (reference) 5B015 HH01 HH03 JJ24 JJ45 KA28 KB44 KB89 5B024 AA04 AA15 BA13 BA18 BA21 CA27

Claims (7)

[Claims] A memory cell array in which a plurality of memory cells are arranged in a matrix; a plurality of word lines arranged in a row direction of the memory cell array; a row decoder circuit for driving the word lines; A pseudo-row decoder circuit equivalent to a circuit; a pseudo-word line driven by the pseudo-row decoder circuit; and monitoring and latching the voltage state of a plurality of nodes on the pseudo-word line, thereby setting the word line to a selected state. When the word line is in a selected state, it is detected that a plurality of nodes have risen to a certain voltage or more when the word line has become unselected, and that the plurality of nodes have fallen to a certain voltage or less when the word line has been deselected. It has a function to determine the period from when it rises above a certain voltage to when it becomes unselected and falls below a certain voltage. The semiconductor memory device characterized by comprising a lead wire voltage detection circuit. 2. The semiconductor memory device according to claim 1, wherein said word line voltage detection circuit includes a first node having a first node of said pseudo word line as an input signal.
And a second node having a second node of the pseudo word line as an input signal.
And a latch circuit for inputting output signals of the first voltage detection circuit and the second voltage detection circuit. 3. The semiconductor memory device according to claim 2, wherein the first node of the pseudo word line is a part of the pseudo word line farthest from the pseudo row decoder or in the vicinity thereof, and the pseudo word line Wherein the second node is a portion of the pseudo word line closest to the pseudo row decoder or in the vicinity thereof. 4. The semiconductor memory device according to claim 2, wherein said first voltage detection circuit and said second voltage detection circuit comprise:
A semiconductor memory device comprising a Schmitt trigger circuit. 5. The semiconductor memory device according to claim 1, wherein said word line voltage detection circuit includes a first node having a first node of said pseudo word line as an input signal.
A second voltage detection circuit that uses second to nth (n−1) nodes of the pseudo word line as input signals; a first voltage detection circuit; and a second voltage detection circuit. And a latch circuit for inputting an output signal of the voltage detection circuit. 6. The semiconductor memory device according to claim 5, wherein the first node of the pseudo word line is a part of the pseudo word line farthest from the pseudo row decoder or in the vicinity thereof, and the pseudo word line The second and subsequent nodes of the pseudo word line are nodes other than the first node and are nodes closer to the pseudo row decoder than the first node. Semiconductor storage device. 7. The semiconductor memory device according to claim 5, wherein said first voltage detection circuit and said second voltage detection circuit comprise:
A semiconductor memory device comprising a Schmitt trigger circuit.