JPH09198894A - Semiconductor memory and testing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable easily and quickly testing to clarify whether a memory cell is normal or unstable. SOLUTION: A P-channel MOS transistor 1 with a small gate width is connected between bit line pairs BL (BL1...) and/BL1 (/BL1...). A data '1' is written into all memory cells MC to activate all the memory cells and then, a P-channel MOS transistor 1 is made to conduct to invert the data of an unstable memory cell to 0. The data of the memory cells MC are read out sequentially to judge that the memory cell storing the data '1' is normal. The memory cell storing the data '0' is determined to be an unstable memory cell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method for testing the same, and more particularly to a semiconductor device having a test mode for selecting an unstable memory cell that easily inverts from a first memory state to a second memory state. The present invention relates to a storage device and a test method thereof.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a structure of a conventional static random access memory (hereinafter referred to as SRAM).

Referring to FIG. 4, this SRAM has a plurality of (four for the sake of simplification of description) memory cells MC1 to MC4 arranged in a matrix and word lines provided corresponding to each row. WL1 and WL2, and bit line pairs BL1, / BL1; BL2, / BL2 provided corresponding to each column.

Further, this SRAM has bit lines BL1 to BL1.
Bit line load 3 for charging / BL2 to a predetermined potential
1 to 34, and the bit line pair BL1, / BL during the read operation
1; equalizers 35 and 36 for equalizing the potential between BL2 and / BL2, and bit line pair BL1 and / BL
1; BL2, / BL2 and data signal input / output line pair IO, /
Column select gates 37 and 38 for connecting to IO are provided.

Each of bit line loads 31 to 34 is an N channel MOS transistor diode-connected between a line 60 of power supply potential Vcc (hereinafter referred to as a power supply line) and one end of a corresponding bit line BL1 to / BL2. Composed of. Each of the equalizers 35 and 36 is connected between the corresponding bit line pair BL1, / BL1; BL2, / BL2,
Its gate is formed of a P channel MOS transistor receiving bit line equalize signal / BLEQ. The column selection gate 37 includes an N-channel MOS transistor connected between the other end of the bit line BL1 and one end of the data signal input / output line IO, the other end of the bit line / BL1 and one end of the data signal input / output line / IO. And N-channel MOS transistors connected between the two, the gates of the two N-channel MOS transistors are connected to one end of the column selection line CSL1.
The column selection gate 38 is an N-channel MO connected between the other end of the bit line BL2 and one end of the data signal input / output line IO.
N channel M connected between the S transistor and the other end of the bit line / BL2 and one end of the data signal input / output line / IO
The gates of the two N-channel MOS transistors including the OS transistor are connected to one end of the column selection line CSL2.

Further, this SRAM has a row decoder 3
9, a control circuit 40, a column decoder 41, a writing circuit 42, and a reading circuit 43. The row decoder 39 includes a plurality of word lines WL according to a row address signal given from the outside.
One of the word lines WL1 and WL2 is raised to the activation level "H" level. The control circuit 40 controls the entire SRAM according to a control signal given from the outside.
The column decoder 41 raises one of the plurality of column selection lines CSL1 and CSL2 to the activation level "H" level in accordance with a column address signal externally applied.

Write circuit 42 and read circuit 43 are both connected to the other end of data signal input / output line pair IO, / IO. The write circuit 42 writes the data externally applied via the data input terminal 44 into the memory cell selected by the row decoder 39 and the column decoder 41. The read circuit 43 outputs the read data from the memory cell selected by the row decoder 39 and the column decoder 41 to the outside through the data output terminal 45.

Next, the operation of the SRAM shown in FIG. 4 will be described. In the write operation, for example, word line WL1 is raised to the active level "H" by row decoder 39 to activate memory cells MC1 and MC2. Then, the column decoder 41 raises, for example, the column selection line CSL1 to the "H" level, which is the activation level, and the column selection gate 37 is turned on to activate the activated memory cell M.
C1 is connected to write circuit 42 via bit line pair BL1, / BL1 and data signal input / output line pair IO, / IO.

Write circuit 42 sets one of data signal input / output line pair IO, / IO to "H" level and the other to "L" level in accordance with externally applied data to memory cell MC1. Write the data. When the word line WL1 and the column selection line CSL1 fall to the “L” level, the data is stored in the memory cell MC1.

In a read operation, column decoder 41 raises column select line CSL1 to the active level of "H", column select gate 37 is rendered conductive, and bit line pair BL1, / BL1 receives a data signal. Output line pair IO, / IO
Is connected to the readout circuit 43 via. Then, the bit line equalize signal / BLEQ goes to the "L" level which is the activation level, the equalizers 35 and 36 become conductive, and the bit line B
The potentials of L1 and / BL1, BL2 and / BL2 are equalized. The bit line equalize signal / BLEQ becomes the inactive level "H" level and the equalizer 3
After 5, 36 are rendered non-conductive, row decoder 39 raises, for example, word line WL1 to the active level of "H", and memory cells MC1, MC2 are activated. As a result, a current flows into the memory cell MC1 from one of the bit line pair BL1, / BL1 according to the data stored in the memory cell MC1, and accordingly, of the data signal input / output line pair IO, / IO. One of the potentials drops. The read circuit 43 includes a data signal input / output line pair IO and / I.
The potentials of O are compared, and data corresponding to the comparison result is output to the outside via the data signal output terminal 45.

Next, the structure of the SRAM memory cell and its storage operation will be described. FIG. 5 is a circuit diagram showing the configuration of the memory cell MC1 of FIG. Referring to FIG. 5, this memory cell MC1 includes load resistance elements 51, 5
2, including driver transistors 53 and 54, access transistors 55 and 56, and storage nodes N1 and N2.
Load resistance elements 51 and 52 are connected between power supply line 60 and storage nodes N1 and N2, respectively. The driver transistors 53 and 54 have storage nodes N1 and N2, respectively.
And a line of ground potential GND (hereinafter referred to as a ground line)
61 and the gates thereof are connected to the storage nodes N2 and N1, respectively. Access transistor 5
Reference numerals 5 and 56 are connected between storage nodes N1 and N2 and bit lines BL1 and / BL1, respectively, and their gates are both connected to word line WL1.

The memory cell MC1 is composed of a flip-flop including two cross-coupled inverters. Here, these two inverters are the inverters including the load resistance element 51 and the driver transistor 53 when the word line WL1 is at the "L" level of the inactivation level and the memory cell MC1 is not activated. , Load resistance element 52 and driver transistor 5
4 means an inverter consisting of a bit line load 31, an access transistor 55 and a driver transistor 53 when the word line WL1 is at the "H" level of the activation level and the memory cell MC1 is activated. And an inverter composed of the bit line load 32, the access transistor 56 and the driver transistor 54.

FIG. 6 is a diagram showing the input / output transfer characteristics of these two inverters. First, the bit line load 32, the access transistor 56 and the driver transistor 54.
Consider an inverter composed of. In this case, voltage V1 between storage node N1 and ground line 61 becomes the input voltage of the inverter, and storage node N2 and ground line 6
The voltage V2 between 1 becomes the output voltage of the inverter. When the input voltage V1 is gradually increased from 0V, 0 ≦ V1
In the range of ≤Vth (Vth is the threshold voltage of the driver transistor 52), the driver transistor 54 becomes non-conductive and the output voltage V2 is Vcc-Vth (Vth is the threshold voltage of the bit line load 32). Become. When the input voltage V1 exceeds Vth, the driver transistor 5
4 conducts with a conduction resistance value corresponding to the input voltage V1, the output voltage V2 suddenly decreases as shown by the curve A in the figure, and then gradually decreases. At this time, the output voltage V2 has a value obtained by dividing the power supply voltage Vcc by the bit line load 32, the access transistor 56 and the driver transistor 54.

The input / output transfer characteristic of the inverter formed by the bit line load 31, the access transistor 55 and the driver transistor 53 is reversed from that of the above-mentioned inverter, and the input / output transfer characteristic thereof is shown by the curve B in FIG. Will be done.

Two intersections S1 and S2 of these two curves A and B are stable points when the memory cell MC1 is activated. At point S1, V1 is at "H" level and V2 is at "L".
This is a level, and shows a state in which data "1" is stored in the memory cell MC1. At point S2, V1 is "L"
V2 is "H" level and the memory cell MC1
Shows the state in which the data "0" is stored. To move the cell state of the memory cell MC1 from the stable point S1 to S2, for example, as described above, the write circuit 42 is used.
To set the bit line BL1 to the "L" level.
BL1 may be set to the “H” level.

The intersection point M of the curves A and B is a metastable point, and is stable at this point M when the cell state is equal to V1 and V2, but normally, the stable points S1 and S are due to a slight difference between V1 and V2.
Move to either of the two.

In the memory holding state where the memory cell MC1 is not activated, as described above, the memory cell MC1
Is a load resistance element 51 and a driver transistor 53.
And an inverter including a load resistance element 52 and a driver transistor 54.
In this case, the cell state of the memory cell MC1 is at the stable point P1 or P2 in FIG. That is, when the memory cell MC1 stores data “1”, the cell state is V1 =
When the memory cell MC1 stores the data "0" at the point P1 of Vcc and V2 = 0, the cell state is V1 =
0, V2 = Vcc at point P2.

It is now assumed that data "1" is stored in the memory cell MC1 and the cell state is at the stable point P1. When the memory cell MC1 is activated during the read operation, the cell state moves from the point P1 to the point S1. When the data reading is completed and the memory cell MC1 is deactivated, the cell state returns from the point S1 to the point P1 via the point P1 ′. When the data “0” is stored in the memory cell MC1,
Similarly, the cell state has a locus of P2 → S2 → P2 ′ → P2.

The memory cell MC1 is designed so that the areas surrounded by the curves A and B are equivalent and sufficiently large. The larger the area surrounded by the curves A and B, the more difficult the flip-flops forming the memory cell MC1 are to invert, and the more stable the operation. Other memory cells MC2 to MC
4 is the same.

[0020]

By the way, when the finished dimension of the photolithography process varies and the gate width W of the driver transistor 53 in FIG. 5 becomes larger than the design value by ΔW, the conduction resistance of the driver transistor 53 is increased. The value is lower than the design value. In this case, the output voltage V1 of the inverter composed of the bit line load 31, the access transistor 55 and the driver transistor 53 is lower than that in FIG. 6, and as shown in FIG. 7, the intersection M of the curves A and B is V1 = It comes to be located below the straight line of V2.

Such a memory cell MC operates normally under normal conditions, but if read operations of other memory cells MC in the same column are continuously performed, storage nodes N1 and N are generated.
The potential of 2 is affected by the potentials of the bit lines BL and / BL,
The cell state moves from point S1 to point S2.

Since such an unstable memory cell MC normally operates under normal conditions, the memory cell MC
In order to sort out, it is necessary to carry out a long-time test using a very complicated test pattern, which is a production problem.

Therefore, a main object of the present invention is to provide a semiconductor memory device and a test method therefor capable of easily and quickly testing whether a memory cell is normal or unstable.

[0024]

A semiconductor memory device according to the present invention is a semiconductor memory device having a test mode for selecting an unstable memory cell which is likely to be inverted from a first memory state to a second memory state. , A plurality of memory cells arranged in a matrix, word lines provided corresponding to each row, bit line pairs provided corresponding to each column, bit line loads provided corresponding to each bit line , And a plurality of memory cells connected between each pair of bit lines and conducting after the plurality of memory cells are activated by the word line in the test mode and in which the first storage state is written. Among these, a transistor for inverting the storage state of the unstable memory cell is provided.

In this semiconductor memory device, the first memory state is written in all memory cells, and after all memory cells are activated, it becomes conductive, and a transistor for inverting the memory state of the unstable memory cells is provided. To be Therefore, the unstable memory cells can be easily selected by reversing the memory states of the unstable memory cells and then reading the memory states of the respective memory cells. Therefore, it is possible to easily and quickly test whether each memory cell is normal or unstable, as compared with the related art in which a complicated test pattern is required.

The transistor may be rendered conductive in a saturated state in response to a test signal input after the plurality of memory cells are activated. This simplifies the configuration.

Further, there is provided a potential generating means for outputting a predetermined potential between a power source potential and a ground potential in response to a test signal input after the plurality of memory cells are activated, and the transistor is provided. It is also possible to conduct in an unsaturated state in response to the input of the predetermined potential from the potential generating means. In this case, since the gate length of the transistor may be long, the transistor can be easily manufactured.

Further, the potential generating means further responds to an equalizing signal for equalizing the potential of each bit line pair immediately before the selected memory cell is activated in the read operation, in response to the power supply potential or A ground potential may be output, and the transistor may be rendered conductive in a saturated state in response to input of a power supply potential or a ground potential from the potential generating means. In this case, the transistor doubles as an equalizer, so that the layout area can be small.

Further, the semiconductor memory device testing method according to the present invention includes a plurality of memory cells arranged in rows and columns, word lines provided corresponding to each row, and bit line pairs provided corresponding to each column. , And in a semiconductor memory device having a bit line load provided corresponding to each bit line, it is easy to determine whether each memory cell is normal or not from the first memory state to the second memory state. By connecting a transistor between each bit line pair, writing the first memory state to all memory cells, activating all memory cells, and then turning on the transistor. The memory state of the unstable memory cell is inverted, and then the memory state of each memory cell is read out, the memory cell of the first memory state is determined to be normal, and the memory cell of the second memory state is disabled. It is characterized by determining the constant memory cell.

In this semiconductor memory device testing method, a transistor is connected between each bit line, the first memory state is written in all memory cells, all memory cells are activated, and then the transistors are made conductive to cause instability. Inverts the storage state of the memory cell. Then, the storage state of each memory cell is read and the memory cell whose storage state is inverted is determined to be an unstable memory cell. Therefore, it is possible to easily and quickly test whether each memory cell is normal or unstable, as compared with the related art in which a complicated test pattern is required.

[0031]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 1 is a circuit diagram showing a structure of a main part of an SRAM according to a first embodiment of the present invention.

Referring to FIG. 1, this SRAM is a conventional S
The difference from RAM is the bit line pair BL1, / BL1; B.
The point is that the P-channel MOS transistor 1 used only in the test mode is connected between each of L2 and / BL2. A test mode signal / TEST is input to the gate of P channel MOS transistor 1. The test signal / TEST is input from the control circuit 40 of FIG. 4 or the outside.

Further, the N-channel MOS transistors and the equalizers 35 and 36 which constitute the bit line loads 31 to 34 are formed.
P-channel MOS transistor forming driver, N-channel MOS transistor forming driver transistors 53 and 54, N-channel MOS transistor forming access transistors 55 and 56, and P-channel MO transistor
Gate width W (μm) / gate length L of the S transistor 1
The design values of (μm) are 10 / 0.8 and 20 /, respectively.
0.6, 1.8 / 0.6, 0.6 / 0.6 and 2/2
It has become. The design values of the resistance values of the load resistance elements 51 and 52 are both 4 teraohms.

Next, a method of testing this SRAM will be described. First, data "1" is written in all the memory cells MC1 to MC4. That is, the memory cells MC1 to MC4
Each storage node N1 is set to "H" level and storage node N2 is set to "L" level. At this time, in the normal memory cell, the cell state is at point P1 in FIG. 6, and in the unstable memory cell in which the gate width W of the driver transistor 53 is larger than the design value by ΔW, the cell state is at point P1 in FIG.

Next, test mode signal / TEST is lowered to the activation level of "L" to make P channel MOS transistor 1 conductive in a saturated state. In this state, the row address is incremented and all word lines WL1, WL
2 is set to the activation level “H” level, and all memory cells M
Activate C1-MC4. At this time, P channel M
Since the size of the OS transistor 1 is W / L = 2/2, which is smaller than the size W / L = 20 / 0.6 of the equalizers 35 and 36, the bit lines BL1 and / BL1, BL2 and / B
Each of L2 is weakly equalized, and memory cells MC1 to MC1
The potentials V1 and V2 of the respective storage nodes N1 and N2 of MC4
Tries to approach a straight line of V1 = V2 as much as possible. At this time,
The cell state of the normal memory cell is slightly below the metastable point M in FIG. 6, and the cell state of the unstable memory cell is between the straight line of V1 = V2 and the metastable point M in FIG.

Then, the increment of the row address is stopped and all the word lines WL1 and WL2 are set to the inactive level "L" to inactivate all the memory cells MC1 to MC4. At this time, the cell state of the normal memory cell moves to the point P1 via the points S1 and P1 'in FIG. 6, and the unstable memory cell state changes to the point P2 through the points S2 and P2' in FIG. Move to P2. That is, the data of the normal memory cell becomes "1", but the data of the unstable memory cell is inverted to "0".

Next, the test mode signal / TEST is raised to the inactive level of "H" and the P channel MOS is turned on.
The transistor 1 is turned off, and the weak equalization is completed. After that, the data in each of the memory cells MC1 to MC4 is sequentially read, and the memory cell MC that stores the data “1”
Is determined to be normal, and the memory cell MC storing the data “0” is determined to be an unstable memory cell.

Then, data "0" is written in all the memory cells MC1 to MC4 and a similar test is performed. Thus, for example, an unstable memory cell in which the gate width W of the driver transistor 54 is larger than the design value by ΔW and the cell state is likely to be inverted from the point S2 to S1 is selected. Unstable memory cells are replaced by spare memory cells, for example.

In this embodiment, all memory cells MC1
After writing the same data to MC4, weak equalization is performed to invert the data in the unstable memory cell.
The unstable memory cells can be easily selected by reading the data of the memory cells MC1 to MC4.

[Second Embodiment] FIG. 2 is a circuit diagram showing a structure of a main portion of an SRAM according to a second embodiment of the present invention.

Referring to FIG. 2, this SRAM is a conventional S
The difference from RAM is the bit line pair BL1, / BL1; B.
A P-channel MOS transistor 2 used only in the test mode is connected between each of L2 and / BL2, and a potential generating circuit 21 is newly provided.

Potential generating circuit 21 includes a P channel MOS transistor 3, N channel MOS transistors 4, 5 and an inverter 6. P-channel MOS transistor 3 is connected between power supply line 60 and the gate of P-channel MOS transistor 2 (node N3). N-channel MOS transistor 4 is connected between node N3 and ground line 61. N-channel MOS transistor 5 is connected between power supply line 60 and node N3. The test mode signal / TEST is input to the gates of the MOS transistors 3, 4, 5 via the inverter 6.

Further, the N-channel MOS transistors and the equalizers 35 and 36 which constitute the bit line loads 31 to 34 are formed.
P-channel MOS transistor forming driver, N-channel MOS transistor forming driver transistors 53 and 54, N-channel MOS transistor forming access transistors 55 and 56, and P-channel MO transistor
Gate width W (μm) / gate length L of the S transistor 2
The design values of (μm) are 10 / 0.8 and 20 /, respectively.
0.6, 1.8 / 0.6, 0.6 / 0.6 and 20 /
It is 0.6. The design values of the resistance values of the load resistance elements 51 and 52 are both 4 teraohms.

When test mode signal / TEST is at the inactive level of "H", P channel MOS transistor 3 is conductive, N channel MOS transistors 4 and 5 are nonconductive, and node N3 is at the power supply potential. It becomes Vcc and the P-channel MOS transistor 2 becomes non-conductive. Therefore, weak equalization of bit lines BL1 and / BL1, BL2 and / BL2 is not performed.

When test mode signal / TEST falls to the "L" level of the activation level, P channel MOS transistor 3 is rendered non-conductive, N channel MOS transistors 4 and 5 are rendered conductive, and node N3 is N channel MOS. The power supply potential Vcc is divided by the conduction resistance value R4 of the transistor 4 and the conduction resistance R5 of the N-channel MOS transistor 5 to obtain a potential Vcc × R4 / (R4 + R5).
As a result, the P-channel MOS transistor 2 becomes conductive in an unsaturated state, and the bit lines BL1 and / BL1 and BL2 and / 2.
BL2 is weakly equalized.

The weak equalization during the test is the P channel M
It is the same as the first embodiment except that the P-channel MOS transistor 2 is used instead of the OS transistor 1.

Also in this embodiment, the same effect as that of the first embodiment can be obtained. [Third Embodiment] FIG. 3 is a circuit diagram showing a structure of a main portion of an SRAM according to a third embodiment of the present invention.

Referring to FIG. 3, this SRAM is a conventional S
The difference from the RAM is that a potential generation circuit 22 is newly provided, and the output potential of the potential generation circuit 22 is replaced with the bit line equalize signal / BLEQ at the gates of the P channel MOS transistors forming the equalizers 35 and 36. Is the point to be input.

The potential generating circuit 22 includes a P channel MOS transistor 7, N channel MOS transistors 8 and 9,
It includes an inverter 10 and a NAND gate 11. The P-channel MOS transistor 7 includes equalizers 35 and 36.
Is connected between the gate (node N4) of the P-channel MOS transistor forming the above and the power supply line 60. N-channel MOS transistor 8 is connected between node N4 and ground line 61. N-channel MOS transistor 9 is connected between power supply line 60 and node N4.
Test mode signal / TEST is input to the gate of N channel MOS transistor 9 via inverter 10 and also to one input node of NAND gate 11. Bit line equalize signal / BLEQ is NAN
It is input to the other input node of the D gate 11. NAND
The output of the gate 11 is input to the gates of the MOS transistors 7 and 8.

Further, the N-channel MOS transistors and the equalizers 35 and 36 which form the bit line loads 32 to 34.
Of the P-channel MOS transistor forming the P-channel MOS transistor, the N-channel MOS transistor forming the driver transistors 53 and 54, and the N-channel MOS transistor forming the access transistors 55 and 56.
m) / gate length L (μm) is 10 / each
0.8, 20 / 0.6, 1.8 / 0.6 and 0.6 /
It is 0.6. The design values of the resistance values of the load resistance elements 51 and 52 are both 4 teraohms.

When both test mode signal / TEST and bit line equalize signal / BLEQ are at the inactive level of "H", P channel MOS transistor 7 is conductive and N channel MOS transistors 8 and 9 are nonconductive. , The node N4 becomes the power supply potential Vcc, and P
The channel MOS transistors 35 and 36 become non-conductive. Therefore, the bit lines BL1 and / BL1, BL2 and / BL2 are not equalized.

The test mode signal / TEST is at the "L" level of the activation level and the bit line equalize signal / B.
When LEQ is at the "H" level of the deactivation level,
P-channel MOS transistor 7 becomes non-conductive, N-channel MOS transistors 8 and 9 become conductive, and node N4 has conduction resistance values R8 and N of N-channel MOS transistor 8.
Power supply potential Vcc is divided by the conduction resistance value R9 of the channel MOS transistor 9 and the potential Vcc × R8 /
(R8 + R9). This enables P-channel MOS
Transistors 35 and 36 are rendered conductive in an unsaturated state, and bit lines BL1 and / BL1 and BL2 and / BL2 are weakly equalized.

The test mode signal / TEST is at the "H" level of the inactivation level, and the bit line equalize signal / TEST
When BLEQ is the “L” level of the activation level,
The MOS transistors 7 and 9 become non-conductive and the N channel M
The OS transistor 8 is turned on and the node N4 is at the ground potential G.
It becomes ND. As a result, the P-channel MOS transistors 35 and 36 become conductive in the saturated state, and the bit lines BL1 and /
Strong equalization of BL1, BL2 and / BL2 is performed.

The weak equalization during the test is the P channel M
The second embodiment is the same as the second embodiment except that the equalizer 35 is used instead of the OS transistor 2.

Also in this embodiment, the same effect as that of the second embodiment can be obtained. Further, since the equalizers 35 and 36 also serve as the P-channel MOS transistor 2, the second embodiment will be described.
The layout area is smaller than that of.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a main part of an SRAM according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a main part of an SRAM according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a main part of an SRAM according to a third embodiment of the present invention.

FIG. 4 is a circuit block diagram showing a configuration of a conventional SRAM.

5 is a circuit diagram showing a configuration of a memory cell of the SRAM shown in FIG.

FIG. 6 is a diagram for explaining a storage operation of the memory cell shown in FIG.

FIG. 7 is a diagram for explaining the operation of an unstable memory cell.

[Explanation of symbols]

1, 2, 3, 7 P-channel MOS transistor, 4,
5,8,9 N-channel MOS transistor, 6,10
Inverter, 11 NAND gate, 21, 22 potential generation circuit, 31-34 bit line load, 35, 36
Equalizer, 37, 38 column select gate, 39 row decoder, 40 control circuit, 41 column decoder, 42 write circuit, 43 read circuit, 44 data input terminal, 45
Data output terminal, 51, 52 Load resistance element, 53, 5
4 driver transistor, 55, 56 access transistor, 60 power supply line, 61 ground line, MC
1 to MC4 memory cells, WL1, WL2 word lines,
BL1, / BL1; BL2, / BL2 Bit line pair.

Claims (5)

[Claims] 1. A semiconductor memory device having a test mode for selecting an unstable memory cell that easily inverts from a first memory state to a second memory state, the plurality of memory cells being arranged in a matrix. A word line provided corresponding to each row, a bit line pair provided corresponding to each column, a bit line load provided corresponding to each bit line, and connected between each bit line pair, and In the test mode, the word line is activated after the plurality of memory cells are activated and then turned on, and the storage state of the unstable memory cell is inverted among the plurality of memory cells in which the first storage state is written. A semiconductor memory device comprising a transistor for causing the semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein said transistor is rendered conductive in a saturated state in response to a test signal input after activation of said plurality of memory cells. 3. The transistor further comprises potential generating means for outputting a predetermined potential between a power source potential and a ground potential in response to a test signal input after the plurality of memory cells are activated. Is conductive in an unsaturated state in response to the input of the predetermined potential from the potential generating means,
The semiconductor memory device according to claim 1. 4. The potential generating means further responds to an equalize signal for equalizing the potential of each bit line pair immediately before a selected memory cell is activated in a read operation, in response to a power supply potential or 4. The semiconductor memory device according to claim 3, wherein the transistor outputs a ground potential, and the transistor further conducts in a saturated state in response to a power supply potential or a ground potential input from the potential generating means. 5. A plurality of memory cells arranged in a matrix, a word line provided corresponding to each row, a bit line pair provided corresponding to each column, and a bit line provided corresponding to each bit line. In a semiconductor memory device having a bit line load, a method of testing whether each memory cell is a normal memory cell or an unstable memory cell that easily inverts from a first memory state to a second memory state, Transistors are connected between each pair of bit lines to write the first memory state to all memory cells, activate all memory cells, and then make the transistors conductive to invert the memory states of the unstable memory cells. ,afterwards,
A method for testing a semiconductor memory device, comprising: reading a storage state of each memory cell, determining that a memory cell row in the first storage state is normal and determining a memory cell in the second storage state as an unstable memory cell.