JPH09197012A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the degree of freedom of designing product by automatically generating a RAM test pattern and expected value and comparing the results of the value and RAM output, and combining the holding signal with a user logic circuit in the case of generating discordance. SOLUTION: The clock signal 102 of a clock generator 100 is input to a circuit 100, and a RAM test address data signal 115 output from the circuit 110 and address data signal 205 from a user logic circuit 200 are input to a selector 300, and both the signals 115 and 205 are selected by the selector 300. At the time of the RAM test state, the signal 115 and RAM testing read/write control and chip select signal 116 are selected. A comparator 410 compares an expected value 112 with a RAM output 321 when enabling state is obtained by a comparison enable signal 113, the comparison result 411 is input to a discordance result holding circuit 420, and when discordance result is output, the discordance generating state is held, and a discordance result hold signal 421 is input to the circuit 200.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a random access memory test circuit, and more particularly to a RAM test circuit incorporated in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 5 shows an example of a conventional RAM test circuit. An address data signal 115, a read / write chip select signal 116, and a user logic circuit 20 which are directly input from the outside of the chip for RAM control.
An address data signal 205 and a read / write chip select signal 206, which are signals for performing a RAM operation from 0, are connected to the selector 300. These signal groups 115, 116, 205 and 206 are selected by the RAM test state setting signal 119, and the address / data signal 305 and the read / write chip select signal 3 are selected.
06, which is connected to the RAM 320. And RA
The M output 321 is the user logic circuit 200 and the selector 23.
Connected to 0. The external signal 201 from the user logic circuit 200 is also input to the selector 230. The output signal 321 or the external output signal 201 described above is switched from the output 231 of the selector 230 by the RAM test state setting signal 119 and is output to the outside of the chip.

When performing a RAM unit test, the RAM
The test status is set by the test status setting signal 119, the RAM test pattern is automatically generated by the LSI tester, and the address / data signal 115 and the read / write signal 116 are output. The test pattern for the RAM test includes a pattern for writing "1" and "0" for all bits of all addresses, a pattern for writing data in which "1" and "0" are alternately combined. , There is a pattern to write the same value as the address to the data, etc. RAM operation such as repeating the write and read alternately according to the contents of these test patterns, or repeating the read operation after performing the write operation to all addresses. There are various methods. The RAM 320 operates by these address, data, and read / write signals, and the output 321 of the RAM 320 becomes the selector output 231 via the selector 230. The output 231 is taken in by the tester and collated with the expected value to judge the quality of the RAM 320.

The RAM test pattern generating function mounted on the LSI tester is prepared as an option.
It is LS that all LSI testers have this function.
There was a problem that became a heavy burden for the I maker. In addition, at present, some LSI testers are provided with this function for a screening test, and there is a problem that it is difficult to significantly increase the screening quantity.

In order to solve such a problem, a measure has been devised to incorporate a function for generating a RAM test pattern and a function for comparing a RAM output result with an expected value into an LSI chip.

The operation will be described with reference to a circuit example shown in FIG. now,
The description will be given assuming that the RAM test state is set by the RAM test state setting signal 119. Therefore, in the selector 300, the address / data signal 115 and read / read
The write signal 116 is selected, and the selector 230 selects the comparison result 411. The clock signal 102 and the reset signal 111 are connected to the test signal generation circuit 110. The reset signal 111 initializes the test signal generation circuit 110. The clock signal 102 automatically generates a test pattern and an address for testing the RAM, and outputs the address / data signal 115. At the same time, a signal for controlling the read / write operation of the RAM is automatically generated and the read / write signal 116 is output. As for the RAM test pattern contents generated by the test signal generating circuit, various test patterns are generated as in the conventional example shown in FIG. Further, the expected value 112 which will be output from the RAM 320 in the read state is also output and input to the comparison circuit 410. RAM output 3
21 is input to the user logic circuit 200 and the comparison circuit 410. The comparison circuit 410 then calculates the expected value 112 and RA.
The M output 321 is compared and the comparison result 411 is output. The comparison result 411 becomes the external output signal 231 via the selector 230. Therefore, the RAM operation test can be performed by inputting the reset signal 111, the clock signal 102, and the RAM test state setting signal 119 from the LSI tester and observing the external output signal 231. Therefore, it became possible to perform a RAM selection test without being restricted by the function of the tester.

[0007]

However, FIG. 5 and FIG.
In the prior art, since a test-dedicated input terminal using an external input terminal is required for setting the RAM test state, there is a problem that a test pin cannot be prepared and a RAM unit test cannot be performed depending on product specifications.

Therefore, the present invention solves such a problem, and an object of the present invention is to easily perform a RAM operation test without providing a test-dedicated input terminal.
It is to improve the operation quality of SI and to realize product design with a high degree of freedom.

[0009]

[Means for Solving the Problems]

(Means 1) Randomly accessible memory (hereinafter RA
As a RAM test circuit of a semiconductor integrated circuit that realizes a predetermined function by a combination of M) and a user logic circuit, RA is generated by a clock signal input from the outside.
RAM test signal generator and RAM for generating M test data, address and access control signal
A RAM test circuit comprising a comparison circuit for comparing an output with an expected value, comprising an inverting logic element having a predetermined delay, and an output of the inverting logic element and an input terminal of the inverting logic element and the RAM test signal generation. It is characterized in that it is connected to a clock signal input terminal of the device.

(Means 2) It is characterized in that it is provided with a circuit configuration for outputting a RAM test state discrimination signal from the RAM test signal generator described in means 1 and connecting it to the inverting logic element described in means 1.

(Means 3) A non-match result holding circuit having a function of holding the output of the comparison circuit described in the means 1 is provided, and the output of the non-match result holding circuit is connected to the user logic circuit described in the means 1. Is characterized by.

(Means 4) The RAM test data and the address and access control signal described in the means 1, and the RAM operation data and the address and access control signal output from the logic circuit to realize a predetermined function,
Select by the RAM test state discrimination signal described in means 2,
It is characterized by including a circuit connected to the RAM.

[0013]

The means 1, means 3, and means 4 automatically generate the RAM test pattern and the expected value and compare the expected value with the RAM output. If a mismatch occurs, the mismatch occurrence signal is held and the held signal is used. By combining with the user logic circuit, it becomes possible to test the RAM alone without providing a test-dedicated input pin.

In the means 2, the self-oscillation is stopped at the end of the RAM test by the RAM test state discrimination signal output from the RAM test signal generating device, so that it is possible to suppress unnecessary current consumption during the normal use state. Becomes

[0015]

1 to 4 show a RAM according to the present invention.
An example of a test circuit is shown. FIG. 1 shows a RAM according to the present invention.
Block diagram of the test circuit. FIG. 2 is a waveform diagram for explaining the operation of FIG. FIG. 3 is an example of a clock generation circuit and an operation waveform diagram. FIG. 4 is an example of a mismatch result holding circuit, an example of a combination circuit of a mismatch result holding signal and a user logic circuit, and an operation waveform diagram.

In FIG. 1, the reset signal 111 is the test signal generation circuit 110 and the mismatch result holding circuit 420.
Control the initialization of the circuit and the start of the RAM test. As an input source of the reset signal 111, a system reset signal for initializing the user logic circuit, a power-on reset circuit output for generating a reset signal when the power is turned on, or the like is used. The clock signal 102 output from the clock generation circuit 100 is the test signal generation circuit 110.
Is input to The clock 102 causes the test signal generation circuit 110 to operate to generate addresses and data necessary for the RAM test operation and signals necessary for RAM control such as read / write. Further, the expected value 112 necessary for confirming the RAM operation and the comparison enable signal 113 for permitting the comparison between the expected value 112 and the RAM output 321 are generated.

A RAM test address / data signal 115 output from the test signal generation circuit 110 and an address / data signal 205 which is a signal for the user logic circuit 200 to access the RAM 320 in the normal operation state.
Are input to the selector 300, and selection of both signals is performed by the RAM test state determination signal 114 output from the test signal generation circuit 110. Similarly, RAM test read / write control and chip select signal 116
In the normal operation state, the user logic circuit 200 is RAM3.
A read / write signal 206 which is a signal for accessing 20 is also input to the selector 300, and both signals are selected by the RAM test state determination signal 114.

In the RAM test state, the RAM test address / data signal 115 and the RAM test read / write control / chip select signal 116 are selected, and the address / data signal 305, read / write control and chip select signal are selected. It becomes 306 and operates the RAM 320. When the RAM test ends, the output of the RAM test state determination signal 114 changes and the selector 300 selects the signal from the user logic circuit 200. That is R
After the AM test is completed, the user logic circuit 200 is automatically turned to R
It is set to the normal operation state for accessing the AM 320.
When the comparison circuit 410 is enabled by the comparison enable signal 113, the expected value 112 and the RAM output 3
21 and outputs the comparison result 411. The comparison result 411 is input to the mismatch result holding circuit 420, and when the mismatch result is output, the mismatch occurrence state is held. That is, the RAM test fail result is held. Then, the mismatch result holding signal 421 is input to the user logic circuit 200 and forms a part of the user logic circuit.

Next, the RAM test operation will be described with reference to the operation explanation waveform chart of FIG. In this operation example, an operation in a test mode in which specific data is written to the RAM and immediately read to compare with an expected value will be described. The operation of the RAM used this time will be described on the assumption that the read / write signal is a write operation when it is "1" and a read operation when it is "0".

First, during the operation step T0, "0" is input to the reset signal 111 and then it is changed from "0" to "1" to initialize the test signal generating circuit 110 and RA
Start M test. At the same time, the RAM test state determination signal becomes "1", indicating that the RAM test state is set. This signal is "1" to "0" after RAM test.
Changes to A circuit example of the clock generation circuit 100 that outputs the clock 102 is shown in FIG. The output signal of the delay element 160 and the RAM test status display signal 114 are input to the NAND element 161. Then, while the RAM test status display signal 114 is "1", the output of the delay element 160 is received and the inverted signal is output. Delay element 16
When the delay value of 0 is D, the cycle of the oscillation clock 102 is twice D. Since this delay value determines the clock frequency, the optimum delay value can be set according to the operation speed of the RAM to be tested. Then, when the RAM test status display signal 114 changes to "0" which means the end of the RAM test, the output of the NAND element 161 is fixed to "1" and the oscillation is stopped, so that generation of useless oscillation current can be prevented. it can.

At step T1, the clock 102 rises and the value "ad1" is set in the addresses 115 and 305, and "data" is set in the write data 115 and 305.
The value "1" is set. The clock 1 is set at step T2.
The read / write signal 116 is synchronized with the falling edge of 02.
・ High pulse is output from 306, and it is sent to RAM320.
"data1" is written. At step T3, the clock 102 rises, the read / write signal becomes "0" in synchronization with it, and the data written at the "ad1" address is read. At step T4, the clock 102 falls and comparison is performed. A high pulse is output from the enable signal 113, and the expected value 112 and the RAM output 321 are compared by the comparison circuit 410. In step 4, RA
Since the M output 321 and the expected value 112 are equal, the comparison result 411 becomes “1”, and the mismatch result holding circuit 420 does not operate.

FIG. 4 shows an example of a combination circuit of the mismatch result holding circuit 420, the mismatch result holding signal 421, and the user logic circuit 200. The mismatch result holding circuit 420 is NA
An RS latch is configured by using two ND elements 450. Then, the reset input 111 initializes the latch data and holds "1". The held data “1” means that there is no mismatch, that is, the RAM test has passed. The comparison result 411 is another input signal of the RS latch, and when the comparison result 411 becomes "0" which means a mismatch, the mismatch result holding circuit 420 holds "0" which means a mismatch occurrence. To do. This held data does not change unless "0" is input to the reset signal 111. The mismatch result holding signal 421 is ANDed with one signal 252 of the signals forming the user logic circuit 200 by the AND element 250, and the AND
The output is 253. While the mismatch result hold signal is "1",
That is, while the RAM test passes, the user signal 252 remains the AND output 253 and the user circuit operates normally. However, once the RAM test does not match or fails, the user signal 252
The AND output 253 is fixed to "0" regardless of the change of. That is, the pulse to be output disappears as shown by the dotted line in FIG. As a result, the user circuit cannot operate normally.

The test for one address is completed in four steps T1 to T4. The test method this time is 1
Since writing and reading are continuously performed with respect to one address, write data and expected value data are set at the same timing. In the step of T5, T1
Similarly to the operation at the time of, the data of the addresses 115 and 305 are set to "ad2" in synchronization with the rising edge of the clock 102, and the write data 115 and 305 are also "data2".
Is set. The operation in steps T5 to T8 is the same as that described in steps T1 to T4.
The operations from T9 to T12 are similar, but it is assumed that a mismatch occurs between the expected value 112 and the RAM output 321 in step T12. The comparison result 411 outputs "0" while the comparison enable signal 113 is "1" because of the non-coincidence. Then, this "0" signal is applied to the mismatch result holding circuit 42.
0 is received, and the mismatch holding result 421 is changed from "1" to "0".
Changes to As a result, a state in which the user logic circuit 200 cannot operate normally can be forcibly created, and a result different from the normal operation state is output. LS in this state
When the function test by the I tester is performed, it fails and is judged as a defective product. That is, it is possible to judge and select a defective RAM by only performing a normal function test.

[0024]

According to the inventions described in Means 1, Means 3 and 4, the RAM test pattern and the expected value are automatically generated and the expected value and the RAM output are compared with each other. If a mismatch occurs, a mismatch occurs. By holding the signal and combining the held signal with the user logic circuit, it is possible to test the RAM alone without providing a test-dedicated input pin, and it is possible to realize a highly flexible product design. .

According to the second aspect of the invention, the self-oscillation is stopped at the end of the RAM test by the RAM test state discrimination signal output from the RAM test signal generating device, so that it is generated unnecessarily during the normal operation state. It is possible to suppress the consumption current and the oscillation noise, and it is possible to realize the low consumption current of the chip and the stable operation of the circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a waveform chart for explaining the operation of the embodiment of the present invention.

FIG. 3 is a clock generation circuit diagram and an operation waveform diagram showing an embodiment of the present invention.

FIG. 4 is a mismatch result holding circuit diagram and an operation waveform diagram showing an embodiment of the present invention.

FIG. 5 is a circuit diagram showing a conventional technique.

FIG. 6 is a circuit diagram showing a conventional technique.

[Explanation of symbols]

100 ... Clock generation circuit 102 ... Clock signal 111 ... Reset signal 110 ... Test signal generation circuit 114 ... RAM test status display signal 119 ... ..Test state setting signal 200 ... User logic circuit 115,205,305 ... Address, data signal 116,206,306 ... Read, write, chip select signal 300,230 ... Selector 320 ... RAM 321 ... RAM output 410 ... Comparison circuit 411 ... Comparison result 112 ... Expected value 113 ... Comparison enable signal 420 ... mismatch result holding circuit 421 ... mismatch result holding signal 161, 450 ... NAND element 250 ... AND element 60 ..... delay element

Claims (4)

[Claims] 1. Randomly accessible memory (hereinafter referred to as R
As a RAM test circuit of a semiconductor integrated circuit that realizes a predetermined function by a combination of (described as AM) and a user logic circuit, R is generated by a clock signal input from the outside.
RAM test signal generator for generating AM test data and address and access control signals, and RA
RAM composed of a comparison circuit for comparing M output with an expected value
The test circuit includes an inverting logic element having a predetermined delay, and an output of the inverting logic element is connected to an input terminal of the inverting logic element and a clock signal input terminal of the RAM test signal generator. A semiconductor device characterized by: 2. A semiconductor device comprising a circuit configuration for outputting a RAM test state determination signal from the RAM test signal generation device according to claim 1 and connecting it to the inverting logic element according to claim 1. 3. A structure comprising a mismatch result holding circuit having a function of holding the output of the comparison circuit according to claim 1, and connecting the output of the mismatch result holding circuit to the user logic circuit according to claim 1. A semiconductor device characterized by: 4. The RAM test data and address and access control signal according to claim 1, and the RAM operation data and address and access control signal output from the logic circuit to realize a predetermined function. Item 2
RAM selected by the RAM test status determination signal
A semiconductor device comprising a circuit connected to the.