JPH09191074A - Memory module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To meet the requirements of design specification changes of a memory module flexibly by a method wherein terminal electrodes are so arranged as to be able to change functions in accordance with the connection states of SMT-type conducting units with which the terminal electrodes of memories and outer terminals are electrically connected to each other. SOLUTION: One jumper chip 4 is mounted between a land 12c and a land 12d with solder so as to correspond to a memory module with an access time of 85ns. Two jumper chips 4 are mounted to make lands 12a and 12b and lands 12c and 12d electrically continuous with each other so as to correspond to a memory module with an access time of 100ns. No jumper chip 4 is mounted and both module terminals 5a and 5b are NC so as to correspond to a module with an access time of 120ns. With this constitution, the manufacturing lead time of a memory module can be shortened significantly and, further, the design cost, the manufacturing cost, etc., can be reduced and an economical memory module can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board and a semiconductor device technology using the same, and more particularly to a technology effective when applied to a memory module.

[0002]

2. Description of the Related Art In the case of manufacturing a semiconductor device such as a memory module, it is common to individually form a wiring board constituting the semiconductor device according to the use and purpose of the module.

A module having electronic components mounted on a wiring board is disclosed in, for example, Japanese Patent Application Laid-Open No. 62-195.
There is a description in Japanese Patent Application Publication No. 159, which describes a technique for improving the bonding strength of a module terminal bonded to a wiring board.

[0004]

However, the present inventor has found that the above-mentioned memory module technology has the following problems.

That is, in this type of memory module, after a product is completed, it is difficult to change a wiring route based on a change in the specification of the product. In each case, it is necessary to re-create the wiring board, and there is a problem that the efficiency of manufacturing the wiring board for the memory module cannot be improved.

For example, a memory module has two specifications depending on the data input / output method of each memory mounted on a module wiring board.

One is a specification in which the input terminal and the output terminal of each memory are led out as one common external terminal, and the other is that the input terminal and the output terminal of each memory are taken as separate external terminals. It is a specification to draw out.

[0008] However, when a product of one specification is manufactured and the manufacturing is changed to a product of the other specification,
In each of these specifications, the wiring route of the wiring board is slightly different, so it is necessary to remanufacture a dedicated wiring board according to the changed specifications from the beginning, and the wiring board is wasted, The money, time and labor spent on manufacturing can be wasted.

Such a problem is also caused by a change in the word / bit configuration (specification) of the entire memory module. Each time the word / bit configuration is changed, the problem is caused according to the changed specification. The dedicated wiring board must be remanufactured from the beginning, and the wiring board may be wasted, or the money, time, and labor spent for the manufacturing may be wasted.

As described above, in the above-described memory module technology, it takes a long time to complete a product, and there is a problem that money, time and labor are wasted, and the product cost of the product increases.

An object of the present invention is to provide a technique capable of flexibly responding to a change in design specifications of a memory module.

It is another object of the present invention to provide a technique capable of improving the manufacturing efficiency of a memory module.

Another object of the present invention is to provide a technique capable of reducing the manufacturing cost of a memory module.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0015]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

A memory module according to the present invention has at least two or more memories mounted on a wiring board surface, and has wiring for electrically connecting the mounted memories to each other, for electrical connection to an external device. A memory module comprising a plurality of external terminals arranged on the wiring board surface,
A terminal electrode electrically connected to an input terminal of the memory, a terminal electrode electrically connected to an output terminal of the memory, and a terminal electrode electrically connected to the external terminal are arranged on the wiring board. Depending on the connection state of the surface-mount type conductive means for electrically connecting these terminal electrodes, data input and output in each memory are performed by a common external terminal or by independent external terminals. The terminal electrodes are arranged so as to be changeable.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings. (Note that components having the same functions are denoted by the same reference numerals throughout the drawings for describing the embodiments.) The description of the repetition is omitted).

(Embodiment 1) FIG. 1 is a plan view showing a main surface of a wiring board according to an embodiment of the present invention, FIG.
FIG. 3C is a plan view of a main part of the wiring board showing a mounting state of the conduction means according to the access time, FIGS. 3A to 3D are plan views of wiring layers constituting the wiring board, and FIG. a),
FIG. 5B is a diagram showing a structure of a jumper chip as a conducting means, and FIG. 5 is a plan view showing a main surface of a memory module using the wiring board.

The memory module 1a according to the first embodiment shown in FIG. 5 has, for example, two access times of 100 ns.
56K × 36-bit dynamic RAM (DRA
M) Module. The access time is based on, for example, a RAS (Row Address Strobe) signal.

On the main surface of the wiring board 2a constituting the memory module 1a, two types of large and small semiconductor memories 3a and 3b, which are electronic components, are arranged on the lower surface side of these semiconductor memories 3a and 3b, although not shown. A bypass capacitor, which is also an electronic component, and a jumper chip 4, which is a conducting means, are mounted.

On one long side of the wiring board 2a, for example, 72 module terminals (external terminals) 5 are arranged along the longitudinal direction of the wiring board 2a. The width of each module terminal 5 is, for example, about 1.04 mm, and the interval between adjacent module terminals 5, 5 is, for example, 1.27 m.
m.

In the first embodiment, of the module terminals 5, for example, the 69th and 70th module terminals 5a and 5b from the left are configured as function identification module terminals for identifying access time. Have been.

The large semiconductor memory 3a described above is mounted, for example, by arranging eight in the longitudinal direction of the wiring board 2a, and constitutes, for example, SOJ (Small Outl).
ineJ-lead) type package has 256K x 4 inside
A bit configuration DRAM chip (not shown) is accommodated.

Also, two small semiconductor memories 3b are mounted on both ends of the surface of the wiring board 2a, respectively.
Constituting this, for example, PLCC (Plastic Leaded Ch
A 256 × 1 bit DRAM chip (not shown) is accommodated inside a package of the (ip carrier) type.

The distance between the lead terminals of the semiconductor memories 3a and 3a and the distance between the lead terminals of the semiconductor memories 3a and 3b are, for example, about 0.2 mm.

The bypass capacitor (not shown) is, for example, a 0.2 μF ceramic capacitor. From the viewpoint of preventing noise and the like, the bypass capacitor is connected between the power supply voltage (Vcc) terminal and the GND terminal of each of the semiconductor memories 3a and 3b. Is electrically connected to

FIGS. 4A and 4B show a jumper chip 4 used in the first embodiment. FIG. 4B is a cross-sectional view taken along the line XX ′ of FIG. The jumper chip 4 is, for example, a chip body substrate 6 made of ceramic.
A primary electrode 7c made of a conductive metal (for example, a palladium-silver-based thick film) is printed and formed on both ends. A conductor 8a (for example, silver) is printed thereon and electrically connected. The protective glass 8b is formed on the conductor. Further, on the primary electrode 7c, a secondary electrode 7b (for example, nickel, solder, etc.), an external electrode 7a
(For example, tin-lead, solder, etc.).

The above-mentioned wiring board 2a is made of, for example, glass epoxy resin, and has, for example, a four-layer wiring structure as shown in FIGS. 3 (a) to 3 (d). In forming such a multilayer wiring board 2a, first, a copper foil is pressed on the entire surface of a plate-like member made of glass epoxy resin, and then an inner layer pattern 9 is formed by etching, and the plate-like member is laminated and pressed. Next, after forming a through hole 10 for conducting between the multilayer wiring layers by drilling or punching,
It is obtained by through-hole plating and pattern formation on the surface.

As described above, the inner layer pattern 9 is mainly formed on the wiring layers on the main surface side (FIG. 3A) and the rear surface side (FIG. 3D) of the wiring board 2a.

The inner two layers of the wiring board 2a (FIG. 3)
Of (b) and (c)), one layer is dedicated to GND wiring from the viewpoint of preventing noise and the like, and the other layer is used as much as possible for Vcc wiring.

Then, as shown in FIG. 1, the wiring board 2a
A plurality of lands 11a for mounting the above-mentioned semiconductor memories 3a and 3b are arranged on the main surface so as to correspond to the lead terminals of each of the semiconductor memories 3a and 3b. Multiple lands 1
1b is arranged. The land 11a is electrically connected to the module terminal 5 via the above-described inner layer pattern 9 (FIGS. 3A and 3D).

In the first embodiment, the independent lands 1 are located on the right side of the main surface of the wiring board 2a, below the lands 11a on which the small semiconductor memory 3b is mounted.
2a, 12b and lands 12c,
12d are arranged.

The lands 12a and the lands 12c are electrically connected to module terminals 5a and 5b, which are electrodes for identifying an access time, via wirings 13 and 14, respectively. Land 12b and land 1
2 d is electrically connected to the GND electrode via the through hole 10. The dimensions of the wiring board 2a are 2
It is about 5.4 × 108 mm.

By the way, conventionally, in order to identify the access time, for example, two predetermined module terminals of the memory module are used as terminals for identifying the access time, and when these terminals are at the NC and GND potential, 85 ns, 100 ns when both are at GND potential, 120 when both are at NC
ns was determined in advance.

Therefore, conventionally, even if the circuit function of the memory module is the same, each time the access time is changed, for example, between 85 ns and 120 ns, only the wiring of the module terminal for identification is changed. In order to do so, a different and separate wiring board had to be created.

However, in the wiring board 2a of the first embodiment, as shown in FIG. 2A, the jumper chip 4 is mounted between the lands 12c and the lands 12d by soldering. By conducting between 12d, the module terminal 5b can be set to the GND potential.

Therefore, according to FIG. 2A, since the module terminals 5a and 5b can be set to the NC and GND potentials, it is possible to correspond to a memory module having an access time of 85 ns.

As shown in FIG. 2B, the wiring board 2a is electrically connected between the lands 12a and 12b and between the lands 12c and 12d by mounting the jumper chips 4 and 4, and the module terminals 5a and 5b Can be set to the GND potential, so that the circuit function can correspond to the memory module 1a having an access time of 100 ns.

Further, as shown in FIG. 2 (c), since the jumper chip 4 is not mounted on the wiring board 2a, both the module terminals 5a and 5b can be set to NC, so that the memory having an access time of 120 ns can be obtained.・ It can correspond to a module.

That is, the wiring board 2a of the first embodiment
By selectively attaching and detaching jumper chips,
The same three types of access time changes can be handled by the same wiring board 2a.

As described above, according to the present embodiment, even when the access time of the memory module 1a is variously changed, it is possible to cope with this by selectively attaching and detaching the jumper chip 4. The wiring board 2a can be standardized.

As a result, the manufacturing time of the memory module 1a can be greatly reduced, the design cost and the manufacturing cost thereof can be reduced, and the memory module 1a can be provided at low cost.

(Embodiment 2) FIGS. 6A and 6B are plan views showing a main surface and a back surface of a memory module according to another embodiment of the present invention, and FIG. (B) is a side view of the memory module shown in (b).

The memory module 1b, which is a memory module according to the second embodiment shown in FIGS. 6A and 6B and FIG.
It is an M module.

The main surface (FIG. 6 (a)) and the back surface (FIG. 6 (b)) of the wiring board 2b constituting the memory module 1b
, Semiconductor memories 3a and 3b are mounted in the same manner as in the first embodiment.

In the memory module 1b, during data access, the semiconductor memories 3a and 3b on the other side do not operate while the semiconductor memories 3a and 3b on the one side operate.

Therefore, the bypass capacitor described in the first embodiment is different from the semiconductor memory 3a, 3a, or the semiconductor memory 3b, on the main surface side and the rear surface side of the wiring board 2b.
3b.

In the second embodiment, of the module terminals 5, for example, the 69th and 70th module terminals 5a and 5b from the left are used to identify the mounting method of the semiconductor memories 3a and 3b, for example. Terminal.

Conventionally, in order to identify the mounting method, similarly to the access time described in the first embodiment, for example, two predetermined terminals of the module terminal are used as identification terminals of the mounting method, and these terminals are used as NC terminals. , When GND potential, single-sided mounting,
In both cases, when the potential is the GND potential, it is determined by such a method as double-sided mounting.

Therefore, conventionally, every time the mounting method is changed, a wiring board must be created from the beginning only to change the wiring of the module terminal portion for identification.

However, in the wiring board 2b of the second embodiment, as shown in FIGS. 2A to 2C of the first embodiment, even after the wiring board 2b is formed, the jumper chip Depending on the mounting method of module terminal 5, module terminal 5
Since a and 5b can be set to the NC and GND potentials or both can be set to the GND potential, the same wiring board 2b
Can respond to the change in the mounting method identified above.

As described above, according to the second embodiment, even if the mounting method of the semiconductor memories 3a and 3b is changed to single-sided mounting or double-sided mounting, the same wiring board 2b can cope with the change. .

(Embodiment 3) FIG. 8 is a circuit block diagram showing a circuit configuration of a memory module according to still another embodiment of the present invention, and FIGS. FIG. 9 is a plan view of a main part of the wiring board shown in FIG.

In the third embodiment, for simplicity of description, as shown in FIG.
The memory module 1c will be described using the DRAMs 15 to 18.

The CAS (Column A) of each of the DRAMs 15 to 18
The (ddress strobe) signal terminal is electrically connected to the module terminal 5c formed on the wiring board 2c via the control signal wiring 19a, so that a CAS signal is externally supplied.

The RAS (Ro) of each of the DRAMs 15 to 18 is
w Address Strobe) The signal terminal is electrically connected to the module terminal 5d via the control signal wiring 19b, so that an external RAS signal is supplied.

Further, the WE (Wri) of each of the DRAMs 15 to 18 is
The te enable) terminal is electrically connected to the module terminal 5e via the control signal wiring 19c, so that writing or reading of data is externally controlled.

The access of data of the DRAMs 15 to 18 is controlled by the RAS and CAS signals and the WE signal.

The address terminals of the DRAMs 15 to 18 are connected to the module terminals 5 through the address signal lines 20.
and is electrically connected to the address f so that the address of the memory cell is designated from the outside. At the time of address designation, for example, a row and column address is input from a predetermined number of the same module terminals 5f by a multiplex method.

Each of the DRAMs 15 to 18 of the memory module 1c according to the third embodiment has a data input terminal Din
And a data output terminal Dout.

The data input terminal Din is electrically connected to the module terminal 5 g via the data line 21, and the mounting area A for mounting the jumper chip 4 described in the first and second embodiments via the wiring 22. (See FIG. 9). The lands (input terminal electrodes) 12e are electrically connected.

The data output terminal Dout is connected to the wiring 23
Is electrically connected to a land (output terminal electrode) 12f formed independently of the land 12e.

The land (external terminal electrode) 12g formed in the mounting area A electrically independently of the lands 12e and 12f is electrically connected to the module terminal 5h via the wiring 24. I have.

Next, the operation of the third embodiment will be described with reference to FIGS. 8 and 9 (a) to 9 (c).

FIG. 9 shows a land 12e in the mounting area A.
12 to 12g show a state in which the jumper chip 4 described in the first and second embodiments is not mounted, the data output terminal Dout is in an open state, and the module terminal 5h is in an NC state.

Here, as shown in FIG. 9B, when the lands 12f and 12g are electrically connected by mounting the jumper chip 4 on the lands 12f and 12g,
The data output terminal Dout and the module terminal 5h are electrically connected.

That is, the module terminal 5h is a terminal for data output, and the module terminal 5g is a terminal for data input. Therefore, each of the DRAMs 15-1
8, the data input / output (I / O) method is an I / O
It becomes a separate system.

On the other hand, as shown in FIG.
When the lands 12f and 12e are electrically connected by mounting the jumper chip 4 on the 2f and 12e, the data input terminal Din and the data output terminal Dout are electrically connected.

That is, the module terminal 5g is connected to the I / O
It becomes a common electrode. At this time, the module terminal 5h
Becomes NC. Therefore, in each of the DRAMs 15 to 18, the data I / O method is the I / O common method.

As described above, according to the third embodiment, the data I of each of the DRAMs 15 to 18 of the memory module 1c is
Even if the / O method is changed to the I / O common method or the I / O separate method, the same wiring board 2c can cope with the change.

(Embodiment 4) FIG. 10 is a circuit block diagram showing a circuit configuration of a memory module according to still another embodiment of the present invention. FIGS. 11 and 12 show conduction according to a word / bit configuration. FIG. 11 is a circuit block diagram of the memory module shown in FIG. 10 showing a mounting state of the means.

Each of the DRAMs 15 to 18 in the memory module 1d according to the fourth embodiment shown in FIG. 10 has, for example, a 1M × 1 bit configuration.
Selection of 15 to 18 is controlled by the RAS signal.

In the fourth embodiment, lands 12h to 12m electrically independent from each other are arranged in mounting area A. The land 12h in each mounting area A is connected to a control signal wiring 19b for electrically connecting the RAS signal terminal of the DRAM 15 and the module terminal 5d via the wiring 25.
Is electrically connected to

The lands 12i in each mounting area A
Are electrically connected to the RAS signal terminals of the DRAMs 16 to 18. Land 12j in each mounting area A,
The lands 12k are electrically connected to the module terminals 5i and 5j, respectively.

Further, the lands 12 in each mounting area A
l is a data input terminal Din and a data output terminal Dout of the DRAM 15 and a module terminal 5
k is electrically connected to a wiring 27 that electrically connects k.

The land 12 m in each mounting area A
Are electrically connected to the data input terminal Din and the data output terminal Dout of each of the DRAMs 16 to 18.

When such a memory module 1d is used in a 1M × 4 bit configuration, for example, the lands 12h and lands 12i in each mounting area A are electrically connected by the jumper chip 4 as shown in FIG. , The RAS signals of the DRAMs 15 to 18 are made common.

At the same time, the lands 12k and the lands 12m in each mounting area A are connected to the jumper chip 4.
And the I / O signal is input / output from / to each of the DRAMs 15-18.

That is, when accessing data, each D
The RAMs 15 to 18 operate simultaneously in synchronization with the RAS signal input from the module terminal 5d, and
To 18 input / output 4-bit data of I / O.0 to I / O.3, respectively.

On the other hand, when the memory module 1d is used, for example, in a 4M × 1 bit configuration, as shown in FIG. 12, the lands 12i and the lands 12j in each mounting area A are made conductive by the jumper chip 4, and each DRA
M15 to M18 can be individually selected by RAS0 to RAS3 signals.

Further, the lands 12l and the lands 12m in each mounting area A are also connected to the jumper chip 4.
To make the I / O signals of the DRAMs 15 to 18 input / output only from the module terminal 5k.

That is, when accessing data, R
A predetermined DRAM among the DRAMs 15 to 18 is selected by the AS0 to RAS3 signals, and the selected DRA is selected.
1-bit data of I / O is input / output from M.

As described above, according to the fourth embodiment, the word / bit configuration of the memory module 1d is, for example,
Even if the configuration is changed to a 4M × 1 bit configuration or a 1M × 4 bit configuration, the same wiring board 2d can cope with the change.

(Embodiment 5) FIG. 13 is a circuit block diagram showing a circuit configuration of a memory module according to still another embodiment of the present invention, and FIG. 14 is a diagram showing a mounting state of the conducting means at the time of defect repair. FIG. 14 is a circuit block diagram of the memory module shown in FIG.

The wiring board 2e of the memory module 1e according to the fifth embodiment shown in FIG.
When a failure occurs in any of the RAMs 15 to 18, a DRAM for mounting an alternative element for the failed DRAM
A mounting area B is provided. The DRAM mounting area B may be provided on either the main surface or the back surface of the wiring board 2e.

In the DRAM mounting area B, a CAS signal land 28a, a RAS signal land 28b, a WE signal land 28c, an address designation land 29, and data input / output lands 30a and 30b are arranged.

The land 28b for the RAS signal is
The lands 12 of each of the mounting areas A1 to A4 via the wiring 31
p and the module terminal 5d.

The data input lands 30 described above are used.
a and the data output land 30b are electrically connected to the lands 12q of the mounting areas A1 to A4 via the wiring 32.

By the way, in the memory module 1d of the fifth embodiment, for example, the defect remedy technique of the memory module 1d when the DRAM 18 fails is described in the fourteenth embodiment.
This is described below with reference to the drawings.

That is, the redundant DRAM 33 for performing a normal circuit operation is mounted in the DRAM mounting area B, and the lands 12i and 12p and the lands 12k and 12m in the mounting areas A1 to A3 are electrically connected by the jumper chip 4. And the land 12k in the mounting area A4
And the land 12q are electrically connected by the jumper chip 4.

As a result, the failed DRAM 18 becomes electrically independent from the circuit system of the memory module 1d, and the redundant DRAM 33 is electrically connected to the circuit system of the memory module 1d instead.

As described above, according to the fifth embodiment, the failed DRAM 18 and the redundant DRAM 33 can be easily replaced on the wiring system by the mounting method of the jumper chip 4 without removing the failed DRAM 18.

Therefore, even if the DRAMs 15 to 18 in the memory module 1d are mounted at high density, highly reliable defect relief can be performed, and a decrease in the yield of the memory module 1d due to the defect relief is reliably prevented. be able to.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof. Needless to say,

For example, in the first embodiment, the access time has been described as an identification target, and in the second embodiment, the mounting method of the semiconductor memory has been described. However, the present invention is not limited to this. It can be applied to other identification of products.

In the first to fifth embodiments,
The case where the conducting means is a jumper chip and the case where the wiring path is selectively switched according to the mounting method of the jumper chip has been described. However, the present invention is not limited to this. An integrated circuit chip may be used to selectively switch between conduction and non-conduction between predetermined lands by a switching operation of a logic circuit inside the integrated circuit chip.

In the first to fifth embodiments,
Access time identification, mounting method identification, I /
The conversion of the O system, the conversion of the word / bit configuration, and the redundant configuration have been described. However, the present invention is not limited thereto. It can be applied in different cases.

In the first to fifth embodiments,
Each of the wiring path conversion techniques has been described separately. However, the present invention is not limited to this. For example, a combination of the first and second embodiments or a combination of the third and fourth embodiments may be used. Or Embodiments 1 to 5
Can be realized on the same wiring board.

[0099]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the memory module of the present invention, the data input / output method of the memory can be changed by the surface mounting type conduction means. That is, the memory
It is possible to flexibly respond to changes in module design specifications.

(2) According to the above (1), it is possible to eliminate the necessity of rebuilding the wiring board for the module from the beginning according to the change of the design specification of the memory module, thereby improving the manufacturing efficiency of the memory module. The manufacturing time of the memory module can be greatly reduced.

(3) By the above (1) and (2), it is possible to eliminate the waste of money, time and labor due to remaking of the wiring board for the module, so that the manufacturing cost of the memory module is significantly reduced. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a plan view showing a main surface of a wiring board according to an embodiment of the present invention.

FIGS. 2A to 2C are plan views of a main part of a wiring board showing a mounting state of a conduction unit according to an access time.

FIGS. 3A to 3D are plan views of respective wiring layers constituting the wiring board.

FIG. 4A is a plan view showing a structure of a jumper chip as a conducting means, and FIG. 4B is a cross-sectional view taken along line XX ′ of FIG.

FIG. 5 is a plan view showing a main surface of a memory module using the wiring board.

FIGS. 6A and 6B are plan views showing a main surface and a back surface of a memory module according to another embodiment of the present invention.

FIG. 7 is a side view of the memory module shown in FIGS. 6 (a) and 6 (b).

FIG. 8 shows a memory according to still another embodiment of the present invention.
FIG. 2 is a circuit block diagram illustrating a circuit configuration of a module.

9 (a) to 9 (c) are plan views of a main part of the wiring board shown in FIG. 8, showing a mounting state of a conduction unit according to an input / output method.

FIG. 10 is a circuit block diagram showing a circuit configuration of a memory module according to still another embodiment of the present invention.

FIG. 11 is a circuit block diagram of the memory module shown in FIG. 10 showing a mounting state of a conduction unit according to a word / bit configuration.

FIG. 12 is a circuit block diagram of the memory module shown in FIG. 10 showing a mounting state of a conduction unit according to a word / bit configuration.

FIG. 13 is a circuit block diagram showing a circuit configuration of a memory module according to still another embodiment of the present invention.

FIG. 14 is a circuit block diagram of the memory module shown in FIG. 13 showing a mounting state of a conduction unit at the time of defect relief.

[Explanation of symbols]

1a-1e Memory module 2a-2e Wiring board 3a, 3b Semiconductor memory 4 Jumper chip (conduction means) 5-5k Module terminal 6 Chip body 7a, 7b Chip electrode 8 Conductor 9 Inner layer pattern 10 Through hole 11a, 11b Land 12a- 12d, 12h to 12n, 12P, 12q Land (terminal electrode) 12e Land (input terminal electrode) 12f Land (output terminal electrode) 12g Land (external terminal electrode) 13, 14, 21 to 27, 31 , 32 wiring 15-18 DRAM 19a-19c control signal wiring 20 address signal wiring 28a CAS signal land 28b RAS signal land 28c WE signal land 29 address specifying land 30a data input land 30b data output land 33 redundancy DRAM

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Osamu Sakai 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi, Ltd. Musashi factory

Claims (3)

[Claims] At least two or more memories are mounted on a wiring board surface, and wiring is provided for electrically connecting the mounted memories to each other. The wiring is provided on the wiring board surface for electrical connection with an external device. A memory module comprising a plurality of external terminals arranged in a terminal electrode electrically connected to an input terminal of the memory; a terminal electrode electrically connected to an output terminal of the memory; A terminal electrode electrically connected to an external terminal is provided on the wiring board, and input and output of data in each memory are performed according to a connection state of a surface mounting type conducting means for electrically connecting the terminal electrodes. Characterized in that the terminal electrodes are arranged so that it is possible to change whether the operation is performed using a common external terminal or an independent external terminal. 2. At least two or more memories are mounted on a wiring board surface, and wiring is provided for electrically connecting the mounted memories to each other. The wiring is provided on the wiring board surface for electrical connection with an external device. A memory module comprising a plurality of external terminals arranged in the memory module, wherein each input terminal of the at least two or more memories is electrically connected to the external terminal and an input terminal electrode on a wiring board; At least 2
The output terminals of each of the above memories are not electrically connected to the external terminals, but are electrically connected to output terminal electrodes on the wiring board and terminated, and are arranged corresponding to each of the memories. In the vicinity of the input terminal electrode and the output terminal electrode, an external terminal electrode electrically connected to the external terminal is arranged, and an input terminal electrode arranged corresponding to each of the memories. The input terminal and the output terminal of each of the at least two or more memories are electrically connected to each other depending on the electrical connection state of the terminal electrode, the output terminal electrode, and the external terminal electrode by the surface mounting type conduction means. And a structure in which the input and output terminals of the at least two or more memories are drawn as separate external terminals. Further, as is possible, the memory module, characterized in that a said terminal electrodes for input, terminal electrodes and terminal electrodes for external output. 3. The memory module according to claim 1, wherein said surface-mount type conductive means is provided with said input terminal electrode and output terminal electrode by a switching operation of a logic circuit formed therein. And an integrated circuit chip capable of switching an electrical connection state between external terminal electrodes.