JP2002026228A - Memory module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory module which can flexibly correspond to a change in the bit constitution of a semiconductor storage device even when changed and whose productivity can be improved. SOLUTION: The semiconductor storage device 1 of four bit constitution has a rectangular packaged body 1a having a storage element inside and a plurality of connection terminals 2, 2,... protruded from the side edge parts of the packaged body 1a. A plurality of connection terminals 2, 2,... are arranged in symmetric positions through the packaged body 1a along confronted side edge parts 1b and 1c in the packaged body 1a. The connection terminals of one side in a pair of connection terminals 2 and 2 which are confronted through the packaged body 1a are set to be data input/output terminals (DQ0 to DQ3) to which data input/output signal lines are allocated, and the other connection terminals are non-connected terminals to which any signal line is not allocated. When constituting an eight bit composition, the data input/output terminal is allocated to a terminal equivalent to the non-connected terminal in a connection terminal arrangement similar to that of a four bit component.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM (Dynami
The present invention relates to a memory module in which a plurality of semiconductor storage devices such as c Random Access Memory) are mounted.

[0002]

2. Description of the Related Art A memory module has a function of mounting a plurality of semiconductor memory devices such as a DRAM on a printed wiring board or the like and increasing the memory of an electronic device such as a computer. As a typical memory module, an asynchronous or synchronous DIMM (Dual In-line Mem
ory Module) or SIMM (Single In-line Memory Modu)
le).

In most of the conventional memory modules, a printed circuit board is individually designed according to the word configuration of the semiconductor memory device in most cases. For example, 16 64-Mbit DRAMs having a 4-bit DQ (data input / output) pin arrangement are mounted on a printed circuit board.
When manufacturing a DIMM having a capacity of 8 Mbytes, a 64-Mbit DRAM having a DQ pin arrangement of 8-bit
64 mounted on individual (or 16) printed wiring boards
Since the pin arrangement is different from the case of manufacturing a DIMM having a capacity of M bytes (or 128 M bytes), it is necessary to prepare two types of printed wiring boards, and it is necessary to design two types of products. The n-bit configuration means a configuration in which input and output are performed in n-bit units. Usually, data input / output terminals (hereinafter, referred to as DQ terminals) are often arranged at symmetrical positions on two opposing sides of a package of a semiconductor memory device.

[0004]

However, the conventional memory module requires a design time for each type of semiconductor memory device having a different bit configuration for a plurality of types of semiconductor memory devices. At present, it is necessary to manage wiring boards. For this reason, the management of the printed wiring board becomes complicated, the management cost increases, and at the same time, when a design change of the memory module is required in a hurry at a customer or the like, there is a problem that the request cannot be promptly responded. Was.

In view of such a problem, the present invention is intended to simplify the management of a printed circuit board for a plurality of types of semiconductor memory devices having different bit configurations, and to flexibly cope with a change in the design of a memory module. The purpose of the present invention is to provide a memory module.

[0006]

In order to achieve the above object, the present inventor focused on the pin arrangement of a semiconductor memory device, and as a result of earnestly studying the correspondence between the pin arrangement and the wiring configuration of a printed wiring board. The present invention has been reached.

That is, a memory module according to a first aspect of the present invention has a main body having two opposing sides packaged with a storage element therein, and protruding from the two opposing sides of the main body. A plurality of connection terminals, and a semiconductor memory device comprising: a module substrate having a plurality of the semiconductor storage devices mounted on the surface thereof; anda plurality of connection terminals of the semiconductor storage device, The module substrate includes a plurality of connection terminal pairs arranged at symmetrical positions along two opposing sides of the main body.
A semiconductor memory device having a first configuration in which one of the connection terminal pairs is a data input / output terminal and the other is a non-connection terminal for each of the plurality of connection terminal pairs; A second terminal having both of the connection terminal pairs as data input / output terminals and having the plurality of connection terminal pairs arranged in the same manner as the semiconductor memory device of the first configuration.
And a wiring that can be mounted at the same position.

The invention according to claim 2 is the memory module according to claim 1, wherein the first configuration has an n-bit configuration and the second configuration has a 2n-bit configuration.

The invention according to claim 3 is the memory module according to claim 1 or 2, wherein the semiconductor memory device is also mounted on the back surface of the module substrate, and one of the front surface and the back surface is provided. A data input / output terminal of the semiconductor memory device and a data input / output terminal or a non-connection terminal of the semiconductor memory device on the other surface, which are located symmetrically on the front and back sides of the data input / output terminal, through the module substrate. They are connected via holes.

The invention according to claim 4 is the memory module according to claim 3, wherein the module substrate comprises:
The control signal wiring of the semiconductor memory device mounted on the front surface and the control signal wiring of the semiconductor memory device mounted on the back surface is switched to one of another electrically separated wiring and a common wiring electrically connected. It is provided with a switching electrode.

The invention according to claim 5 is the invention according to claims 1 to
5. The memory module according to claim 4, wherein the module substrate individually has data input / output wirings for the first configuration and the second configuration, and one of the data A resistor mounting electrode for adjusting the circuit resistance of the module substrate is provided on the input / output wiring.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Various embodiments of the present invention will be described below with reference to the drawings.

<First Embodiment> FIGS. 1 and 2 are plan views of a semiconductor memory device 1 according to a first embodiment of the present invention. FIG. 1 shows a semiconductor memory device having a 4-bit configuration, and FIG. 2 shows a semiconductor memory device having an 8-bit configuration. Semiconductor memory devices include SDRAM (Synchronous DRAM) and RDR.
A synchronous DRAM such as an AM (Rambus DRAM) or an asynchronous DRAM can be used. These semiconductor memory devices include a rectangular main body that is packaged with a storage element therein, and a plurality of connection terminals (pins) protruding from opposite side edges of the main body. Each of these connection terminals is connected to an address input signal (A), a data input / output signal (DQ), a column address strobe signal (CAS), a row address strobe signal (RAS), a chip select signal (CS), a power supply ( V). Terminals not assigned to any signal line are NC (Non Connecti
on) terminal (non-connection terminal).

The main body 1a of the semiconductor memory device 1 shown in FIG.
Has a rectangular shape, and a plurality of connection terminals 2, 2,... Are arranged at equal intervals and protrude from opposite side edge portions 1b, 1c of the main body 1a. Its side edge portions 1b, 1
c is DQ0 to DQ to which data input / output signals are assigned.
Three terminals, NC terminals, V _ss terminals and V _dd terminals to which power is _allocated are arranged, and these terminals are arranged at symmetrical positions via the main body 1a to form a plurality of connection terminal pairs. . If one of these connection terminal pairs is one of the data input / output terminals DQ0 to DQ3, the other has N
Terminal C is assigned. Although not explicitly shown in the figure,
The above-mentioned address input signal lines, chip select signal lines, and the like are assigned to the other connection terminals 2, 2,.

The 8-bit semiconductor memory device 10 shown in FIG. 2 has the same outer shape as the 4-bit semiconductor memory device 1 shown in FIG.
And connection terminal pairs having the same arrangement as the above, and data input / output terminals (DQ0 to DQ7) are allocated to both of these connection terminal pairs. Assignment of signal lines to terminals 11, 11,... Other than these data input / output terminals is the same as that of semiconductor memory device 1 shown in FIG.

The type of the package of the semiconductor storage devices 1 and 10 may be a pin insertion type or a surface mount type. The pin insertion type is a type in which connection terminals protrude vertically downward from the main body of the semiconductor storage device, and the surface mount type has connection terminals protruding from the main body of the semiconductor storage device bent or This is a type in which ball-shaped connection terminals are provided on the surface of the main body. As a surface mount type package, an SOP (Small Outline Packag) in which the ends of the connection terminals are bent outward to be substantially parallel to the substrate is used.
e), TSOP (Thin Small Outline Package), SO
I (Small Outline I-leaded Package). DIP (Dual Inl.
ine Package), ZIP (Zigzag Inline Package), S
IP (Single Inline Package) and the like. In particular, the surface mount type package is preferable because the height from the substrate at the time of mounting can be suppressed to be lower than that of the pin insertion type and is advantageous in terms of mounting density in the height direction.

A memory module is formed by mounting a plurality of the semiconductor storage devices 1 and 10 on a module substrate. The data input / output wiring of the module board can be shared by the above-described semiconductor memory device 1 having the 4-bit configuration and the semiconductor memory device 10 having the 8-bit configuration. As illustrated in FIG. 3, the memory module 12 includes the above-described 4-bit or 8-bit semiconductor memory devices 15, 15,..., 15 on the front surface 13 a or both front and back surfaces of the module substrate 13 made of a printed wiring board. Are connected by soldering or the like.

Also, as shown in FIG.
3 along the lower side edge of the plurality of contact portions 14, 1
4, ... are juxtaposed. For example, JEDEC (Joint Electron
They are arranged according to predetermined widths and intervals according to standards such as Device Engineering Council. These contact portions 14, 14,... Are made of copper foil or the like, and are mounted and electrically connected to an external socket (not shown) prepared in a computer or the like. The contact portions 14, 14,
The notch 13c formed between... Can determine the positioning of the memory module with respect to the external socket and the logical structure of the memory module. Further, it is desirable to use a substrate compliant with the standard such as JEDEC as the module substrate 13 from the viewpoint of general use. Further, a latch or a buffer may be provided on the output side of the semiconductor memory device 15.

By using the semiconductor memory devices 1 and 10 as shown in FIGS. 1 and 2, the data input / output wiring of the module substrate is shared by the 4-bit semiconductor memory device and the 8-bit semiconductor memory device. Since it is possible, the trouble of designing a different module substrate for each bit configuration is reduced, and the design time can be shortened. In addition, it is possible to reduce the management cost of the printed wiring board and to respond quickly and flexibly to design changes.

FIGS. 1 and 2 show examples of a semiconductor memory device having a 4-bit configuration and an 8-bit configuration, respectively. However, the present invention is not limited to this.
The present invention can be similarly applied to a semiconductor memory device having an n-bit configuration (n: natural number) such as a 16-bit configuration and a 32-bit configuration and a 2n-bit configuration.

Second Embodiment Next, a memory module according to a second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a schematic diagram showing an example of wiring of a module substrate on which semiconductor memory devices are mounted on both front and rear surfaces, respectively.
a, (b) shows the back surface 20b of the module substrate 20;
FIG. 3 is a schematic view showing an example of wiring formed on each of the first and second embodiments.

As shown in FIG. 4A, the module substrate 2
0 is provided on the main surface 20a of the semiconductor memory device 2 having the 4-bit configuration or the 8-bit configuration as described in the first embodiment.
1, electrode terminals 2 provided on the main surface 20a thereof.
The connection terminals of the semiconductor memory device 21 are respectively mounted on 2, 22,. On the lower edge of the main surface 20a, there are formed contact portions 24A, 24A,... Which are mounted and electrically connected to an external socket (not shown) prepared on a motherboard of a computer or the like. The contact portions 24A, 24A,... Are connected to the electrode terminals 22, 22,.
It is conducting.

On the other hand, as shown in FIG. 4B, a semiconductor memory device 26 having the same bit configuration and connection terminal arrangement as shown in FIG. 4A is also mounted on the back surface 20b of the module substrate 20. , The electrode terminal 2 provided on the back surface 20b
The connection terminals of the semiconductor storage device 26 are respectively mounted on 7, 27,. In addition, a contact portion 2 to be attached to the above-mentioned external socket is provided on a lower side edge of the back surface 20b separately from the contact portion 24A formed on the main surface 20a.
4B, 24B,... Are formed. Contact part 24
, B, 24B, ... are electrically connected to the electrode terminals 27, 27, ... through wiring (not shown) provided on the module substrate 20.

The module substrate 20 has through holes 23A to 23H formed by burying a wiring material in through holes penetrating the front and back surfaces. Through these through holes 23A to 23H, the electrode terminals 22 formed on the main surface 20a and the electrode terminals 2 formed on the back surface 20b
,... Are connected according to the wiring configuration of FIGS.

When the semiconductor memory devices 21 and 26 mounted on both the front and back surfaces of the module substrate 20 are the semiconductor memory device 1 having a 4-bit configuration (hereinafter, referred to as a 4-bit configuration product), the through-hole 23A is provided. 23H are connected to the data input / output terminals (DQ0 to DQ3) of the connection terminal pair of the semiconductor memory device 1 and the four NC terminals located symmetrically with the DQ0 to DQ3 terminals. FIG.
FIG. 2 is an equivalent circuit diagram showing a wiring configuration between such 4-bit components 1 and 1 on both sides. As shown, between the 4-bit components 1 and 1 on the front and back surfaces, the DQ0 to DQ3 terminals and the four NC terminals are connected in a one-to-one correspondence, and at the same time, connected by a common wiring.

When the semiconductor memory devices 21 and 26 mounted on the front and back surfaces of the module substrate 20 are both the 8-bit semiconductor memory device 10 (hereinafter, referred to as an 8-bit component), the through holes 23A are provided. 23H are respectively connected to data input / output terminals (DQ0 to DQ7) among the connection terminals of the 8-bit component 10. FIG.
FIG. 2 is an equivalent circuit diagram showing a wiring configuration between the 8-bit components 10 on both sides. As shown
The DQ1 terminal and the DQ6 terminal, the DQ2 terminal and the DQ5 terminal, the DQ3 terminal and the DQ4 terminal are respectively connected between the 8-bit components 10 and 10 on the front and back surfaces, and are also connected by common wiring.

As described above, the wiring structure corresponding to both the 4-bit component and the 8-bit component is formed on both sides of the module substrate 20.

When the semiconductor memory devices 21 and 26 are both the 8-bit components 10, 10, the data input / output terminals (DQ0 to DQ7) of the semiconductor memory device on both the front and back surfaces of the module substrate 20 are commonly wired. In order to avoid data signal collisions, the main surface 20
8-bit components 10, 10 to be mounted on a and the back surface 20b
It is necessary to separately provide control signal wiring for selecting and switching any one of them. In such a case, one bank is constituted by the group of 8-bit components mounted on the main surface 20a, and one bank is constituted by the group of 8-bit components mounted on the rear surface 20b. Thus, two banks are constituted as a whole. As a control signal for controlling such bank switching, a CS signal may be used when the 8-bit component 10 is a synchronous DRAM, and a RAS signal may be used when the 8-bit component 10 is an asynchronous DRAM.

<Embodiment 3> When the 8-bit components are mounted on both the front and back surfaces of the module substrate as described above, it is necessary to separately prepare control signal wiring for bank switching on the front and back surfaces. This is not necessary when 4-bit components are mounted on both sides of the module substrate. FIG. 7 is a schematic diagram showing an example of the control signal wiring of the module substrate 30 of the memory module according to Embodiment 3 of the present invention. In FIG. 7, reference numeral 30 denotes a module substrate, 31A.
31D indicate semiconductor memory devices mounted on the main surface 30a of the module substrate 30, 32A to 32D indicate electrode terminals joined to connection terminals of the semiconductor memory device, and 38, 39 and 40 indicate electrodes. Reference numerals 33A to 33D, 34A to
Reference numerals 34D, 35, and 36 denote through holes formed by embedding a wiring material in through holes penetrating the front and back of the module substrate 30.

On the back surface 30b of the module substrate 30, semiconductor storage devices 31Ad to 31Dd (not shown) correspond to the semiconductor storage devices 31A to 31D, respectively.
Are mounted via electrode terminals (not shown) formed on the back surface 30b. The electrode terminals corresponding to the data input / output terminals of the semiconductor memory devices 32A to 32D and 32Ad to 32Dd mounted on the front and back surfaces are connected via through holes (not shown) as shown in FIG. I have.

The through holes 33A to 33D are connected to electrode terminals 32A to 32D corresponding to CS signals (or RAS signals) of the semiconductor memory devices 31A to 31C mounted on the main surface 30a of the module substrate 30, respectively. These through holes 33A to 33D and through hole 35 are connected by common wiring. On the other hand, through holes 34A to 34D are connected to electrode terminals corresponding to CS signals (or RAS signals) of semiconductor memory devices 31Ad to 31Cd mounted on back surface 30b of module substrate 30, respectively. 34D and the through hole 36 are connected by common wiring.

The semiconductor memory devices 31A to 31D, 31Ad to 31
When the above 4-bit component 1 is adopted as 31Dd,
By mounting a short-circuit resistor between the electrode 38 and the electrode 39, a control signal line such as a CS signal or a RAS signal on both front and rear surfaces becomes a common wiring, and the control signal line is electrically connected to the contact portion 37.

On the other hand, semiconductor memory devices 31A to 31D, 31Ad to 31
When the 8-bit component 10 is adopted as the 31Dd, by opening the electrode 38 and the electrode 39 and mounting an open resistor between the electrode 39 and the electrode 40, the CS signal and the RAS signal on both the front and back surfaces are controlled. The control signal lines are individually connected to the contact portions 37, 37. This allows
Since the bank can be switched, it is possible to prevent a data signal collision caused by connecting the data input / output terminals of the semiconductor memory devices on both the front and back sides with a common wiring.

As described above, by mounting the above-described open resistor or short-circuit resistor on the module substrate 30, wiring for control signals can be simplified in accordance with the bit configuration of the semiconductor memory device mounted on the module substrate 30. Can be switched.

In the third embodiment, the module substrate 30 corresponding to both the 4-bit component and the 8-bit component
However, the present invention is not limited to this, and can be applied to n-bit components and 2n-bit components such as 8-bit components and 16-bit components, and 16-bit components and 32-bit components.

<Embodiment 4> Next, in the standard by JEDEC or the like, the specification of the circuit resistance on the module substrate differs between the case where a 4-bit component is mounted and the case where an 8-bit component is mounted, for example. In such a case, it is necessary to change the circuit resistance of the module substrate between the case where the 4-bit component is mounted and the case where the 8-bit component is mounted. FIG. 8 is a schematic diagram illustrating an example of a wiring configuration of a module board according to Embodiment 4 of the present invention.

In FIG. 8, reference numeral 50 denotes a module substrate, 50a denotes a main surface of the module substrate 50, 50b denotes a back surface thereof, 51 denotes a semiconductor memory device mounted on the module substrate 50, and 52 denotes a connection with a connection terminal of the semiconductor memory device 51. The electrode terminal 53 is a through hole formed by embedding a wiring material in a through hole penetrating the front and back of the module substrate 50.
Reference numerals 4, 55, 56, 57, and 58 indicate electrodes, and 59 indicates a contact portion. Also, the back surface 50b of the module substrate 50
A semiconductor memory device 51d (not shown) of the same type as the semiconductor memory device 51 is mounted on the semiconductor device.

The electrodes 54 and 56 are connected to the semiconductor memory 5
An electrode terminal 52 corresponding to one data input / output terminal is connected, and an electrode 55 and an electrode 57 are connected via a through hole 53. The through holes 53 are connected to electrode terminals (not shown) corresponding to data input / output terminals of the semiconductor memory device 51d mounted on the back surface. Such wiring is similarly formed on the back surface of the module substrate 50.

When the 4-bit component 1 is used as the semiconductor memory device 51 mounted on the module substrate 50, a switching resistor is mounted between the electrode 56 and the electrode 58 so that the electrode terminal 52 is connected to the electrode 56. Conduction is made to the contact part 59 via the electrode 58. On the other hand, the semiconductor memory devices 51 mounted on the front and back surfaces of the module substrate 50,
When the 8-bit component 10 is adopted as the component 51d, a chip resistor for adjusting the circuit resistance is mounted between the electrode 54 and the electrode 55, and a switching resistor is mounted between the electrode 57 and the electrode 58. Terminal 52 is connected to electrodes 54 and 5
Conduction is made to the contact portion 59 through 5, 57, 58. Here, between the electrode 56 and the electrode 58 or the electrode 5
As the switching resistor or the chip resistor mounted between the electrode 7 and the electrode 58, a noise removing damping resistor may be used.

As described above, in the module substrate 50 according to the present embodiment, the circuit resistance for data input / output can be easily changed corresponding to the bit configuration of the semiconductor memory device 51. And 8-bit components. In the third embodiment, the module board 30 corresponding to both the 4-bit component and the 8-bit component has been described. However, the present invention is not limited to this.
The present invention is also applicable to n-bit components and 2n-bit components such as 8-bit components and 16-bit components, and 16-bit components and 32-bit components.

[0041]

As described above, according to the memory module of the first aspect of the present invention, the module substrate can be shared by both the semiconductor memory device having the first configuration and the semiconductor memory device having the second configuration. Therefore, there is no need to design and manage a module substrate for each of the two types of semiconductor memory devices having different bit configurations, so that the design time of the memory module can be shortened and the design change can be made flexibly and quickly. Also, during mass production of the memory module, it is possible to simplify the production and management of the module substrate.

According to the second aspect, a memory module using a general-purpose semiconductor memory device such as a 4-bit configuration and an 8-bit configuration, or an 8-bit configuration and a 16-bit configuration can be manufactured.

According to the third aspect, since the semiconductor memory device can be mounted on both the front and back surfaces, a large-capacity memory module can be realized.

According to the fourth aspect, 2n is provided on the module substrate.
When a semiconductor memory device with a bit configuration is mounted, either one of the front and back semiconductor memory devices can be selected, thereby avoiding collision of data signals by connecting the data input / output terminals of the semiconductor memory devices on both front and back surfaces with a common wiring. can do.

According to the fifth aspect, the wiring resistance of the module substrate can be adjusted in accordance with the standards such as JEDEC, depending on whether or not a resistor is mounted on the module substrate. And the semiconductor memory device having the second configuration can be easily supported.

[Brief description of the drawings]

FIG. 1 is a plan view showing a 4-bit semiconductor memory device according to a first embodiment of the present invention;

FIG. 2 is a plan view illustrating an 8-bit semiconductor memory device according to the first embodiment of the present invention;

FIG. 3 is a schematic plan view showing the memory module according to the first embodiment of the present invention.

4A is a schematic diagram illustrating a front surface of a memory module according to a second embodiment of the present invention, and FIG. 4B is a schematic diagram illustrating a back surface of the memory module illustrated in FIG.

5 is an equivalent circuit diagram showing a wiring configuration when the 4-bit semiconductor memory device shown in FIG. 1 is mounted on both front and rear surfaces.

6 is an equivalent circuit diagram showing a wiring configuration when the 8-bit semiconductor memory device shown in FIG. 2 is mounted on both front and rear surfaces.

FIG. 7 is a diagram showing a wiring example for a control signal of a module substrate according to a third embodiment of the present invention.

FIG. 8 is a diagram showing a wiring example for data input / output of a module board according to a fourth embodiment of the present invention.

[Explanation of symbols]

1,10 semiconductor storage device, 2,11 connection terminal (pin), 20 module substrate, 21,26 semiconductor storage device, 22,27 connection terminal (pin), 23A to 23H
Through hole, 24 contacts.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/10 495 H01L 25/14 Z

Claims (5)

[Claims] 1. A semiconductor memory comprising: a main body having two opposing sides packaged with a storage element therein; and a plurality of connection terminals protruding from the two opposing sides of the main body. A memory module comprising: a device; and a module substrate on which a plurality of the semiconductor storage devices are mounted. A plurality of connection terminals of the semiconductor storage device are symmetrical along two opposing sides of the main body. A plurality of connection terminal pairs arranged at different positions, wherein the module substrate has one of the connection terminal pairs as a data input / output terminal and the other as a non-connection terminal for each of the plurality of connection terminal pairs. The semiconductor memory device of the first configuration, wherein both of the connection terminal pairs are data input / output terminals for each of the plurality of connection terminal pairs, and are the same as those of the semiconductor memory device of the first configuration. Memory module, characterized in that said semiconductor memory device of the second configuration having a plurality of connecting terminal pairs, both of having wiring which can be mounted in the same position. 2. The memory module according to claim 1, wherein said first configuration is an n-bit configuration and said second configuration is an n-bit configuration.
Is a 2n-bit memory module. 3. The memory module according to claim 1, wherein said semiconductor memory device is also mounted on a back surface of said module substrate, and data of said semiconductor memory device on one of said front surface and back surface. An input / output terminal and a data input / output terminal or a non-connection terminal of the semiconductor memory device on the other surface, which are symmetrically positioned with respect to the data input / output terminal,
A memory module connected through a through hole penetrating the module substrate. 4. The memory module according to claim 3, wherein the module substrate electrically connects each control signal wiring between the semiconductor memory device mounted on the front surface and the semiconductor memory device mounted on the back surface. A memory module comprising a switching electrode for switching to one of a separated separate wiring and a common wiring electrically connected. 5. The memory module according to claim 1, wherein the module substrate individually connects data input / output wirings of the first configuration and the second configuration. A memory module comprising: a resistor mounting electrode for adjusting a circuit resistance of the module substrate on one of the data input / output lines.