JPH0918837A - Hd-ws conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the HD-WS conversion device capable of conversion with less degradation of the picture quality in a simple constitution. SOLUTION: 2112 picture elements of one line of the high-vision signal subjected to A/D conversion are expanded to four layers to obtain 528 picture elements in each layer. In the double speed conversion, line memories 24 and 25 are switched by a switching circuit 26 to read out 352 picture elements. 64 picture elements are read and enabled to obtain 412 picture elements by a field memory 27, and four layers are synthesized in a RAMDAC 28 to obtain 1664 picture elements, and thereafter, D/A conversion is performed. A part more than the number of effective picture elements 1280×1024 of the WA signal is blanked by the RAMDAC 28. The clock frequency of double speed conversion or overall picture element data to 1/6 is 17.82MHz for write and 23.76MHz for read. The double speed conversion processing with <=30MHz clock signal having a lower frequency is possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a BTA (broadcasting
technology association) HD that converts high-definition signals conforming to the standard to workstation signals
The present invention relates to a WS conversion device.

[0002]

2. Description of the Related Art Conventionally, HDTV (High Definition Tele)
The so-called high-definition signal of vision) is well-equipped with equipment and facilities, and is attracting attention in various fields as high-quality video material. It has already been performed to digitize a high-vision signal as this high-quality image and convert it into an NTSC signal, a computer signal, or the like. In such an environment, in order to utilize the most probable HD video signal of technology and equipment, more economical HD-WS
There is a need for a conversion device.

[0003] As a conventional example similar to the present invention in the technical field, Japanese Patent Application Laid-Open No. Hei 3-23 regarding NTSC-HD converter
No. 9079, and Japanese Patent Application Laid-Open No. 3-2 regarding image forming apparatus
No. 05982. The former purpose is to add E to the NTSC signal.
By performing DTV signal processing and compressing the output signal in the horizontal direction at a specific magnification on the time axis, the original signal can be accurately reproduced on a high definition monitor. The latter object is to prevent image distortion by forming an image such that the aspect ratio of each pixel corresponding to an image signal is in a predetermined state.

[0004]

However, conventionally, when a Hi-Vision signal is handled as a digital signal, B
In the TA path, the pixel configuration is 1920 × 1035, and the aspect ratio of each pixel is not 1: 1 but a vertically long shape.
Therefore, if a high-definition signal is supplied to a device that handles image data assuming that the aspect ratio of each pixel is 1: 1,
The aspect ratio of the original image is different. Further, when converting a high-definition signal into a workstation signal, since the signal format is completely different, there is a problem that the conversion method is complicated or the image quality is greatly deteriorated depending on the method.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an HD-WS converter capable of performing conversion with a simple configuration and with little image quality deterioration.

[0006]

In order to achieve the above object, an HD-WS converter according to the present invention converts a high-definition signal into a workstation signal, and converts the high-definition signal from a valid pixel 1920.times.1035 to a workstation signal. HD-W to cut out pixels 1280 × 1024
An A / D converter for A / D-converting a Hi-Vision signal; and developing four layers of all pixel data per A / D-converted line to reduce the number of pixels per layer to one of the total number of pixels. / 4, and double-speed conversion means for converting the pixel data of each layer developed for the four layers to double-speed and for reducing the number of pixels per layer to 1/6 of the total pixel data. The pixel data thus obtained is used as frame data and used as image data of a workstation.

Further, it is preferable that the above-mentioned double speed conversion means sets the read data per layer in the four-layer expansion to 352 lines and obtains the effective pixel 1280 from this read data.

[0008]

Therefore, according to the HD-WS converter of the present invention, the HDTV signal is A / D-converted, all the pixel data per A / D-converted line are expanded into four layers, and the number of pixels per one layer is reduced. The number of pixels per one layer is reduced to approximately 1/6 of the total pixel data by converting the pixel data of each layer developed into four layers to double the speed. The double-speed-converted pixel data is used as frame data and image data of a workstation. Therefore, since approximately one-sixth pixel data is cut out and subjected to the conversion process, it is possible to perform processing with a lower frequency clock signal.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
An embodiment of the WS converter will be described in detail. 1 to 3, there is shown an embodiment of an HD-WS conversion device according to the present invention. FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention, FIG. 2 is a diagram for explaining a pixel conversion process per line, and FIG. 3 is a system configuration diagram showing an application example of the embodiment of the present invention. is there.

In FIG. 3, the system configuration of an application example is as follows.
It comprises a high-vision device 1, an HD-WS converter 2, and a display 3 for a workstation.

[0011] The Hi-Vision device 1 of these components is:
It is a video source of a Hi-Vision video signal, and is, for example, a Hi-Vision camera, a Hi-Vision VTR, or a Hi-Vision LD. The HD-WS conversion device 2 is an HD-WS conversion device of the present embodiment that converts a video signal from the high-definition device 1 and outputs it as a workstation signal. The workstation-compatible display 3 is a display corresponding to a workstation signal, and is, for example, a CRT display or a multi-sync projector.

FIGS. 1 and 2 show an example of a signal processing configuration in which a HD video signal of the HD-WS converter of the present embodiment applied as described above is used as a WS video signal. First, the signal processing contents of the HD-WS converter of the present embodiment will be described.

When a Hi-Vision signal is sampled at 74.25 MHz defined by the BTA standard, the number of effective pixels per line is 1920. Therefore, 192
Each effective pixel composed of 0 × 1035 has a vertically long shape in an image having an aspect ratio of 16: 9. In other words, it is vertically long with a ratio of 1920/16: 1035/9 = 24: 23.

On the other hand, since the aspect ratio of the pixels in the display is 1: 1 and a square, the number of pixels in one line is 1 in order to realize the aspect ratio of the HDTV signal of 16: 9.
1920 × 23/24 = 1 obtained by dividing 920 by the aspect ratio
From 840, 1840 pixels per line may be used. Therefore, when displaying a Hi-Vision signal on a square pixel display, the number of effective pixels per line is set to 1920.
From 1840 to 1840. When sampling is performed so that the number of effective pixels per line is 1840, the total number of samples s per line is as follows.

S = 1840 × 2200/1920 = 2108.333

Next, four layers are developed in order to lower the data processing frequency. In this case, the number of samples
It is desirable to select a value that is an integral multiple of four. A value satisfying this condition is an approximate value of 2108.333 for 2108 or 2112.

Next, when the double speed conversion is performed, all the data is read at the clock frequency which is normally doubled. In the present embodiment, the purpose is to convert to a workstation signal and cut out effective pixels 1280. Therefore, in the 4-layer development, 1/4 of 3
It suffices to read out 20 or more effective pixels. From the viewpoint of hardware scale and PLL stability, it is desirable that the total number of samples in one line be a value divisible by an even integer. The value is obtained as follows.

2108/6 = 351.333; 21
12/6 = 352

Of these values, the integer 352 is the optimum value. The total number of samples in one line at that time is 211
2 is the optimal value. The clock frequencies at that time are 23.76 MHz and 71.28 MHz. 2
3.76 MHz becomes 1/3 of 71.28 MHz and can be easily divided.

The above processing is executed by the HD-
The WS converter includes an A / D converter 21 that converts a high-definition signal into a digital signal, a four-layer expansion unit 22 that expands a digitized video signal into four layers, and line memories 23 and 24 that generate an interpolation signal and perform double-speed conversion. 25, line memory 2
A switching circuit 26 for switching and taking in input signals from 4 and 25, a field memory 2 for forming a field image
7. It has each signal processing unit of the RAMDAC 28 for converting to a WS image signal. Further, a PL that generates a timing signal and a CLK signal to be supplied to each of the signal processing units described above.
It has an L circuit 29, a timing generation circuit 30, and a CLK generation circuit 31.

In each of the above sections, the A / D converter 21 A / D converts the Hi-Vision signal input from the input terminal at a sample clock frequency of 71.28 MHz. A
As shown in FIG. 2A, the number of samples and the number of pixels per line after the / D conversion are 2112 (the number of effective pixels is 1).
840).

Next, four layers are developed by the four-layer developing unit 22, and the clock frequency to be processed is set to 17.82 MHz. The number of samples (the number of effective pixels) per layer after the development processing is 528 (460 pixels) as shown in FIG.
Thereafter, an interpolation signal is created for each layer using the line memory 23.

Next, double speed conversion is performed in the line memories 24 and 25. Figure 2 shows the number of samples per layer after the conversion process.
As shown in (4), there are 352 lines. At this time, data writing is reset with a pulse of 33.75 kHz. When the phase of the reset pulse is changed, the start position of 352 lines cut out from 528 lines per line is changed, and the output screen can be moved left and right. Reading is 67.5 kHz.
Reset by the pulse of z. The clock frequency at this time is 17.82 MHz for writing and 2 for reading.
3.76 MHz.

Next, the switching circuit 26 switches the original signal line and the interpolation signal line for each line as shown in FIG.

Next, 67.5 is stored in the field memory 27.
Convert from kHz to 64.68 kHz. FIG. 2 (6),
As shown in (7), 352 lines are written and 416 lines are read. Read enable is applied to 64 of the differences. At this time, writing is reset by a pulse of 67.5 kHz, and reading is reset by a pulse of 64.68 kHz. The clock frequency at this time is 23.76 MHz for writing and 26.9 MHz for reading,
The read enable period is 604.6 nS.

Next, the signals of the four layers are synthesized by the RAMDAC 28 and D / A converted by the D / A converter. As shown in FIG. 2 (8), there are 1408 effective pixels per line. As shown in FIG. 2 (9), the number of effective pixels of the WS signal is 12
The portion larger than 80 is blanked by the RAMDAC 28.

Thus, the high-definition signal can be easily converted into the workstation signal, and the effective pixel 1920 ×
An image of 1280 × 1024 with little deterioration in image quality can be cut out from 1035.

The read clock frequency of 23.76 MHz in the double-speed conversion of the above embodiment is 35.64 which is の of the general read clock frequency of 71.28 MHz.
MHz, but within 30 MHz.

Although the above embodiment is an example of a preferred embodiment of the present invention, the present invention is not limited to this, and various modifications can be made without departing from the gist of the present invention.

[0030]

As is clear from the above description, the HD-WS conversion device of the present invention converts the high-definition signal from analog to digital and converts all the pixel data per line after the analog-to-digital conversion into four.
Expand the layers and set the number of pixels per layer to 1/4 of the total number of pixels.
The pixel data of each of the developed layers is double-speed-converted to make the number of pixels per layer approximately 1/6 of the total pixel data. The double-speed-converted pixel data is defined as frame data and image data of effective pixels 1280 × 1024 per line. Therefore, since the pixel data of approximately 1/6 is cut out and subjected to the conversion process, the double speed conversion process with a lower frequency clock signal of 30 MHz or less becomes possible. This allows for hardware scale,
Cost, power consumption and heat generation can be reduced.

[Brief description of the drawings]

FIG. 1 is a functional block configuration diagram of an embodiment of an HD-WS conversion device of the present invention.

FIG. 2 is a diagram illustrating a process of converting pixels per line in FIG. 1;

FIG. 3 is a system block diagram to which the embodiment of FIG. 1 is applied.

[Explanation of symbols]

 1 Hi-Vision equipment 2 HD-WS converter 3 Workstation compatible display 21 A / D converter 22 4 layer development circuit 23, 24, 25 Line memory 26 Switching circuit 27 Field memory 28 RAMDAC 29 PLL circuit 30 Timing generation circuit 31 CLK generation circuit

Claims (2)

[Claims] 1. A high-definition signal is converted into a workstation signal, and the effective pixel 1920 × of the high-definition signal is converted.
The effective pixel 128 of the workstation signal from 1035
An HD-WS conversion device that cuts out 0 × 1024, A / D conversion means for A / D converting the high-definition signal, and converting the A / D converted all pixel data per line into four.
Expand the layers and set the number of pixels per layer to 1/4 of the total number of pixels 4
Layer developing means; and double-speed converting means for converting the pixel data of each of the four-layer-expanded layers to double-speed conversion so that the number of pixels per layer is substantially 1/6 of the total pixel data. An HD-WS converter, wherein pixel data is used as frame data and used as image data of a workstation. 2. The double speed conversion means is one of the four-layer expansion.
2. The HD-WS converter according to claim 1, wherein the read data per layer is 352, and the effective pixels 1280 are obtained from the read data.