JPH09186563A - Circuit and method for generating signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal with a more accurate pulse width corresponding to input data. SOLUTION: A selector 10 selects input data when a most significant bit D8' of data selected by the selector 10 at one preceding period of an SCK is coincident with a most significant bit D8 of the input data, and selects data resulting from inverting all bits of the input data when dissident. Genuine D/A converters (DAC) 4 and 5 apply D/A conversion to the data selected by the selector 10 and comparators 2, 3 compare a triangle wave TRI generated from a triangle wave generating circuit 1 with the output of the DAC 4, 5. A switch S1 selects the output of the comparator 2 when the D8', D8 are coincident similarly to the case with the selector 10 and the switch S1 selects the output of the comparator 3 when dissident to provide the output of a PWM.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal generation circuit and a method thereof, for example, a signal generation circuit and a method thereof for generating a signal having a pulse width corresponding to input data in synchronization with an input clock. It is a thing.

[0002]

2. Description of the Related Art FIG. 1 is a block diagram showing a configuration example of a PWM pixel modulation circuit. A pulse signal whose cycle is the same as that of an input clock signal SCK and whose pulse width changes according to input data from the center of one cycle of SCK is shown. I will get it.

In FIG. 1, a triangular wave generating circuit 1 generates a triangular wave TRI synchronized with SCK, and a true D / A converter (DAC) 4 outputs its true analog value for digital input data D8 to D1. . Then, by comparing the output of the DAC 4 and the triangular wave TRI with the comparator 2, a pulse signal having a pulse width corresponding to the input data can be obtained.

[0004]

However, the above-mentioned technique has the following problems.

Generally, an electronic circuit has variations in element characteristics, stray capacitance, and the like, and even in the DAC 4, due to these influences, there is some delay in the transition of the signal level.
There is a slight slope at the output change point of C4. Therefore, even if a stable triangular wave can be obtained, it takes a lot of time to change the level of DAC4 in a place where the signal level changes greatly, and as a result, a part of the pulse width is reduced (or increased). I cannot get accurate PWM output. This level transition time is always present, and the higher the frequency of the input clock signal, the larger the lack of the pulse width, which is a serious problem for the high-speed PWM circuit.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a signal generation circuit and a method therefor which can obtain a more accurate pulse width signal corresponding to input data.

[0007]

The present invention has the following configuration as one means for achieving the above object.

A signal generation circuit according to the present invention is a signal generation circuit which generates a signal having a pulse width corresponding to input data in synchronization with an input clock, and generates a reference signal from the input clock. Generating means, inverting means for inverting each bit of the input data, first selecting means for selecting the input data or the output of the inverting means, and data selected by the first selecting means. First comparing means for converting into a signal corresponding to an exact value and comparing with the reference signal, and data converted by the first selecting means into a signal corresponding to its complement value and the reference signal Second comparing means for comparing, second selecting means for selecting one of the comparison results obtained by the first and second comparing means, and the first selecting one cycle before the input clock. And the predetermined bits of data selected by the step, in response to a predetermined bit of said input data,
And a control means for controlling the first and second selection means.

A signal generation circuit for generating a signal having a pulse width corresponding to input data in synchronization with an input clock, wherein a reference signal is generated from a signal obtained by dividing the input clock. Means, an inverting means for inverting each bit of the input data, a first selecting means for selecting the input data or an output of the inverting means, and a data selected by the first selecting means as an exact numeric value thereof. And a first comparing means for converting the signal into a signal corresponding to the above and comparing with the reference signal, and converting the data selected by the first selecting means into a signal corresponding to its complement value and comparing with the reference signal. Based on the second comparing means and the predetermined signal,
Second selecting means for selecting one of the comparison results obtained by the first and second comparing means, and a predetermined bit of data selected by the first selecting means one cycle before the input clock Controlling the first selecting means according to the predetermined bit of the input data,
And a control unit for switching the predetermined signal for controlling the selection of the second selection unit.

An image processing apparatus according to the present invention is a signal generation circuit for generating a signal having a pulse width corresponding to input data in synchronization with an input clock, and generating a reference signal from the input clock. Generating means, inverting means for inverting each bit of the input data, first selecting means for selecting the input data or the output of the inverting means, and data selected by the first selecting means. First comparing means for converting into a signal corresponding to an exact value and comparing with the reference signal, and data converted by the first selecting means into a signal corresponding to its complement value and the reference signal Second comparing means for comparing, second selecting means for selecting one of the comparison results obtained by the first and second comparing means, and the first selecting one cycle before the input clock. And the predetermined bits of data selected by the step, in response to a predetermined bit of said input data,
A signal generating circuit having a control means for controlling the first and second selecting means is provided, and a signal having a pulse width according to the input image data is output.

A signal generating method according to the present invention is a signal generating method for generating a signal having a pulse width corresponding to input data in synchronization with an input clock, the input data or the input data. From the input clock, a first selection step of selecting data with each bit inverted, a first conversion step of converting the data selected in the first selection step into an exact value signal corresponding to the exact value, and A first comparing step of comparing the generated reference signal with the exact value signal, and a second converting step of converting the data selected in the first selecting step into a complementary value signal corresponding to the complementary value thereof. , A second comparison step of comparing the reference signal and the complement value signal, and a second selection step of selecting one of the comparison results obtained in the first and second comparison steps. And-up, and the predetermined bits of data selected in the first selection step before one cycle of the input clock, in response to said predetermined bit of said input data,
A control step for controlling the selection of the first and second selection steps.

A signal generation method for generating a signal having a pulse width corresponding to input data in synchronization with an input clock, wherein the input data or data obtained by inverting each bit of the input data is generated. A first selection step for selecting, a first conversion step for converting the data selected in the first selection step into a true value signal corresponding to the true value, and a signal generated by dividing the input clock. A first comparison step of comparing the reference signal and the exact value signal, and a second conversion step of converting the data selected in the first selection step into a complementary value signal corresponding to the complementary value thereof, A second comparison step of comparing a reference signal and the complement value signal, and one of the comparison results obtained in the first and second comparison steps is selected based on a predetermined signal. Two selection steps, the selection of the first selection step according to the predetermined bit of the data selected in the first selection step one cycle before the input clock and the predetermined bit of the input data. And a control step of switching the predetermined signal for controlling the selection in the second selection step.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION

[Triangular Wave Generation Circuit] First, a configuration for obtaining a stable triangular wave will be described.

FIG. 2 is a block diagram showing an example of the configuration of a triangular wave generation circuit. The frequency dividing circuit 11, variable delay circuit 12, exclusive OR (EXOR) circuit 18, comparators 22 to 24, buffer 13, charge pump circuit ( CP) 14,15, error signal generator (Du, PP)
16, 17, capacitor C1, and current sources I1 to I3.

That is, the triangular wave generating circuit 1 eliminates the influence of the duty deviation by dividing the SCK into two, and the variable delay circuit 12 having a delay amount of T0 / 2 with respect to the cycle T0 of the SCK divides it into two. Delay the rounded signal by T0 / 2. Then, by EXORing the divided signal and the delayed signal, a signal synchronized with SCK and having a predetermined duty is obtained.

FIG. 3 is a circuit diagram for explaining the operation of the variable delay circuit 12, and FIG. 4 is a diagram showing the waveform of each part of the variable delay circuit 12, where R1 = R2 = R, I11 = I14, and the delay amount. ΔT is determined by the following equation. ΔT = R ・ C11 ・ I13 / I12… (1)

In this circuit, the input Pin is H level, Ni
When n is at the L level, the transistors Q9 and Q8 are off, and the current I13 flows through R2 and Q6. Therefore, Q10
Is off, and the output Nout is at L level. On the other hand, I12
It flows through Q2, Q3, and Q4, and Q5 turns off, so Q1 turns on and Pout is at the H level. At this point, the emitter potential Vb of Q3 changes from the potential of Pout to the base-emitter voltage Vb.
It is fixed at a potential lower by e.

Next, when the polarities of Pin and Nin are reversed, Q9 turns on and Q4 turns off, I12 first flows from C11 through Q9, and the emitter potential Va of Q8 gradually decreases. Then, when Va becomes a potential lower than the potential of Nout by Vbe, a current starts to flow in Q8, and accordingly, the collector current I16 of Q6 decreases and the collector potential Vc of Q6 increases. When Vc rises, Q10 turns on, Nout becomes H level, the base current of Q8 increases, and the collector current of Q8 further increases. When the emitter internal resistances of Q5 and Q6 are r1 and r2, respectively, Q16 turns off when R / (r1 + r2) = 1.

On the other hand, when Q6 turns off, I13 flows through R1 and Q5, and the collector potential Vd of Q5 decreases, so Q1 turns off, Pout becomes L level, and Q3 turns off, and C11 No current flows through.

Therefore, Va is a voltage as the potential of Nout rises.
Along with Vx (= R ・ I16), Q3 and Q4 are off, so Vb also rises by Vx and Va and Vb do not change until the polarity of Pin and Nin is reversed again.

By repeating such an operation, the signal delayed by ΔT with respect to the input signal is output from the variable delay circuit 12. Here, if the value of Vx is set to a large value, the effect of Vbe of Q1, Q3, Q8, Q10 can be reduced by that amount, but the time required to invert Pout, Nout also increases, so consider them. The designed design is required.

Further, by inputting an error signal from the outside to the variable delay circuit 12, controlling the value of the current I13 and the value of Vx by this error signal, an accurate delay amount ΔT can be obtained. .

With the clock signals having the same duty thus obtained, the switch S5 shown in FIG. 2 is opened and closed, and the capacitor C1 is charged and discharged by the currents I2 and I3, whereby a triangular wave can be obtained. The current I3 is 2.I2
Set to. However, the triangular wave TRI thus obtained does not always obtain a desired peak value due to variations in internal elements. Therefore, the comparators 22 and 23 compare the signals V10 and V90 having the levels of 10% and 90% of the desired peak value with the level of the triangular wave TRI.

FIG. 5 is a diagram showing the comparison results P10, P90 of the triangular waves TRI, V10, V90 and the comparators 22, 23. Signal P10
Is input to CP14 whose details are shown in FIG. 6A. CP14 is
By using the current source Io and the current source 0.9Io, the signal P10
Stable only when the duty of becomes 9: 1. Du16
Generates an error current ΔI according to the output of CP14.
Is fed back to the variable delay circuit 12 to control the duty of the triangular wave, that is, its offset value.

Further, the signal P90 obtained by the comparator 23
Is input to CP15 shown in FIG. 6B together with P10. CP15
P10 by using current source 1.8I0 and current source Io
Stable only when the duty of P90 and P90 both become 9: 1. The PP17 generates an error voltage ΔV according to the output of the CP15, and controls the peak values of the triangular wave TRI by controlling the current sources I2 and I3 by this ΔV.

The comparator 24 for comparing the signal V22 shown in FIG. 2 with the triangular wave TRI is a starting circuit for quickly converging the triangular wave when the triangular wave is generated, and locks the triangular wave TRI to its lower peak value every cycle. By doing so, it plays the role of a jitter correction circuit that improves the jitter of the output signal. However, this signal V22 is set to a level that does not disturb the triangular wave TRI.

As described above, the triangular wave generation circuit 1 shown in FIG.
By using, a stable triangular wave TRI can be obtained, and a PWM output can be obtained by comparing this triangular wave TRI with an analog signal obtained by D / A converting the input data D8 to D1. However, as described above, the DAC 4 has a level transition time, and when the frequency of the input clock signal is high, there is a problem that the pulse width of the obtained PWM signal becomes large.

An image processing apparatus according to an embodiment of the present invention will be described below in detail with reference to the drawings.

[0029]

First Embodiment [Structure] FIG. 7 is a block diagram showing the structure of a signal generation circuit according to an embodiment of the present invention. 1 to 6 are denoted by the same reference numerals and detailed description thereof will be omitted.

The image processing apparatus shown in FIG. 7 includes a switch S1 and a selector 10, a true DAC 4 that outputs the true analog value of input data, a complement DAC 5 that outputs the complementary analog value, comparators 2 and 3, It is composed of logic circuits 6 to 9, a triangular wave generating circuit 1, etc., and outputs a PWM signal whose pulse width grows from the center by using a triangular wave TRI synchronized with the signal SCK. Also, the most significant bit D8 of the input data
Is changed with respect to the same bit immediately before (one clock before), by switching the logic level of the input data and the outputs of the true DAC4 and the complement DAC5 at the rising timing of the signal SCK, the DAC The accurate PWM output is obtained without being affected by the level transition time of.

The DF / F7 synchronized with the SCK inverted by the inverter 9 inputs the most significant bit D8 'of the input data one clock before input to the true DAC 4 and the complement DAC 5. E
The XOR circuit 8 EXORs the Q output of DF / F7 and D8, and the EXOR result is input to DF / F6 synchronized with SCK. That is, EXO
The R circuit 8 EXORs D8 'and D8 to determine whether or not there is a change in both data. Then, the switch S1 and the selector 10 are controlled at the rising timing of the signal SCK. D8 and D
If 8'is different, the selector 10 selects the data obtained by inverting each bit of the input data by the inverter 9, and the switch S1 selects the output of the comparator 3.

[Operation] FIG. 8 is a timing chart showing an operation example of the present embodiment. FIG. 8A shows input data,
(b) shows the clock signal SCK.

First, the operation of the PWM circuit shown in FIG. 1 will be described. When the output of DAC4 suddenly changes from the level corresponding to '00' to the level corresponding to'FF 'as in the fourth SCK section shown in Fig. 8, the level of triangular wave TRI becomes'FF'. It is desirable that the PWM output (Fig. 8 (d)) becomes L level when the corresponding level is exceeded. However, as mentioned above,
Since the output of DAC4 does not reach the level corresponding to'FF 'immediately, even after the level of TRI exceeds the level corresponding to'FF', the section shown by the shaded area in Fig. 8 (d) is the PWM output. Will remain at the H level.

Next, the operation of the PWM circuit shown in FIG. 7 will be described. It is assumed that the outputs of DF / F6 and 7 are L level in the initial state, the selector 10 selects the input data as it is, and the switch S1 selects the comparator 2 (true DAC 4) side.

In the first SCK section shown in FIG. 8, DF / F6
Since the output of is at L level, the input data remains unchanged from DAC4 and DAC5.
Input to switch S1 selects the true DAC4 side,
Obtain the first output shown in (f). Next, in the second SCK section, since the output of DF / F7 is at the H level and D8 is at the L level, the output of DF / F6 is at the H level at the rising edge of the second SCK. Therefore, the input data in which each bit is inverted is input to the DACs 4 and 5, and the switch S1 selects the side of the comparator 3 (complement DAC5), so that the second output of FIG. Next, the third SCK section is also D8 and DF
Since the outputs of / F7 are both at the H level, the input data is directly input to DACs 4 and 5, and the switch S1 selects the true DAC4 side. Therefore, the third output shown in FIG.

Then, in the fourth SCK section, DF / F7
Since the output of D becomes L level with respect to the H level, the output of DF / F6 becomes H level at the fourth rising of SCK.
Therefore, the input data in which each bit is inverted is input to the DACs 4 and 5, and the switch S1 selects the complement DAC 5 side. In other words, in the third to fourth SCK section, the input data changes abruptly from'FF 'to' 00 ', but there is no change in the data input to DAC4 and 5, respectively. The output will not change either. Therefore, the TRI level is'F
PWM output when the level corresponding to F'is exceeded (Fig. 8 (f))
Becomes L level.

Next, also in the fifth SCK section, the output of DF / F7 is at the L level while the output of DF / F7 is at the H level, so the output of DF / F6 remains at the H level and each bit is The inverted input data is input to DACs 4 and 5, and switch S1 switches to complement DAC5.
Choose the side. Therefore, the fifth output shown in FIG.

As described above, the output level range of the antilogarithmic DAC4 corresponds to the range of "00" to "7F" of the input data, and the complement DAC5
The output level range of corresponds to between '80'and'FF'. Therefore, the level transition region of the true DAC4 also corresponds to the maximum between '00' and '7F', and the level transition region of the complementary DAC5 also corresponds to the maximum between '80'and'FF'. That is, the maximum value of the level transition amount of the DAC in the PWM circuit shown in FIG. 7 is half that of the DAC of the PWM circuit shown in FIG. 1, and the effect of the level transition time on the PWM output is greatly reduced. be able to. Note that the output level range of the true DAC4 and the complement DAC5 is the first most significant bit D8 of the input data.
It changes depending on whether H is at H level or L level.

As described above, according to this embodiment, the true number DAC and the complement DAC are provided, and each bit of the data input to these DACs is non-inverted according to the change of the most significant bit of the input data. The maximum level transition amount of the DAC can be halved by reversing and selecting the output of any of the DACs. Therefore, the DAC level transition time is PWM
The effect on the output can be greatly reduced, and more accurate PWM output can be obtained. It is especially effective in high-speed PWM circuits.

[0040]

Second Embodiment Hereinafter, an image processing apparatus according to a second embodiment of the present invention will be described. In the second embodiment,
The same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

FIG. 9 is a block diagram showing an example of the configuration of the PWM circuit of the second embodiment. In synchronization with the input clock signal SCK (FIG. 11 (a)), the left and right ends of the SCK cycle on the time axis are used as references. This is a type of PWM circuit in which the output pulse width changes and the pulse width grows from the left and right. The EXOR circuit 20 and the AND circuit 19 are for controlling the switch S1 based on the signals RLS, RS, TS to select the output.
The output of the comparator 3 is selected when the output of the D circuit 19 is at the L level, and the output of the comparator 2 is selected when it is at the H level.

FIG. 10 is a block diagram showing a configuration example of the triangular wave generating circuit 1 shown in FIG. 9, which includes comparators 22 to 24, a buffer 13, charger pumps (CP) 14 and 15, and error signal generating circuits (Du, PP). ) 16 and 17, capacitor C1, current sources I1 to I
It consists of three parts. V10, V90, and V22 input to the comparators 22 to 24 are the same as the signals shown in FIG. 2, and the signal CK for opening / closing the switch S5 is the output of the divide-by-2 circuit 11 shown in FIG. 9 (FIG. 11 (b)). Is.

Comparator 22 in the circuit shown in FIG.
The circuits such as 24, buffer 13, CP14 and 15, Du16 and PP17 are similar to the configuration shown in FIG. 2, and the difference from the configuration shown in FIG. 2 is that the error current signal Δ of the offset control loop is
Only I was changed to flow to the capacitor C1.
Therefore, the offset of the triangular wave TRI is controlled by controlling the charging / discharging current of the capacitor C1 by the error current signal ΔI. Since all other configurations are the same, by controlling the switch S5 with the signal CK having a double cycle of SCK, a triangular wave TRI having a double cycle of SCK can be obtained.

Next, the process of growing the pulse width from the left and right will be described.

First, when the pulse width is to be grown from the left (may be referred to as "left growth" hereinafter), the signal RLS is set to H level, the signal CK is input to the signal TS, and
Set RS to L level. As shown in Fig. 11 (c), the triangular wave TRI
Assuming that the rising slope of is an odd pixel (OD) and the falling slope is an even pixel (EV), as shown in Figs. 11 (d) and (e), in the case of left growth, the true DAC4 on the OD side of TRI is And the positive pulse obtained by comparator 2 is the complement D on the EV side.
The negative pulse obtained by the AC5 and the comparator 3 is selected, and the PWM signal whose pulse width grows is output from the left.

On the other hand, when the pulse width is to be grown from the right (hereinafter sometimes referred to as "right growth"), the signal RLS is set to H level, the signal CK is input to the signal TS, and
Set RS to H level. The switch S1 operates in the opposite direction to that during left growth, and as shown in FIGS. 11 (f) and 11 (g), the triangular wave TRI
On the V side, a positive pulse obtained by the true DAC 4 and the comparator 2 is selected, and on the OD side, a negative pulse obtained by the complementary DAC 5 and the comparator 3 is selected, and a PWM signal whose pulse width grows is output from the right.

When the data corresponding to the output change of the antilogarithmic DAC 4 shown in FIG. 11 (h) is input, the shaded area shown in FIG. 11 (i) or (j) is reduced depending on the level transition time of the DAC. The output PWM signal is output.

FIG. 12 is a block diagram showing a configuration example of a PWM circuit for solving this problem, which is a combination of the circuit shown in FIG. 7 and the circuit shown in FIG. That is, by switching the selector 10 and the switch 1 with the change of the most significant bit D8 of the input data, the polarity of the input data and the outputs of the two comparators are selected to obtain an accurate PWM signal. .

FIG. 13 is a timing chart for explaining the operation of the PWM circuit shown in FIG. 12, which is the antilogarithmic DAC shown in FIG. 13 (c).
The operation when the data corresponding to the output change of 4 is input will be described.

In the initial state, D8 and DF / F6 and
The output of 7 is assumed to be L level. The first SC shown in Figure 13
In the K section, the AND circuit 19 is used to obtain the PWM signal for right growth.
Output is at L level ((e) in the figure). DF / F6 output is L
Since it is at the level, the input data is directly input to the DACs 4 and 5, and the switch S6 selects and outputs the output of the AND circuit 19 as it is. Therefore, the switch S1 selects the output of the comparator 3 (complement DAC5 side) ((f) in the same figure), and obtains the first output in FIG. 13 (g).

Next, in the second SCK section, P of left growth is
The output of the AND circuit 19 is at L level to obtain the WM signal.
Since the output of DF / F7 becomes H level with respect to L level, the output of DF / F6 becomes H level at the second rising of SCK. Therefore, the input data with each bit inverted is DA
Input to C4 and 5, switch S6 outputs the output of inverter 21 (A
The inverted output of the ND circuit 19) is selected and output, and the switch S1 selects the output of the comparator 2 (on the side of the true number DAC4) to obtain the second output of FIG. 13 (g).

Next, in the third SCK section, P of left growth
The output of the AND circuit 19 is at the H level to obtain the WM signal.
Since the output of DF / F7 is at the H level with respect to the L level, the output of DF / F6 is at the H level at the third rising of SCK. Therefore, the input data with each bit inverted is DA
Input to C4 and 5, switch S6 selects and outputs the output of inverter 21, switch S1 selects complement DAC5 side, and
Get the third output of 13 (g).

Next, in the fourth SCK section, P for right growth
The output of the AND circuit 19 is at the H level to obtain the WM signal.
Since the outputs of D8 and DF / F7 both become L level, the output of DF / F6 becomes L level at the fourth rising of SCK. Therefore, the input data is directly input to the DACs 4 and 5, and the switch S6 selects and outputs the output of the AND circuit 19,
The switch S1 selects the true number DAC4 side to obtain the fourth output in FIG. 13 (g).

Next, in the fifth SCK section, P of left growth
The output of the AND circuit 19 is at the H level to obtain the WM signal.
Since the output of DF / F7 is at the H level with respect to the L level, the output of DF / F6 is at the H level at the fifth rising edge of SCK. Therefore, the input data with each bit inverted is DA
Input to C4 and 5, switch S6 selects and outputs the output of inverter 21, switch S1 selects complement DAC5 side, and
Get the fifth output of 13 (g).

Next, in the sixth SCK section, the left growth P
The output of the AND circuit 19 is at L level to obtain the WM signal.
Since the outputs of D8 and DF / F7 both go low, the output of DF / F6 goes low at the sixth rise of SCK. Therefore, the input data is directly input to the DACs 4 and 5, and the switch S6 selects and outputs the output of the AND circuit 19,
The switch S1 selects the complement DAC5 side, and the sixth output in FIG. 13 (g) is obtained.

As described above, according to the present embodiment, even in the PWM circuit in which the pulse width grows left and right, the problem that the pulse width decreases due to the level transition time of the DAC can be solved, and the accurate pulse width PWM output can be obtained.

[0057]

Third Embodiment Hereinafter, an image processing apparatus according to a third embodiment of the present invention will be described. In the third embodiment,
The same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the PWM circuit shown in FIG. 7 of the first embodiment, the most significant bit D8 of the input data is EX.
The OR circuit 8 and DF / F7 are allowed to pass therethrough, and the selector 10 is controlled according to the result. Therefore, due to the delay in the switching timing of the selector 10, a certain amount of time is required until correct data is input to both DACs. Then, in order to prevent the influence of this delay, it is necessary to perform delicate timing adjustment between the signals. The third embodiment is for avoiding this delicate timing adjustment.

FIG. 14 is a block diagram showing an example of the configuration of the PWM circuit of the present embodiment, in which a triangular wave TRI synchronized with the input clock signal SCK is used to obtain a PWM signal whose pulse width grows from the center. That is, the most significant bit D8 of the input data
At H level, the remaining bits D7 to D1 are inverted and DAC4
And 5 to the output of comparator 3 (complement DAC5
Side) and the L level, the remaining bits D7 to D1
Is input to the DACs 4 and 5 as it is, and the output of the comparator 2 (on the side of the true number DAC4) is selected. The most significant bit input of DAC4 and DAC5 is fixed to L level.

With such a configuration, the influence of the level transition time of the DAC can be halved and a more accurate PWM output can be obtained with a simpler configuration than that of the first embodiment. it can.

Further, as in the case of the above-described first embodiment, the PWM circuit (FIG. 12) of the second embodiment can be simplified and the same operation can be performed. Figure 15 shows the PWM of this embodiment
In the block diagram shown in the circuit configuration example, the input clock signal SC
A triangular signal TRI synchronized with K is used to obtain a PWM signal whose pulse width grows from the left and right, and D8 directly controls the selector 10 and the switch S6. When D8 is H level, the selector 10 selects the output of the inverter 9,
The switch S6 selects the output of the inverter 21. Also, D8
Is at the L level, the selector 10 selects and outputs the input data as it is, and the switch S6 outputs and selects the AND circuit 19.

With this structure, the same effect as that of the second embodiment can be obtained.

[0063]

[Other Embodiments] Even if the present invention is applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), an apparatus (for example, a copying machine) Machine, facsimile machine, etc.).

[0064]

As described above, according to the present invention,
It is possible to provide a signal generation circuit and method that can obtain a more accurate pulse width signal corresponding to input data.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of a PWM pixel modulation circuit,

FIG. 2 is a block diagram showing a configuration example of a triangular wave generation circuit,

FIG. 3 is a circuit diagram for explaining the operation of the variable delay circuit shown in FIG.

FIG. 4 is a diagram showing waveforms at various parts of the variable delay circuit shown in FIG.

[FIG. 5] Triangle waves TRI, V10, V90 and comparison result P1 shown in FIG.
Figure showing 0, P90,

6A is a circuit diagram showing a configuration example of CP14 shown in FIG.

6B is a circuit diagram showing a configuration example of CP15 shown in FIG.

FIG. 7 is a block diagram showing a configuration example of a signal generation circuit according to an embodiment of the invention.

8 is a timing chart showing an operation example of the circuit shown in FIG.

FIG. 9 is a block diagram showing a configuration example of a PWM circuit according to a second embodiment of the present invention,

10 is a block diagram showing a configuration example of the triangular wave generation circuit 1 shown in FIG.

11 is a timing chart showing an operation example of the circuit shown in FIG.

12 is a block diagram showing a configuration example of a PWM circuit for solving the problem of the circuit shown in FIG.

13 is a timing chart for explaining the operation of the circuit shown in FIG.

FIG. 14 is a block diagram showing a configuration example of a PWM circuit according to a third embodiment of the present invention,

FIG. 15 is a block diagram showing a configuration example of another PWM circuit of the third embodiment.

Claims (13)

[Claims] 1. A signal generation circuit for generating a signal having a pulse width corresponding to input data in synchronization with an input clock, comprising: generating means for generating a reference signal from the input clock; Inverting means for inverting each bit of data, first selecting means for selecting the input data or the output of the inverting means, and the data selected by the first selecting means into a signal corresponding to its exact value. First comparing means for converting and comparing with the reference signal, and second comparing means for converting the data selected by the first selecting means into a signal corresponding to its complement value and comparing with the reference signal. A second selection means for selecting one of the comparison results obtained by the first and second comparison means, and a data selected by the first selection means one cycle before the input clock. And a predetermined bit, in accordance with the predetermined bit of the input data, the signal generating circuit, characterized in that a control means for controlling said first and second selection means. 2. The signal generation circuit according to claim 1, wherein the predetermined bit is the most significant bit. 3. The control means causes the first control means to select the input data when the most significant bit of the selected data and the most significant bit of the input data match each other. The second selecting means is caused to select the comparison result obtained by the first comparing means, and when the two most significant bits do not match, the first controlling means is caused to select the output of the inverting means. The second selection means is caused to select the comparison result obtained by the second comparison means.
The signal generation circuit described in. 4. The control means holds a first holding means for holding the most significant bit of the selected data in units of one cycle of the input clock, an output of the first holding means and the input data. And a second holding means for holding the output of the arithmetic means in units of one cycle of the input clock, the output means of the second holding means 3. The signal generation circuit according to claim 2, which controls the first and second selection means. 5. The signal generation circuit according to claim 1, wherein the signal generation circuit generates a signal in which a pulse width grows in both directions from near the center of the pulse width in accordance with the input data. The signal generation circuit described in 1. 6. A signal generation circuit for generating a signal having a pulse width corresponding to input data in synchronization with an input clock, wherein the reference signal is generated from a signal obtained by dividing the input clock. Means, an inverting means for inverting each bit of the input data, a first selecting means for selecting the input data or an output of the inverting means, and a data selected by the first selecting means as an exact numeric value thereof. And a first comparing means for converting the signal into a signal corresponding to and comparing with the reference signal, and converting the data selected by the first selecting means into a signal corresponding to its complement value and comparing with the reference signal. Second comparing means, second selecting means for selecting one of the comparison results obtained by the first and second comparing means based on a predetermined signal, and one cycle before the input clock Controlling the first selecting means and controlling the selection of the second selecting means in accordance with a predetermined bit of the data selected by the first selecting means and the predetermined bit of the input data; A signal generation circuit having a control means for switching a predetermined signal. 7. The signal generation circuit according to claim 6, wherein the predetermined bit is the most significant bit. 8. The control means causes the first control means to select the input data when the most significant bit of the selected data and the most significant bit of the input data match each other. The second selecting means is caused to select the comparison result obtained by the first comparing means, and when the two most significant bits do not match, the first controlling means is caused to select the output of the inverting means. 7. The second selection means is caused to select the comparison result obtained by the second comparison means.
The signal generation circuit described in. 9. The control means comprises: first holding means for holding the most significant bit of the selected data in units of one cycle of the input clock; output of the first holding means; and the input data. And a second holding means for holding the output of the arithmetic means in units of one cycle of the input clock, the output means of the second holding means 8. The signal generation circuit according to claim 7, which controls the first and second selection means. 10. The signal generating circuit generates a signal in which the pulse width grows from the vicinity of one end of the pulse width toward the other end in accordance with the input data. 9. The signal generation circuit described in any one of 9. 11. An image processing apparatus comprising the signal generating circuit according to claim 1, and outputting a signal having a pulse width according to input image data. 12. A signal generation method for generating a signal having a pulse width corresponding to input data in synchronization with an input clock, wherein the input data or data obtained by inverting each bit of the input data is generated. A first selecting step of selecting, a first converting step of converting the data selected in the first selecting step into an exact value signal corresponding to its exact value, a reference signal generated from the input clock, and the A first comparing step of comparing with an exact value signal, a second converting step of converting the data selected in the first selecting step into a complementary value signal corresponding to its complementary value, the reference signal and the complementary value A second comparison step of comparing with a numerical signal, a second selection step of selecting one of the comparison results obtained in the first and second comparison steps, and the input clock A control step for controlling the selection of the first and second selection steps according to a predetermined bit of the data selected in the first selection step one cycle before and a predetermined bit of the input data. A signal generating method comprising: 13. A signal generation method for generating a signal having a pulse width corresponding to input data in synchronization with an input clock, wherein the input data or data obtained by inverting each bit of the input data is generated. A first selecting step of selecting, a first converting step of converting the data selected in the first selecting step into a true value signal corresponding to the true value, and a signal generated by dividing the input clock. A first comparing step of comparing the reference signal and the exact value signal, a second converting step of converting the data selected in the first selecting step into a complementary value signal corresponding to its complementary value, A second comparison step of comparing a reference signal with the complement value signal, and selecting one of the comparison results obtained in the first and second comparison steps based on a predetermined signal A second selection step, a selection of the first selection step according to a predetermined bit of the data selected in the first selection step one cycle before the input clock and the predetermined bit of the input data And a control step of switching the predetermined signal for controlling the selection in the second selection step.