JPH0918365A - Radio communication equipment - Google Patents

Abstract

PURPOSE: To eliminate the need of preliminary data input and to reduce reception faults by the unwanted radiation of clock signals with simple constitution by switching the frequency of the clock signals with a prescribed interval at the time of detecting reception signals. CONSTITUTION: A control means 50 synchronizes a control operation by the clock signals outputted from a clock oscillation means 30 and a shift control means 51 is activated when a reception frequency is changed. When the reception signals from a signal detection means 35 are confirmed, the shift control means 51 controls a shifting means 34 and grounds the other terminal of a capacitor 32. Thus, a clock frequency is shifted for a prescribed range corresponding to the capacitance of the capacitor 32. In a state where the clock frequency is shifted, the reception signals in the reception frequency are not present when the reception signals are the higher harmonic of the clock signals. When the reception signals are external signals, the reception state of the signal detection means 35 is continued.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wireless communication device, and more particularly, to a wireless communication device for reducing a reception failure due to unnecessary radiation of harmonics contained in a clock signal.

[0002]

2. Description of the Related Art A radio communication device is provided with a signal system for inputting a voice signal obtained by modulating a transmission signal and transmitting it from an antenna or demodulating a reception signal to a speaker, and a control system for controlling the signal system. ing.

In recent years, a digital circuit has been used in the above control system, and the digital circuit is naturally equipped with a clock oscillating means for establishing synchronization of its own control operation. The clock signal obtained from the clock oscillating means may generate various harmonics and may cause reception failure during reception.
For example, when a 4 MHz clock signal is used and a harmonic of 464 MHz, which is 116 times that frequency, is generated, at this time, a 464 MHz signal having the same frequency as the above-mentioned harmonic is received as a reception signal. If so, the above harmonics are mixed in the received signal.

When the above harmonics are mixed in the received signal as described above, the received signal is reproduced and the obtained received voice is drowned out, or a beat phenomenon occurs in the received voice. Therefore, Japanese Patent Laid-Open No. 62-272629 discloses a technique of changing the frequency of a clock signal according to the reception frequency so that its harmonics do not match the reception frequency.

According to the contents described in this publication, control data related to a specific reception frequency is stored, and when the specific frequency is received, a clock signal of the clock signal is generated using the related control data. I try to shift the frequency.

Further, Japanese Patent Laid-Open No. 06-338813 discloses a technique of modulating the clock signal using a modulation signal and changing the frequency of the clock signal when the received demodulation signal includes the modulation signal. Have been described.

[0007]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention JP-A-62-272629
According to the description of the publication, it is necessary to collect and store the control data in advance, which is troublesome, and when the clock frequency shifts due to the influence of temperature, the frequency resulting from the shift is a signal input from the outside. May cause interference with.

Further, according to the contents described in Japanese Patent Laid-Open No. 06-338813, a modulating signal oscillating means for temporarily modulating a clock signal, a clock signal modulating means, and a modulating signal detecting means are required, and the structure is complicated. As a result, cost disadvantages will occur.

Further, since the clock is modulated, there is a possibility that it will affect other circuits and the like, which will limit the circuit design. The present invention has been proposed in view of the above-mentioned conventional circumstances, and provides a wireless communication device that does not require preliminary data input, has a simple structure, and reduces reception interference due to unnecessary radiation with a large cost advantage. The purpose is to do.

[0010]

In order to achieve the above object, the present invention employs the following means. That is, as shown in FIG. 1 (a), in a wireless communication device including a control means 50 for synchronizing a control operation with a clock signal output from a clock oscillation means 30 and a signal detection means 35 for detecting a received signal, When the signal detecting means 35 detects a received signal, a shift control means 51 for controlling the shift means 34 to switch the frequency of the clock signal at a predetermined interval, and a shift means 34 controlled by the shift control means 51. It is configured to include.

The shift control means 51 determines whether or not there is a detection signal from the signal detection means 35, and at the same time, a signal / timer determination portion 51a for determining whether or not the timer 51b is operating, and the above-mentioned. It is configured to include a timer 51b that defines a predetermined interval.

Further, in addition to the above configuration, as shown in FIG. 1B, an initial state storage means 60 for storing an initial state when the signal detection means 35 is not detecting a signal, and a frequency of the clock signal. Shift means 34 after the change in
It is also possible to add a state determining means 54 for ending the operation of the shift control means 51 when the state is the same as the initial state.

[0013]

With the above structure, when the signal detecting means 35 detects the received signal of the specific frequency, the shift controlling means 51 controls the shift means 34 to change the frequency of the clock signal. When the frequency of the clock signal is changed in this way, when the received signal is a harmonic of the clock signal, the received signal is no longer detected by the signal detection means 35, and the received signal detected before the change is the clock signal. It is determined to be due to harmonics, and the frequency of the clock signal is set to the changed frequency. As a result, even if there is a received signal from the outside at the above-mentioned specific frequency, it is possible to eliminate the influence of unnecessary radiation from the clock signal at this frequency (see FIG. 6 (a)).

On the other hand, even if the frequency of the clock signal is changed by the shift means 34, when the received signal is an externally input signal, the signal detecting means 35 continues to detect the received signal. Therefore, after the timer 51b has timed out, the shift means 34 is controlled again to set the original clock frequency, and after the subsequent timed-out, the shifted frequency is set again. Will be repeated.

However, even in this case, when there is no received signal (when the received signal is only a signal from the outside, when the signal from the outside is interrupted, the signal from the outside is a harmonic of the clock signal). When a wave is mixed, the signal from the outside is cut off and the frequency of the clock signal is changed, so that when the harmonic is not input), the clock frequency affects the reception. Certainly set to a non-existent frequency (Fig. 6
(b)).

In the above configuration, when the received signal is an external signal, the shift means 34 alternately sets the frequency of the clock signal to two states until the state where there is no received signal is formed. Control becomes redundant.

Therefore, the state of the shift means 34 is stored as the initial state when there is no received signal in the initial state storage means 60. When the received signal is detected in this state,
When the shift means 34 is controlled to change the clock frequency as described above, the state determination means 54 determines at this stage whether or not the state is the same as the stored content. As a matter of course, since the state has changed from the initial state, the timer 51b is activated and the signal detecting means 35 detects the receiving state again.

At this time, when the received signal is a harmonic of the clock signal, the detection by the signal detection means 35 is eliminated by the above change, so the current state is stored in the initial state storage means 60 and the processing is terminated (FIG. 6 (a)). )).

On the other hand, when the received signal is an external signal, the detection by the signal detecting means 35 still continues even if the frequency is changed, so that the shift means 34 is controlled again to return to the original state. Become. Since this state is the same as the initial state (state of the shift means 34 when there is no received signal) stored in the initial state storage means 60, the shift operation ends. This enables reception of the clock signal without unnecessary radiation.

[0020]

FIG. 2 is a block diagram of one embodiment of the present invention.
FIG. 3 is a flow chart of the present invention showing the operation procedure of the embodiment shown in FIG.

The antenna 10, the high frequency amplification means 12, the intermediate frequency conversion means 14, the local oscillation means 16, the intermediate frequency amplification means 17, the demodulation means 18, the low frequency amplification means 20, and the speaker 22 constitute a reception system.

The control system controls various settings and storages of the reception system, for example, the reception frequency band and the reception frequency, and the control circuit 50 is synchronized with a clock signal. Has become Therefore, the control means 50 uses the clock oscillation means 30.
It has a structure with the exterior.

A frequency shift means 34 is further connected to the clock oscillation means 30 via one end of a capacitor 32, and the frequency shift means 34 is a shift control means 51.
Has a switch function for opening the other end of the capacitor 32 or grounding.

On the other hand, the output of the demodulating means 18 is inputted to the signal detecting means 35, and when there is a received signal, the signal detecting means 35 detects the received signal. Further, the control means 50 includes a signal / timer discrimination section 5
1a and timer 51b are incorporated and operate as described below.

In the above configuration, the frequency change confirmation means 5
5 confirmed that the reception frequency was changed by dialing etc. (The clock frequency was set to 4.00MHz as shown in Fig. 6)
By doing so, the shift control means 51 is activated and processing is started (time t _{0 as} shown in FIGS. 6A, 6B, and 6C).

First, the signal of the shift control means 51 /
When the timer discriminating section 51a confirms the received signal from the signal detecting means 35 and confirms that the timer 51b is not operating, it controls the shift means 34 to ground the other end of the capacitor 32. As a result, the clock frequency is shifted by a predetermined range corresponding to the capacity of the capacitor 32 (the clock frequency of the shift result is 4.01 MHz as shown in FIG. 6). The timer 51b is activated at the same time as this frequency shift, and the state where the frequency is shifted is maintained for a predetermined time (for example, 500 ms) (FIG. 3, steps S1 to S4).

When the received signal is a harmonic of the clock signal and the state in which the clock frequency is shifted is formed as described above, the received signal at the received frequency becomes as shown in FIG. 6 (a). Since there is no more, the operation ends (FIG. 3, step S2: Y → S1: N → S5, FIG. 6 (a) time t ₁₀ ). As a result, the reception signal based on the harmonics of the clock signal is not received at the set reception frequency.

When the received signal is an external signal, FIG. 6 (b)
As shown in, even if the frequency of the clock is once shifted, the receiving state of the signal detecting means 35 continues. Therefore, after the timer 51b has timed out (step S1 → S2: N in FIG. 3), the clock frequency is shifted again (the other end of the capacitor 32 is opened contrary to the above), and the timer 51b is activated again. To start. Therefore,
The frequency of the clock signal alternates between the initial state and the shifted state in a time division manner.

In the above, when the received signal is purely from the outside (when harmonics of the clock signal are not mixed), the time t ₁ at which the received signal is no longer detected is shown in FIG.
Continue until (b).

When the received signal is composed of the harmonics of the external signal and the clock signal mixed therein, and when the frequency of the clock signal is not changed from the initial state as described above (for example, time t ₁ ). Therefore, even if the signal from the outside is interrupted, the harmonics of the clock signal remain, so that the reception continues even at the next timer cycle, and within this cycle (for example, time t ₂₀ ), Figure 6
As in the case shown in (a), the frequency of the clock signal is shifted and the process ends. As a result, a state is formed that is not affected by the harmonics of the clock signal.

In the above configuration, as described above, when the received signal is a signal coming from the outside, the frequency of the clock signal is such that the initial state and the shifted state are alternately repeated. Waves or signals from the outside) will continue until the operation disappears.

Therefore, it is conceivable to configure the control means 50 as shown in FIG. 4 and operate it as shown in FIG. That is, first, when the signal detection means 35 does not detect the received signal, the initial state of the shift means 34 is stored in the initial state storage means 60 by the storage control means 53 (FIG. 5, step S16).

When the signal detecting means 35 detects the received signal and the timer 51b is not operating, the signal / timer discrimination section 51a controls the shifting means 34 to shift the frequency of the clock signal ( FIG. 5, step S1
3), start the timer 51b (FIG. 5, step S1)
5). There is a step for discriminating the state of the shift means 34 between steps S13 and S15, and this step will be described later.

As a result, when the received signal is a harmonic of the clock signal, the received signal is no longer detected regardless of whether the timer 51b is activated. in this way,
When the received signal is no longer detected, the current state of the shift means 34 is stored in the initial state storage means 6 by the storage control means 53.
0 (FIG. 5, step S16), whereby the clock frequency is shifted from the beginning at the next reception (when the reception is temporarily stopped, the transmission state is set, and then the reception state is made again). ing.

When the received signal is an external signal, the state in which the received signal is detected by the signal detecting means 35 continues even if the clock frequency is shifted as shown in step S13 of FIG. Therefore, even if the timer 51b is once set as described above and the time is over, the shift control means 51 is activated again at the stage of step S13 to shift the clock frequency (return to the initial clock frequency). .

Here, it is determined whether or not the state determination means 54 is activated and the state of the shift means 34 is the state stored in the initial state storage means 60 (FIG. 5, step S1).
4). Since the state of the shift means when there is no received signal is stored in the initial state storage means 60, when the state of the shift means 34 is the state stored in the initial state storage means 60, a signal from the outside is received. Signal detection means 35
Means that the timer has been started, and therefore the timer ends without starting the timer again (time t in FIG. 6 (c)).
₃₀ ).

The activation of the shift control means 51 in the above embodiment is not limited to the change of the reception frequency,
It may be activated even when the transmission state is switched to the reception state or when the power is turned on. Further, the signal detecting means 35 in the above embodiment is not limited to the configuration in which the received signal is detected from the output of the demodulating means 18, and for example, the output of the intermediate frequency amplifying means 17 may be input, or after demodulation. Any type may be used as long as the received signal can be detected, such as detection from a noise component.

[0038]

As described above, the present invention has the effect of reducing the reception disturbance due to unnecessary radiation of the clock signal with a simple configuration in which the frequency of the clock signal is shifted when the received signal is input. Furthermore, if the state without unnecessary radiation is stored as the initial state, the frequency can be shifted at a higher speed.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a block diagram of one embodiment of the present invention.

FIG. 3 is a flowchart of FIG. 2;

FIG. 4 is a block diagram of another embodiment of the present invention.

5 is a flowchart of FIG. 4.

FIG. 6 is a time chart showing the operation of the present invention.

[Explanation of symbols]

 30 clock oscillating means 34 shift means 35 signal detecting means 50 control means 51 shift control means 51a signal / timer discriminating means 51b timer 54 state discriminating means 60 initial state storing means

Claims (4)

[Claims] 1. A radio communication device comprising a control means for synchronizing a control operation with a clock signal output from a clock oscillating means and a signal detecting means for detecting a received signal, wherein the signal detecting means detects the received signal. At this time, a wireless communication device comprising shift control means for controlling the shift means for switching the frequency of the clock signal at predetermined intervals, and shift means controlled by the shift control means. 2. The shift control means determines whether or not there is a detection signal from the signal detection means, and a signal / timer determination portion for determining whether or not a timer is operating, and the predetermined interval. The wireless communication device according to claim 1, comprising a prescribed timer. 3. A wireless communication device comprising control means for synchronizing a control operation with a clock signal output from a clock oscillating means and signal detecting means for detecting a received signal, wherein the signal detecting means does not detect a signal. Initial state storage means for storing an initial state, shift control means for controlling the shift means to switch the frequency of the clock signal at a predetermined interval when the signal detection means detects a received signal, and the clock signal After the frequency is changed, the wireless device is provided with a state determination means for ending the operation of the shift control means when the state of the shift means is the same as the initial state and a shift means controlled by the shift control means. Communication equipment. 4. A signal / timer discriminating section for discriminating whether or not the shift control means detects a detection signal from the signal detecting means, and discriminating whether or not a timer is operating, and the predetermined interval. The wireless communication device according to claim 3, comprising a prescribed timer.