JPH0918342A - A/d converter - Google Patents

Abstract

PURPOSE: To provide a highly accurate A/D converter operated by a low power supply voltage by making a current mirror circuit constituting a tree structure to be formed of a current mirror circuit of only one type of N type or P type. CONSTITUTION: The tree structure of three stages is constituted of only the N type current mirror circuit constituted of an N channel MOS type field effect transistors. A first current source CS1 is connected to the input terminal of a first stage current mirror circuit CM1 and a second current source CS2 is connected to an output terminal. The second current source CS2 is connected to the output terminal of a second stage current mirror circuit CM2. A third current source CS3 and a comparator CP are connected to the output terminal of a third stage current mirror circuit CM3. The output of the comparator CP is inputted to an encoding circuit EC and converted to digital code there.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to A /
The present invention relates to a D converter, and more particularly to an A / D converter constituted by a current mirror circuit.

[0002]

2. Description of the Related Art In recent years, a low voltage A which can be operated at a low power supply voltage
A / D converter (hereinafter abbreviated as ADC) is required, and an ADC using a current mirror circuit has been proposed. For example, "1994 SYMPOSIUM ON
VLSI CircuitsDIGEST OF TE
CHNICAL PAPERS, pp. 17-18, I
EEE CAT. NO. 94CH3434-8 "or" IEICE Technical Report [Integrated Circuit] Vo
l. 94, No. 124, ICD94-45 (1994
−06), pp. 1-8 ". As a conventional example, an example of a 3-bit ADC is shown in FIG. 4 for simplicity.

In this conventional example, a tree structure (tree structure) is formed by a current mirror circuit, and A / D conversion is performed by adding and subtracting current at each part of the tree structure. FIG. 4 is a circuit diagram in which a current mirror circuit having one input and two outputs is hierarchically connected in three stages, thereby forming a three-stage tree structure of a binary tree as shown in FIG. Input terminals of the current mirror circuits CM1, CM2, CM3 of each stage;
A first current source CS1, a second current source CS2, and a third current source CS3 are connected to the output terminals, respectively, and add and subtract the current at each terminal. The signal current is input to the input terminal of the first-stage current mirror circuit, and propagates through the tree structure from this to the output terminal of the last terminal current mirror circuit. Further, a comparator CP for determining whether the current is positive or negative is connected to the output of the last stage, and further connected to the encoding circuit EC.

FIG. 6 shows a configuration of a part of the current mirror circuit, that is, a node portion in FIG. An N-channel MOS type field effect transistor (hereinafter referred to as NMOS) N1 and N2 constitute a current mirror circuit CMF 'in the preceding stage, and P-channel MOS type field effect transistors (hereinafter referred to as PMOS) P1 and P2 constitute a current mirror circuit in the subsequent stage. A mirror circuit CMR 'is formed. Here, the current mirror circuit in the preceding stage is formed of an NMOS, and is therefore referred to as an N-type current mirror circuit for convenience. Further, the current mirror circuit at the subsequent stage is constituted by a PMOS, and is therefore referred to as a P-type current mirror circuit for convenience. The mirror ratio of each current mirror circuit is 1. The current source C is connected to the connection point between each of the current mirror circuits in the preceding and subsequent stages.
S0 is connected, and the current of the current source is added to or subtracted from the current propagated through the tree structure.

For this reason, the input current I1 is supplied to the current mirror circuit CMF 'in the preceding stage comprising the NMOSs N1 and N2.
Is input, the current I2 is output from the current mirror circuit.
(= I1) is output. The current source CS for this I2
When a current Is of 0 is given as shown in FIG.
The subsequent stage current mirror circuit CMR 'composed of P2
Input current I3 becomes I2-Is (= I1-Is),
The output current I4 of this current mirror circuit is I3, that is, I1-Is (= I2-Is). That is, while the current I1 propagates through the current mirror circuit, the current Is
Is subtracted and output as a current I4.

In this way, the input current is branched by the tree structure, and the addition and subtraction are performed during the propagation of the signal current to the terminal. If the current value of the current source on the way is set as shown in FIG. 5, for example, the current at the end of the tree structure becomes the current value shown on the right side of the figure. Here, a code value corresponding to the magnitude of the input current can be obtained by comparing whether the terminal current is positive or negative in the comparator. For example, assuming that the input current in FIG. 5 is 5.3, the current values to the comparator in the figure are 5.3, 4.3, 3.3, 2.3, 1.3, 0.3,.
3, -0.7, -1.7, and the codes obtained from the eight comparators are, for example, "HHHHHHLL". Here, “H” and “L” correspond to digital values of 1 and 0, respectively. If this code is converted into a desired digital code by an encoder circuit, A / D conversion can be performed.

An N-type current mirror circuit is constructed by NPN bipolar transistors instead of NMOS, and PM
There has been proposed a P-type current mirror circuit composed of PNP bipolar transistors instead of the OS, and an ADC composed of these current mirror circuits.

[0008]

As described above, the tree structure in the conventional ADC is realized by alternately connecting N-type current mirror circuits and P-type current mirror circuits. However, when the N-type current mirror circuit and the P-type current mirror circuit are alternately connected, the potential at the connection node is easily affected by the fluctuation of the power supply voltage and the fluctuation of the signal current. As a result,
There is a problem that an error easily occurs between the input current and the output current of the current mirror circuit, and it becomes difficult to perform high-precision A / D conversion.

Further, the operation speed of the P-type transistor is slower than that of the N-type transistor, and a PNP transistor having good characteristics cannot be obtained in the process of the bipolar transistor. When both elements are used, there is a problem that performance is limited in terms of operation speed and process.

Further, in the conventional example, two kinds of current sources for adding and subtracting a current in the middle of the tree structure are required, a current sink type current source and a current source type current source, and the current source circuit becomes complicated. is there.

[0011]

An object of the present invention is to operate at a low power supply voltage,
And to provide a highly accurate ADC.

[0012]

The ADC of the present invention comprises a current mirror circuit in the preceding stage having one input terminal and a plurality of output terminals, and a first current source connected to the input terminal for adding and subtracting currents. , A plurality of second current sources connected to each of the plurality of output terminals for adding and subtracting a current, and a current supplied from each of the output terminals as an input, each having a plurality of output terminals. And a plurality of output current terminals connected to each of a plurality of output terminals of the latter-stage current mirror circuit and a plurality of output terminals of the latter-stage current mirror circuit, which add and subtract currents. The third current source, a comparator for comparing the output current of the current mirror circuit of the latter stage with a predetermined level and outputting the comparison result, and the digital outputs of the plurality of comparators are digital coded. And a encoding circuit for converting the.

Further, the current mirror circuit of each stage has a pre-stage current mirror circuit which receives an input current and outputs an output current having the same value, and an addition / subtraction value of the current of the output of the pre-stage current mirror circuit and the current source. It is composed of a post-stage current mirror circuit that is input and outputs the same output current,
The front-stage current mirror circuit and the rear-stage current mirror circuit are all composed of the same conduction type transistor.

[0014]

According to the present invention, the current mirror circuit constituting the tree structure is a current mirror circuit of only one of the N-type and the P-type, so that the potential fluctuation at the connection node between the current mirror circuits is reduced. The current error between the input and output of the current mirror circuit is reduced. In addition, since the tree structure can be configured with only one of the N-type and P-type current mirror circuits, it is convenient in terms of operation speed and process.

[0015]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment in which the present invention is applied to a 3-bit ADC. In this example, a three-stage tree structure as shown in the equivalent model in FIG. 2 is constituted only by the N-type current mirror circuit. Each current mirror circuit has a one-input two-output configuration. A first current source CS1 is connected to the input terminal of the first-stage current mirror circuit CM1, and a second current source CS2 is connected to the output terminal. A current source is connected. The current supplied from the output terminal of the first-stage current mirror circuit CM1 is input to the input terminal of the second-stage current mirror circuit CM2, and the second terminal is connected to the output terminal in the same manner as the first-stage current mirror circuit CM1. The current source as the current source CS2 is connected. Further, the current supplied from the output terminal of the second-stage current mirror circuit CM2 is input to the input terminal of the third-stage current mirror circuit CM3 as the last stage,
A third current source CS3 is connected to the output terminal. A comparator CP is connected to each of the output terminals to compare the output current of the current mirror circuit CM3 with the third current source CS3, that is, determine whether the difference between the two is positive or negative. The outputs of these comparators CP are input to an encoding circuit EC, where they are converted into digital codes.

FIG. 3 shows a connection circuit of an N-type current mirror circuit having a tree structure according to the present invention. Here, NMOS N
1 and N2 constitute a current mirror circuit CMF in the preceding stage,
Current mirror circuit CM at the subsequent stage with NMOS N3 and N4
It constitutes R. Then, the current I1 is input to the previous-stage current mirror circuit CMF, the output current I2 is subtracted from the current Is of the current source CS0, and the current I3 is input to the subsequent-stage current mirror circuit CMR to obtain the output current I4. I have.

When the configuration of such a current mirror circuit is compared with the conventional circuit shown in FIG. 4, the following can be understood. First, in the conventional tree structure, both N-type and P-type current mirror circuits are used, but in the tree structure of this embodiment, only the N-type current mirror circuit is used. Therefore, the error between the input current and the output current of the current mirror circuit can be reduced. The reason why this error can be reduced will be described later. Generally, an N-type transistor is a P-type transistor.
Since it can operate faster than the type transistor, it can operate faster than the conventional example.

Next, as a current source for supplying a current to be added or subtracted in each part of the tree structure, in the conventional example, both a current sink type current source and a current source type current source are used. Only source current sources are used. Therefore, the current source circuit becomes simpler.

Since the tree structure is composed only of the N-type current mirror circuit, the setting of the current value to be added or subtracted at each part of the tree structure cannot be simply determined as in the conventional example. It can be overcome by various ideas.
Here, for the sake of simplicity, description will be made with reference to the equivalent model diagram of the circuit of FIG. 1 shown in FIG. 2 and the equivalent model diagram of the conventional circuit of FIG. 4 shown in FIG. In the conventional example, it is assumed that the addition and subtraction of the current by the current source in each part of the tree structure is performed only by subtraction, and in the example of the present invention, the addition and subtraction of the current by the current source are performed only by addition. In this case, the most basic A
This is a process for / D conversion. In special cases, addition,
The subtraction can be set arbitrarily. Also, the input current I
The range of in is from 0 to 8, and the bias current IB added to the input current is 0.

In the conventional example, while the input current passes through one path of the tree structure, the current is subtracted at each node and reaches the terminal comparator. 8 for 3-bit ADC
Since the input current value is determined by comparing the input currents with the comparison levels, the total value of each path is 0, 1, 2,.
7 may be subtracted from each other. That is, the input current Ii
Assuming that n is the subtraction value of each stage, I1, I2, and I3, the current I that reaches each comparator is given by equation (1). I = ((Iin−I1) −I2) −I3 = Iin− (I1 + I2 + I3) (1)

However, I1, I2 and I3 are given by a certain Iin
It is necessary to satisfy at least one path or more for (0 <Iin <8), that is, Iin− (I1 + I2 + I3)> 0. Therefore, in the conventional example, the subtraction current value on the path from the input to each comparator is, for example,
For the input full scale FS, I1 = FS / 2,0 I2 = FS / 4,0 I3 = FS / 8,0. That is, Table 1 is obtained.

[0022]

[Table 1]

On the other hand, in the case of the present invention, at each node of the tree structure, the current obtained by subtracting the input current to the node from the added current supplied from the current source passes through the path and reaches the comparator. Become. That is, the input current Ii
n, and assuming that the added current value of each stage is I1, I2, I3, the current value I reaching each comparator is given by the following equation (2). I = I3- (I2- (I1-Iin)) = (I1-I2 + I3) -Iin (2)

However, I1, I2 and I3 are some Iin
At least one path for (0 <Iin <8) and simultaneously satisfying (I1-Iin)> 0 (I2- (I1-Iin))> 0 I3- (I2- (I1-Iin))> 0 There is a need. This is a restriction due to the fact that the current mirror circuit cannot propagate a negative current to the next stage.

In order to make the total current value until reaching the comparator apparently reach the judgment level, similarly to the conventional example, the above equation is modified to become equation (3). I = -1 × {Iin- (I1-I2 + I3)} (3) The right side (-1) may be obtained by inverting the output of the conventional comparator. Also, in order to keep the input of the comparator positive even when the input from the preceding stage is 0, paying attention to I3> 0, the added current of each stage is, for example, as shown in Table 2. However, since I3 cannot be set to 0, the effect of I3 on the determination level is actually smaller than the current value in this table by one.

[0026]

[Table 2]

Next, when a tree structure is formed by only one of the N-type or P-type current mirror circuits,
It will be described that the source current error of the current mirror circuit is smaller than that in the case where the current mirror circuit is configured with the current mirror circuit of the present invention. Here, the case of an N-type current mirror circuit is illustrated, but the same applies to the case of a P-type current mirror circuit.

The error of the current mirror circuit is caused by the difference between the drain-source voltage Vds of the input transistor and the output transistor of the current mirror circuit. In the present invention, as shown in FIG.
1 is the N-channel threshold voltage Vtn of N1 itself, while the Vds (N2) of NMOS N2 is
Is substantially determined by the threshold voltage Vtn of N3. This is because Vgs = Vtn + (2 · Ids / K) ^1/2 ≒ Vtn (4) if the drain current Ids is sufficiently small at the gate-source voltage Vgs of the N-channel transistor Nx connecting the gate terminal and the drain terminal. ) Holds. Here, K is a constant indicating the characteristics of the element. Therefore, in the current mirror circuit of the present invention, approximately Vds (N1) = Vds (N2) holds,
The error of the current mirror circuit is small.

On the other hand, as shown in FIG. 6, a current mirror circuit composed of P-type and N-type
While Vds (N1) of N1 is almost equal to N1's own N-channel threshold voltage Vtn, Vds of NMOS N2 is
(N2) is Vds of the PMOS P3 from the power supply voltage Vdd.
(P3) is subtracted. Vds of PMOS P3
Becomes almost the P-channel threshold voltage Vtp of P3 itself, so that Vds (N2) = Vdd-Vds (P3) = Vdd-V
tp. Therefore, Vds (N2) depends on Vdd and Vtp, and Vds (N1) = Vds (N2) does not always hold. Therefore, the error of the current mirror circuit is larger than that of the present invention.

Therefore, the current error of the current mirror circuit is smaller when the tree structure is formed on one of the N-type or P-type current mirror circuits than when the current mirror circuit is formed by the N-type and P-type current mirror circuits. From this result, it can be seen that the tree structure using the current mirror circuit of the present invention has higher accuracy than the conventional example. In addition to this,
According to the present invention, since a tree structure using a current mirror circuit can be constituted only by NMOS, high-speed operation can be realized and the current source circuit can be simplified.

In the above embodiment, the N-type current mirror circuit is constituted by NMOS, but the current mirror circuit may be constituted by NPN bipolar transistors.
Similarly, a P-type current mirror circuit may be constituted by PNP bipolar transistors. In the above embodiment, the mirror ratio of the current mirror circuit is set to 1 for simplicity.
In practical applications, it is possible to take values other than 1.

[0032]

As described above, the present invention relates to the conventional A
Since the DC tree structure is realized by the current mirror circuit configured with only one of the N-type transistor and the P-type transistor, the error of the current mirror circuit is reduced, and a highly accurate ADC can be obtained. In addition, since the tree structure can be configured with only one of the N-type and P-type current mirror circuits, it is convenient in terms of operation speed and process. In particular, when the current mirror circuit is configured only with N-type transistors. Can provide a more advantageous and superior ADC in terms of operation speed.

[Brief description of the drawings]

FIG. 1 is an overall circuit diagram of an embodiment in which the present invention is applied to a 3-bit ADC.

FIG. 2 is an equivalent model diagram of the ADC of FIG. 1;

FIG. 3 is a circuit diagram of a part of a current mirror circuit in the circuit of FIG.

FIG. 4 is an overall circuit diagram of an example of a conventional 3-bit ADC.

FIG. 5 is an equivalent model diagram of the ADC in FIG. 4;

6 is a circuit diagram of a part of a current mirror circuit in the circuit of FIG.

[Explanation of symbols]

 CM1, CM2, CM3 Current mirror circuit CP comparator EC encoding circuit CS1, CS2, CS3 Current source N1, N2, N3, N4 NMOS P1, P2 PMOS Iin Input current IB Bias current

Claims (5)

[Claims] 1. A front-stage current mirror circuit having one input terminal and a plurality of output terminals, a first current source connected to the input terminal for adding and subtracting a current, and each of the plurality of output terminals. A plurality of second current sources connected to add and subtract currents, and a current supplied from each of the output terminals as an input, each having a plurality of output terminals, and a current mirror circuit of the preceding stage A second stage current mirror circuit composed of elements of the same conductivity type, and a plurality of third current sources connected to each of a plurality of output terminals of the second stage current mirror circuit for adding and subtracting currents,
It is characterized by comprising a comparator for comparing the output current of the current mirror circuit of the latter stage with a predetermined level and outputting the comparison result, and an encoding circuit for converting the digital outputs of the plurality of comparators into digital codes. A / D converter. 2. A connection structure composed of a current mirror circuit at a front stage and a current mirror circuit at a rear stage is connected in a plurality of stages as a tree structure, and a first current source is connected to an input terminal of the current mirror circuit at the first stage, and a final stage. 3. The A / D converter according to claim 1, wherein a third current source is connected to the output terminal of the current mirror circuit of, and a second current source is connected to the output terminals of one or more middle stage current mirror circuits. 3. The current mirror circuit comprises: a pre-stage current mirror circuit that receives an input current and outputs an output current of the same value; and an addition / subtraction value of the current between the output of the pre-stage current mirror circuit and the current source. 3. The A / D converter according to claim 1, wherein the A / D converter is composed of a rear-stage current mirror circuit that outputs the same output current, and the front-stage current mirror circuit and the rear-stage current mirror circuit are all composed of the same conduction type transistor. . 4. A transistor forming a current mirror circuit is an N-channel field effect transistor or NPN.
The A / D converter according to claim 3, which is a bipolar transistor. 5. The A / D according to claim 1, wherein the comparator is configured to compare the magnitude of the output current of the final stage current mirror circuit with the comparison current supplied by the third current source. converter.