JPH0918332A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of required transistors, to reduce power consumption and delay and to provide a complicated logic function. SOLUTION: Prestage output signals are impressed to a poststage gate between a first path transistor circuit PT1 and a second path transistor circuit PT2, the prestage output signals are impressed to the source.drain route of a poststage between the second path transistor circuit PT2 and a third path transistor circuit PT3 and first input signals and second input signals in logically independent relation are impressed to the first input node In1 and second input node In2 of the first path transistor circuit PT1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and in particular, can be applied to an LSI such as a general-purpose processor, a signal processor, an image processor, etc. which partially includes a logic circuit.

[0002]

2. Description of the Related Art Circuits using pass transistors have been used so far in the IEEE Journal of Solid.
-State Circuits, Vol. sc-2
2, No. 2, April 1987 pp216
-Pp222 (hereinafter, referred to as "first related art"), Differential Pass-trans
What is introduced as isor Logic, I
EEE Journal of Solid-Stat
e Circuits, Vol. sc-25, N
o. 2, April 1990 pp388-pp
C in 395 (hereinafter, referred to as the second related art).
complementary Pass-transis
There is something introduced as tor Logic.
All of these circuits are complementary logic circuits that use both positive and negative logic. See also Custom Integra
Ted Circuits Conference 1
994 Digest pp603-pp606 (hereinafter, referred to as a third conventional technique) includes a pass transistor circuit using a single channel type MOSFET instead of a complementary type and a standard cell type pass transistor circuit designing method using the same. It is shown. In addition, 1
Proceedings of the 1994 Autumn Meeting of the Institute of Electronics, Information and Communication Engineers, Basics
Boundary volume pp64 (hereinafter, referred to as the fourth conventional technology)
2 shows a method of forming a pass transistor circuit using a logic expression method called a binary decision graph. In addition, IEEE TRANSACTIONS ON CO
MPUTERS, Vol. c-35, No. 8, AUG
UST 1986, pp677-pp691 contains Bi
An effective method of logical operation using a nary-Decision-Diagram (a binary decision graph) (hereinafter referred to as a fifth conventional technique) is shown. Further, in Japanese Patent Laid-Open No. 1-216622 (hereinafter referred to as a sixth prior art), the output signal of the complementary pass transistor circuit in the preceding stage is compared with the complementary MO transistor of the complementary pass transistor circuit in the succeeding stage.
A logic circuit for realizing logic such as an exclusive OR circuit and a full adder circuit by applying it to the gate of the SFET is shown. Further, in Japanese Unexamined Patent Publication No. 1-256219 (hereinafter, referred to as a seventh prior art), an output signal of a complementary pass transistor circuit at a front stage is applied to a source of a complementary MOSFET of a complementary pass transistor circuit at a rear stage. Thus, a logic circuit that implements logic such as an exclusive OR circuit and a full adder circuit is shown. Further, in U.S. Pat. No. 4,477,904 (hereinafter referred to as "eighth prior art"), an output signal of a complementary pass transistor circuit in a preceding stage is compared with a complementary type M of a complementary pass transistor circuit in a succeeding stage.
The exclusive OR circuit is used by combining the method of applying to the gate of the OSFET and the method of applying the output signal of the complementary pass transistor circuit of the preceding stage to the source of the complementary MOSFET of the complementary pass transistor circuit of the following stage. A parity detection / generation circuit is shown.

[0003]

In order to realize the same logic function, the pass transistor circuit requires a smaller number of transistors as compared with a general CMOS logic circuit, and power consumption and delay can be reduced. . However,
Since the pass transistor circuit is difficult to perform logic synthesis, it has not been used for a random logic circuit that requires all logic functions. That is, the sixth prior art showing a method of applying the output signal of the complementary pass transistor circuit in the preceding stage to the gate of the complementary MOSFET of the complementary pass transistor circuit in the succeeding stage, and the output signal of the complementary pass transistor circuit in the preceding stage Is applied to the source of the complementary MOSFET of the complementary pass transistor circuit in the subsequent stage, the seventh prior art is applied to a logic circuit that realizes logic such as an exclusive OR circuit and a full adder circuit. Is. However, the sixth conventional technique and the seventh conventional technique do not show a method of using a pass transistor circuit to realize all logical functions. In addition, a method of applying the output signal of the complementary pass transistor circuit of the preceding stage to the gate of the complementary MOSFET of the complementary pass transistor circuit of the succeeding stage and the output signal of the complementary pass transistor circuit of the preceding stage of the complementary pass transistor circuit of the succeeding stage Complementary MOSFE
The eighth prior art showing that the method of applying to the source of T is also used is applied to a parity detection / generation circuit using an exclusive OR circuit. However, even in the eighth conventional technique, a method of using a pass transistor circuit to realize all logic functions is not shown. On the other hand, in order to provide a pass transistor circuit that can be used for a random logic circuit that requires all logic functions, it is necessary to realize a complicated logic function with a small number of required transistors. On the other hand, according to the study by the present inventor, in the eighth conventional technique, two MOSFETs of the same conductivity type in the complementary pass transistor circuit of the preceding stage for driving the gate or the source of the complementary MOSFET of the complementary pass transistor circuit of the subsequent stage are provided. Since a complementary logic signal having a logically complementary relationship of low and high is applied to the source of, the problem that it is difficult to realize a complicated logic function with a small number of required transistors becomes clear. Was done. Therefore, the object of the present invention is:
It is an object of the present invention to provide a semiconductor integrated circuit having a pass transistor circuit that requires a small number of transistors, can reduce power consumption and delay, and can realize a complicated logic function.

[0004]

In order to achieve the above object, the semiconductor integrated circuit according to the embodiment of the present invention is
A logic circuit having second and third pass transistor circuits (PT1, PT2, PT3) is provided, and the first, second and third pass transistor circuits (PT1, P3) of the logic circuit are provided.
Each pass transistor circuit (T2, PT3) is the first input node
(In1), second input node (In2), output node (0ut)
A first field effect transistor (Q1) having a source / drain path connected between the first input node (In1) and the output node (0ut), and the second input node (In2). A second field effect transistor (Q2) having a source / drain path connected to the output node (0ut),
The signal of the output node (Out) of the first pass transistor circuit (PT1) is applied to the second pass transistor circuit (PT2).
Of the first field effect transistor (Q1) of the third field effect transistor (Q1) and the second field effect transistor (Q1) of the third pass transistor circuit (PT3) The source / drain path of at least one of (Q1) of (Q2) is connected to one of the first input node (In1) and the output node (OUT) of the second pass transistor circuit (PT2), The first input node (In1) of the first pass transistor circuit (PT1) and the second input node (In1)
The first input signal and the second input signal are applied to the input node (In2), and the first input signal and the second input signal have a logically independent relationship (B, GND). Characterizing
(See FIGS. 1 and 2). In the semiconductor integrated circuit according to the embodiment of the present invention as described above, it is related to the logic decision of the output signal of the logic circuit obtained from either the output node of the second pass transistor circuit or the output node of the third pass transistor circuit. The first pass transistor circuit and the second
Between the second pass transistor circuit and the third pass transistor circuit, a method of applying the output signal of the former stage pass transistor to the gate of the latter stage pass transistor circuit is adopted, and between the second pass transistor circuit and the third pass transistor circuit. Is applied to the source / drain path of the subsequent pass transistor, and the first input node and the second input node of the first pass transistor circuit are logically independent of each other. A method of applying an input signal and a second input signal is adopted. As a result, the output signal of the logic circuit having the first, second, and third pass transistor circuits depends on the above three signal application methods, the number of required transistors is small, and power consumption and delay can be reduced. Thus, it becomes possible to provide a semiconductor integrated circuit having a logic circuit capable of realizing a complicated logic function. Furthermore, the first, second and third
Change the mutual connection form of the pass transistor circuits, and apply a logic input signal to the first input node and the second input node of each pass transistor circuit of the first, second and third pass transistor circuits. By making it complicated, it becomes possible to realize more complicated logical functions. A semiconductor integrated circuit according to a specific embodiment of the present invention includes at least the first field effect transistor (Q1) and the second field effect transistor (Q2) of the third pass transistor circuit (PT3). One of the source / drain paths (Q1) is connected to the first input node (In1) of the second pass transistor circuit (PT2), and is connected to the first input node (In1) of the first pass transistor circuit (PT1). The gate of the field effect transistor (Q1) and the gate (Q2) of the second field effect transistor are responsive to the first complementary input signal (A, / A), and Type transistor (Q
1) and the second field effect transistor (Q2) are complementarily conducted, and the gate of the first field effect transistor (Q1) of the second pass transistor circuit (PT2) and the second field effect transistor (Q2) are connected to each other. The gate of the field-effect transistor (Q2) of FIG. 2 is responsive to the second complementary input signal, so that the first field-effect transistor (Q1) and the second field-effect transistor (Q2) are complementary to each other. Electrically conductive, the first field effect transistor (Q1) of the third pass transistor circuit (PT3)
Gate and the gate of the second field effect transistor
(Q2) is complementary to the first field effect transistor (Q1) and the second field effect transistor (Q2) by responding to the third complementary input signal (C, / C). To the first pass transistor circuit (PT1).
Complementary input signals (A, / A) and the first input node (In1)
A signal (A · B) of the logical product of the first input signal (B) and the third complementary input signal (PT3) is generated at the output node (Out). C, / C) and the input signal (D) of the first input node (In1) and a logical product signal (C · D) is generated at the output node (Out),
The second complementary input signal supplied to the pass transistor circuit (PT2) of the above is the first pass transistor circuit (PT1).
Of the first pass transistor circuit in response to the logical product signal (AB) generated from the output node (Out) of
The signal (AB) of the logical product generated at the output node (Out) of (PT1) and the third pass transistor circuit (PT3)
Signal of the logical product generated at the output node (Out) of
The total signal (A, B, C, D) of the logical product with (C, D) is the output node (Ou) of the second pass transistor circuit (PT2).
t) is obtained (see FIG. 1). A semiconductor integrated circuit according to another specific embodiment of the present invention includes the first field effect transistor (Q1) and the second field effect transistor (Q2) of the third pass transistor circuit (PT3). The source / drain path of at least one (Q1) of the first pass transistor circuit (PT1) is connected to the output node (Out) of the second pass transistor circuit (PT2). Field effect transistor
The gate of (Q1) and the gate (Q2) of the second field effect transistor are responsive to the first complementary input signal (A, / A), so that the first field effect transistor (Q1) And the second field-effect transistor (Q2) are complementarily conducted, and the gate of the first field-effect transistor (Q1) of the second pass transistor circuit (PT2) and the second electric field The gate of the effect transistor (Q2) is responsive to the second complementary input signal to allow the first field effect transistor (Q1) and the second field effect transistor (Q2) to respond.
2) is complementarily conductive, and the gate of the first field effect transistor (Q1) of the third pass transistor circuit (TP3) and the gate of the second field effect transistor (Q2).
Means that in response to the third complementary input signal (D, / D), the first field effect transistor (Q1) and the second field effect transistor (Q1)
Of the field effect transistor (Q2) is complementarily conducted, and the first pass transistor circuit (PT1) is connected to the first complementary input signal (A, / A) and the first input node (In1). The second complementary input for generating a logical product signal (AB) with the first input signal (B) at the output node (Out) and supplying the signal to the second pass transistor circuit (PT2). The signal is the output node (Out) of the first pass transistor circuit (PT1).
In response to the logical product signal (AB) generated from the logical product signal (AB) and the logical product signal (C) of the logical product signal (AB) and the input signal (C) of the first input node (In1). A, B, C) are generated at the output node (Out) of the second pass transistor circuit (PT2) and are supplied to the first input node (In1) of the third pass transistor circuit (PT3). Input signal in response to the logical product signal (A, B, C) generated from the output node (Out) of the second pass transistor circuit (PT2), ) Above output node
Total signal of logical product of the logical product signals (A, B, C) generated at (Out) and the third complementary input signal (D, / D)
(A / B / C // D) is the third pass transistor circuit
It is obtained from the output node (Out) of (PT3) (see FIG. 2). A semiconductor integrated circuit according to a more specific embodiment of the present invention is the first pass transistor circuit of each of the first, second and third pass transistor circuits (PT1, PT2, PT3) of the logic circuit. The field effect transistor (Q1) and the second field effect transistor (Q2) are N-channel MOSFETs, and are generated from the output node (Out) of the first pass transistor circuit (PT1). The logical product signal (A / B) is a CMOS inverter.
(4000, 4002, 4003, 4004) applied to the input of the CMOS inverter (4000, 4002,
It is characterized in that the second complementary input signal supplied to the second pass transistor circuit (PT2) is generated from the output of 4003, 4004) (see FIG. 4). A semiconductor integrated circuit according to the most specific embodiment of the present invention includes at least two logic circuits (LC1 and LC2) having a circuit configuration similar to the logic circuit described above and a logic signal supply system similar to the logic circuit described above, and the two logic circuits. And a synthesis logic circuit (LC12) for logically processing each output signal of (LC1, LC2) (see FIGS. 3 and 4). Other objects and novel features of the present invention will be apparent from the following examples.

[0005]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.
This will be described with reference to the drawings.

FIGS. 1 and 2 are circuit diagrams of a semiconductor integrated circuit having a logic circuit according to an embodiment of the present invention, and although not particularly limited, each circuit element is formed by a known semiconductor integrated circuit process technique. It is formed in one single crystal silicon semiconductor substrate. The logic circuit of the semiconductor integrated circuit according to this embodiment has a first pass transistor circuit (PT1), a second pass transistor circuit (PT2,) and a third pass transistor circuit (PT1, PT2, PT3).
First, second and third pass transistor circuits (PT1, PT2, PT
Each pass transistor circuit of 3) is the first input node (In1)
A second input node (In2), an output node (0ut), a first
First field effect transistor having a source / drain path connected between an input node (In1) and an output node (0ut)
(Q1), and a second field effect transistor (Q2) having a source / drain path connected between the second input node (In2) and the output node (0ut). The gate of the first field effect transistor (Q1) of the second pass transistor circuit (PT2) responds to the signal of the output node (Out) of the first pass transistor circuit (PT1). At least one of the first field effect transistor (Q1) and the second field effect transistor (Q2) of the third pass transistor circuit (PT3)
The source / drain path of (Q1) is the first input node (In1) and output node (O1) of the second pass transistor circuit (PT2).
UT). First input node (In1) and second input node of the first pass transistor circuit (PT1)
A first input signal and a second input signal are applied to (In2), and the first input signal and the second input signal have a logically independent relationship (B, GND). To do. still,
In FIG. 1 and FIG. 2, the first field effect transistor (Q1) and the second field effect transistor of each pass transistor circuit of the first, second and third pass transistor circuits (PT1, PT2, PT3) are shown. The transistor (Q2) is an N-channel MOSFET. First, second and third pass transistor circuits (PT1, P
C2 as a polarity inverter between the gate of the first field effect transistor (Q1) and the gate of the second field effect transistor (Q2) of each pass transistor circuit (T2, PT3).
The S inverter circuits (INV1, INV2, INV3) are connected to each other. In each of the pass transistor circuits of the first, second, and third pass transistor circuits (PT1, PT2, PT3), as a modified embodiment, the second field effect transistor (Q2) is an N-channel MOSFET. It can be replaced with a P-channel MOSFET.
In this case, a CMOS inverter circuit as a polarity inverter
(INV1, INV2, INV3) can be omitted and the gate of the first field effect transistor (Q1) and the gate of the second field effect transistor (Q2) can be directly connected.

Next, the structure and operation of the logic circuit of FIG. 1 will be described in more detail. The first N-channel type of the first pass transistor circuit (PT1) of the logic circuit of FIG.
A logic input signal A that changes to a low level and a high level is applied to the gate of the field effect transistor (Q1) of
The gate of the second field effect transistor (Q2) has a CMO
Logic input signal A from the output of the S inverter circuit (INV1)
The inversion signal / A is applied. Also, the first input node (In
The logic input signal B that changes between low level and high level is applied to 1), and the ground potential (GND) is constantly applied to the second input node (In2). As a result, the output signal A · B of the logical product of the logical input signal A and the logical input signal B is output from the output node (0ut) of the first pass transistor circuit (PT1).
Is obtained. The output signal A / B of the logical product of the first pass transistor circuit (PT1) is the second pass transistor circuit.
CMO is applied to the gate of the second field effect transistor (Q2) of the second pass transistor circuit (PT2) while being applied to the gate of the first field effect transistor (Q1) of (PT2).
An inverted signal of the logical product A and B is applied from the output of the S inverter circuit (INV2). Further, a logic input signal C that changes between a low level and a high level is applied to the gate of the N-channel first field effect transistor (Q1) of the third pass transistor circuit (PT3), The gate of the field effect transistor (Q2) has a CMOS inverter circuit (I
The inverted signal / C of the logic input signal C is applied from the output of NV3). Further, the logic input signal D that changes between low level and high level is applied to the first input node (In1), and the ground potential (GND) is constantly applied to the second input node (In2). As a result, the third pass transistor circuit (PT
From the output node (0ut) of 3), the output signal C · D of the logical product of the logical input signal C and the logical input signal D is obtained. The output signal C / D of the logical product of the third pass transistor circuit (PT3) is applied to the first input node (In1) of the second pass transistor circuit (PT2). On the other hand, the first field effect transistor (Q1) of the second pass transistor circuit (PT2)
Since the output signals A and B of the logical product of the first pass transistor circuit (PT1) are applied to the gate of, the logical input signal A from the output node (0ut) of the second pass transistor circuit (PT2). Output signals A, B, C, D of the logical product of the logical input signal B, the logical input signal C, and the logical input signal D are obtained. Thus, the logic circuit having the first pass transistor circuit (PT1), the second pass transistor circuit (PT2,) and the third pass transistor circuit (PT1, PT2, PT3) of the embodiment of FIG. It can be understood that it operates as a 4-input AND circuit. Needless to say, the multi-input AND circuit is the basis of a random logic circuit that requires all logic functions. In this respect, the practical value of the logic circuit of the embodiment of FIG. 1 is extremely large. Further, the logic circuit of the embodiment of FIG. 1 can not only operate as a simple multi-input AND circuit, but can realize a more complicated logic function. For example, instead of constantly applying the ground potential (GND) to the second input node (In2) of the first pass transistor circuit (PT1), the logic input signal X changing to low level and high level is input. Consider the case where it is applied. In this case, the logical product signal / AX (logical product of the inverted signal / A of the logical input signal A and the logical input signal X) and the logical product signal AB (logical input signal A and logical input signal B) The logical sum of the signal and the signal A ・ B + / A ・ X is the first
It is easy to understand that a very complicated logic output signal can be obtained from the output node (0ut) of the second pass transistor circuit (PT1) and finally from the output node (0ut) of the second pass transistor circuit (PT2). It will be done.

The logic circuit of the embodiment shown in FIG. 2 shows another embodiment of the present invention. That is, the gate of the N-channel first field effect transistor (Q1) of the first pass transistor circuit (PT1) of the logic circuit of the embodiment of FIG. 2 has a logic input that changes to a low level and a high level. Signal A
Is applied, and the inverted signal / A of the logic input signal A is applied to the gate of the second field effect transistor (Q2) from the output of the CMOS inverter circuit (INV1). Also, the first
The input node (In1) is applied with the logic input signal B that changes between low level and high level, and the second input node (In2)
A ground potential (GND) is constantly applied to the. As a result, the output node (0u) of the first pass transistor circuit (PT1)
From t), the output signals A and B of the logical product of the logical input signal A and the logical input signal B are obtained. The output signals A and B of the logical product of the first pass transistor circuit (PT1) are applied to the gate of the first field effect transistor (Q1) of the second pass transistor circuit (PT2) while the second The inversion signal of the logical product A and B is applied from the output of the CMOS inverter circuit (INV2) to the gate of the second field effect transistor (Q2) of the pass transistor circuit (PT2). The ground potential (GND) is constantly applied to the second input node (In2).
As a result, from the output node (0ut) of the second pass transistor circuit (PT2), output signals A, B, and C of the logical product of the logical input signal A, the logical input signal B, and the logical input signal C are obtained. . In addition, the first of the third pass transistor circuit (PT3)
The input node (In1) has a second pass transistor circuit (PT2)
AND signal A, B, C obtained from the output node (0ut) of
Is applied, and the inverted signal / D of the logic input signal D is applied from the output of the CMOS inverter circuit (INV3) to the gate of the second field effect transistor (Q2), and the first field effect transistor (Q1) is applied. A logic input signal D is applied to the gate of, and the second input node (In2) constantly receives the ground potential (G
ND) is applied. As a result, from the output node (0ut) of the third pass transistor circuit (PT3), from the output node (0ut) of the third pass transistor circuit (PT3), the logic input signal A, the logic input signal B, and the logic The output signals A, B, C, and / D of the logical product of the input signal C and the logical input signal D are obtained. Further, the logic circuit of the embodiment of FIG. 2 can not only operate as a simple multi-input AND circuit, but also realize a more complicated logic function. For example, the second input node (In2) of the first pass transistor circuit (PT1), the second input node (In2) of the second pass transistor circuit (PT2), and the second input node (In2) of the third pass transistor circuit (PT3). Input node (In2)
Consider the case where the logic input signals X, Y, and Z that change to the low level and the high level are applied to each of them, instead of constantly applying the ground potential (GND). In this case, finally, the third pass transistor circuit (P
It will be easily understood that a very complicated logic output signal can be obtained from the output node (0ut) of T3). As described above, according to the embodiment of the present invention, the mutual connection form of the first, second and third pass transistor circuits (PT1, PT2, PT3) can be changed, and the first, second and third pass transistor circuits can be changed. First pass transistor circuit of each pass transistor circuit (PT1, PT2, PT3)
By complicating the method of applying the logic input signal to the input node (In1) and the second input node (In2), it becomes possible to realize a more complicated logic function. In addition to realizing such complex logic functions, the number of required transistors is small, and the power supply and delay can be reduced. Mutual connection of multiple pass transistor circuits and logic input signals to each pass transistor circuit. In order to determine the application method of the
The minute decision graph can be applied.

FIG. 5 shows a 16-input AND circuit formed by serially connecting 15 general pass transistor circuits. From the output OUT of this circuit, a logical product output signal of 16 logical input signals from the logical input signal Q to the logical input signal A can be obtained, but the critical path from the logical input signal Q to the output OUT is 15 This is a series connection of individual pass transistor circuits. As a result, the signal delay of this AND circuit becomes extremely large.

On the other hand, FIG. 3 shows a 16-input A according to an embodiment of the present invention in which the signal delay is reduced by applying the binary decision graph.
The ND circuit is shown. Logic circuit block LC1, LC
2, LC3 and LC4 are exactly the same as the circuit configuration of FIG. Therefore, from the output of the logic circuit block LC1,
A logical product signal of B, C, D is obtained, and the logical circuit block L
A logical product signal of A, B, C, D is obtained from the output of C1, and E, F, G,
A logical product signal of H is obtained, a logical product signal of I, J, K, and L is obtained from the output of the logical circuit block LC3, and a logical product of M, N, P, and Q is obtained from the output of the logical circuit block LC4. The signal is obtained. Therefore, the logic circuit blocks LC1 and L
A logical product signal of A, B, C, D, E, F, G, and H is obtained from the output of the logic circuit block LC12 provided above C2, and the logic provided above the logic circuit blocks LC3 and LC4. From the output of the circuit block LC34, IJK
A logical product signal of L, M, N, P and Q is obtained. Thus, from the output of the logic circuit block LC1234 provided above the logic circuit blocks LC12, 34, A, B, C
・ D ・ E ・ F ・ G ・ H ・ I ・ J ・ K ・ L ・ M ・ N ・ P ・
A logical product signal of Q is obtained. The critical path to the output at this time is a series connection of four pass transistor circuits, and the signal delay of the AND circuit is significantly reduced.

FIG. 4 shows a 15-input A according to the embodiment of FIG.
7 shows another embodiment in which the loss of the signal level passing through the pass transistor circuit is recovered by partially changing the configuration and connection of the ND circuit. That is, it is well known that the signal level is subject to the loss of the gate-source threshold voltage of the N-channel MOSFET when passing through the pass transistor circuit composed of only the N-channel MOSFET. The logic circuit blocks LC1, LC2, LC3, LC4, LC12, of FIG.
34, CMOS inverters 4000, 4001, 400 as signal amplifiers provided inside LC1234
2, 4003, 4004, 4005, 4006 are for recovering the loss of the threshold voltage. That is,
Even if the high level of the logic input signal of the CMOS inverters 4000 to 4006 is slightly lowered, the output signal thereof changes between the high level of the power supply voltage and the low level of the ground potential. Since the CMOS inverters 4000 to 4006 as signal amplifiers invert the logic input signal and transmit it to the output, the logic circuit blocks LC1, LC2,
The signal application form to the gates of the pass transistor circuits at the output stages of LC3 and LC4 has been changed, and the signal application form to the gates of the logic circuit blocks LC12, 34, LC1234 pass transistor circuits has been changed. But,
Finally, from the output of the logic circuit block LC1234, A / B / C / D / E / F / G / H / I / J / K / L / M.
It will be easily understood that an AND signal of N, P and Q is obtained.

The embodiments of the present invention made by the present inventor have been described in detail above, but the present invention is not limited to the above specific embodiments, and various modifications can be made within the scope of the technical idea thereof. Not to mention possible. For example, the field effect transistor of the pass transistor circuit is a silicon MO
The SESFET is not limited to the SFET, and a MESFET made of a compound semiconductor of GaAs can be used. Further, the logic circuit having the pass transistor circuit of the present invention is a random logic for decoding a RISC type instruction and controlling an instruction execution unit in an LSI such as a general-purpose processor, a signal processor, an image processor, etc. Needless to say, when applied to a circuit, the power consumption and delay of the entire LSI can be reduced.

[0013]

According to the present invention, it is possible to provide a semiconductor integrated circuit having a pass transistor circuit which requires a small number of transistors, can reduce power consumption and delay, and can realize a complicated logical function. You can

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a logic circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a logic circuit according to another embodiment of the present invention.

FIG. 3 is a circuit diagram of a 16-input AND circuit according to another embodiment of the present invention.

FIG. 4 is a circuit diagram of a 16-input AND circuit according to a modified embodiment of the present invention.

FIG. 5 is a circuit diagram of a general 16-input AND circuit.

[Explanation of symbols]

PT1 ... First pass transistor circuit, PT2 ... Second pass transistor circuit, PT3 ... Third pass transistor circuit, I
n1 ... first input node, In2 ... second input node, 0ut ... output node, Q1 ... first field effect transistor, Q2 ... second
Field effect transistor.

Front page continuation (72) Inventor Koichi Seki 1-280, Higashi Koigokubo, Kokubunji, Tokyo Inside Hitachi Central Research Laboratory

Claims (6)

[Claims] 1. A pass transistor comprising a logic circuit having first, second, and third pass transistor circuits, wherein each pass transistor of the first, second, and third pass transistor circuits of the logic circuit is provided. The circuit includes a first input node, a second input node, an output node, a first field effect transistor having a source / drain path connected between the first input node and the output node, and Second
A second field effect transistor having a source / drain path connected between the input node and the output node, wherein the second field is applied to the signal at the output node of the first pass transistor circuit. The gate of the first field effect transistor of the pass transistor circuit responds, and the source of at least one of the first field effect transistor and the second field effect transistor of the third pass transistor circuit. The drain path is connected to either the first input node or the output node of the second pass transistor circuit, and is connected to the first input node and the second input node of the first pass transistor circuit. Is applied with the first input signal and the second input signal, and the first input signal and the second input signal have a logically independent relationship. Semiconductor integrated circuit to be butterflies. 2. A source / drain path of at least one of the first field-effect transistor and the second field-effect transistor of the third pass-transistor circuit has a source-drain path of the second pass-transistor circuit. First above
Connected to an input node, wherein the gate of the first field effect transistor and the gate of the second field effect transistor of the first pass transistor circuit are responsive to a first complementary input signal, The first field effect transistor and the second
Of the second field effect transistor and the gate of the first field effect transistor and the gate of the second field effect transistor of the second pass transistor circuit have a second complementary input signal. In response to the first field effect transistor and the second field effect transistor.
Of the third field effect transistor, and the gate of the first field effect transistor and the gate of the second field effect transistor of the third pass transistor circuit have a third complementary input signal. In response to the first field effect transistor and the second field effect transistor.
Of the field effect transistor, and the first pass transistor circuit outputs a logical product signal of the first complementary input signal and the first input signal of the first input node to the output node. The third pass transistor circuit generates a signal of a logical product of the third complementary input signal and the input signal of the first input node at the output node, and outputs the signal to the second pass transistor circuit. The second supplied
The complementary input signal of the first pass transistor circuit is responsive to the AND signal generated from the output node of the first pass transistor circuit, and the complementary input signal of the AND signal generated at the output node of the first pass transistor circuit is 2. The integrated signal of the logical product with the signal of the logical product generated at the output node of the third pass transistor circuit is obtained from the output node of the second pass transistor circuit. The semiconductor integrated circuit according to 1. 3. The source / drain path of at least one of the first field-effect transistor and the second field-effect transistor of the third pass-transistor circuit is provided in the second pass-transistor circuit. Connected to the output node, wherein the gate of the first field effect transistor and the gate of the second field effect transistor of the first pass transistor circuit are responsive to a first complementary input signal, The first field effect transistor and the second field effect transistor.
Of the second field effect transistor and the gate of the first field effect transistor and the gate of the second field effect transistor of the second pass transistor circuit have a second complementary input signal. In response to the first field effect transistor and the second field effect transistor.
Of the third field effect transistor, and the gate of the first field effect transistor and the gate of the second field effect transistor of the third pass transistor circuit have a third complementary input signal. In response to the first field effect transistor and the second field effect transistor.
Of the field effect transistor, and the first pass transistor circuit outputs a logical product signal of the first complementary input signal and the first input signal of the first input node to the output node. And is supplied to the second pass transistor circuit.
In response to the signal of the logical product generated from the output node of the first pass transistor circuit, and outputs a signal of the logical product of the signal of the logical product and the input signal of the first input node. An input signal generated at the output node of the second pass transistor circuit and supplied to the first input node of the third pass transistor circuit is generated from the output node of the second pass transistor circuit. In response to the signal of the logical product, the integrated signal of the logical product of the signal of the logical product generated at the output node of the first pass transistor circuit and the third complementary input signal is the third path. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is obtained from the output node of a transistor circuit. 4. The first field effect transistor and the second field effect transistor of each of the pass transistor circuits of the first, second and third pass transistor circuits of the logic circuit are N. It is a channel type MOSFET, and the signal of the logical product generated from the output node of the first pass transistor circuit is applied to the input of the CMOS inverter and supplied from the output of the CMOS inverter to the second pass transistor circuit. The semiconductor integrated circuit according to claim 2, wherein the second complementary input signal is generated. 5. At least two logic circuits of a logic signal supply system similar to that of the logic circuit according to claim 1, and a composite logic circuit for logically processing each output signal of the two logic circuits. And a semiconductor integrated circuit. 6. At least two logic circuits of a logic signal supply system similar to that of the logic circuit according to claim 4, and a synthetic logic circuit for logically processing each output signal of the two logic circuits. And a semiconductor integrated circuit.