JPH09181629A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To recover a carrier with an accurate frequency. SOLUTION: This circuit is provided with a frequency conversion circuit 1 converting a frequency of a received RF signal into a frequency of an IF signal, a demodulation circuit 3 demodulating an output of the circuit 1 into a base band signal, a carrier recovery circuit 2 recovering a carrier, a voltage controlled oscillator(VCO) 4 oscillating a local oscillation signal, a variable frequency divider means 6 dividing a received signal variably, a reference signal generating means 7 generating a reference signal, a phase comparator means 9 comparing phases, and an output of the means 9 is used to control the oscillated frequency of the voltage controlled oscillator VCO 4 as a control voltage. In this case, the reference signal generating means 7 is made up of a variable reference oscillator 13 and frequency discrimination means 11, 12 discriminating the frequency of the carrier are provided and an output of the frequency discrimination means 11, 12 is used to control the carrier frequency to be constant.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit suitable for use as a channel selection device in a digital satellite broadcast receiver or the like.

[0002]

2. Description of the Related Art Generally, a frequency synthesizer type channel selecting device is often used in a digital satellite broadcasting receiver. FIG. 2 shows a block diagram of a conventional PLL circuit used in this channel selection device. Reference numeral 1 is a frequency conversion circuit that frequency-converts an RF signal that has been digitally modulated by QPSK modulation and transmitted to an IF signal, 2 is a carrier wave reproduction circuit that reproduces a carrier wave from this IF signal, and 3 is the above based on the reproduced carrier wave. A demodulation circuit for demodulating an IF signal into a baseband signal, 4 is a VCO (voltage controlled oscillator) for outputting a local oscillation signal necessary for frequency conversion in the mixer circuit 1, and 5 is this VCO.
4 is a fixed frequency divider that divides the output of 1 / p, 6 is a variable frequency divider that variably divides the output of the fixed frequency divider 5 into 1 / n, 7 is a fixed reference oscillator that outputs a reference oscillation output, Reference numeral 8 is a fixed frequency divider that divides the output of the fixed reference oscillator 7 by 1 / m, 9 is a phase comparator that compares the output of the fixed frequency divider 8 with the output of the variable frequency divider 6, and 10 is the phase comparison. It is a low-pass filter that removes high-frequency components of the output of the device 9 and determines the response characteristics and synchronization characteristics of the PLL.

In the PLL circuit described above, the VCO 4 output whose phase is locked to the reference signal of the fixed reference oscillator 7 can be obtained by changing the frequency division ratio n of the variable frequency divider 6 according to the desired channel. By supplying this to the frequency conversion circuit 1 as a local oscillation signal, the received RF signal can be converted into a desired IF signal.

The characteristic of the PLL circuit is that the frequency is stable and the phase noise is small, but in order to suppress the phase noise of the VCO, it is necessary to increase the gain and the band of the feedback circuit. Further, the output of the phase comparator includes the component of the comparison frequency fr, and this fr is included in the control voltage of the VCO.
In order to suppress the component, it is necessary to set the cutoff frequency of the LPF lower than fr. In order to meet these requirements, it is desirable that the comparison frequency fr be as high as possible.

On the other hand, by inserting a 1 / n variable frequency divider 6 and a 1 / p fixed frequency divider 5 in the PLL circuit, VC
A comparison frequency fr obtained by dividing the output frequency fvco of O4 and the output fref of the fixed reference oscillator 7 by 1 / m by the fixed frequency divider 8 is expressed by the following equations.

[0006]

[Equation 1]

[0007]

[Equation 2]

Therefore, in the variable frequency divider 6, the frequency step fs of the VCO which can be set by changing n
Is

[0009]

(Equation 3)

[0010]

[0011]

Here, the comparison frequency f
The higher r is, the larger the frequency step fs of the VCO becomes, so that the oscillation frequency of the VCO cannot be set finely, and V which is necessary for obtaining a desired IF signal is not obtained.
If the oscillation frequency of CO is fl, then fl and the actual VCO
A frequency deviation Δf represented by the following equation is generated between the oscillation frequency fvco and the oscillation frequency fvco.

[0012]

(Equation 4)

The closer Δf is to 0, the better it is. However, if Δf becomes large, the carrier frequency reproduced from the IF signal is deviated, and the demodulation circuit 3 cannot perform accurate demodulation. There is.

The present invention solves the above-mentioned drawbacks and provides a PLL circuit capable of reproducing a carrier wave of an accurate frequency by minimizing the frequency deviation Δf even if the frequency step fs of the VCO becomes large. To do.

[0015]

The present invention is directed to a received RF.
A frequency conversion circuit that frequency-converts the signal into an IF signal, and a demodulation circuit that demodulates the IF signal into a baseband signal,
A carrier regenerating circuit for regenerating a carrier based on the IF signal and / or the baseband signal, a VCO for oscillating a local oscillation signal, and a variable frequency dividing means for variably dividing the oscillation output of the VCO based on a channel selection command. A reference signal generating means for generating a reference signal; and a phase comparing means for comparing the output of the reference signal generating means with the phase of the output of the variable frequency dividing means. The output of the phase comparing means is used as a control voltage. PL that controls the oscillation frequency of VCO
In the L circuit, the reference signal generating means is composed of a variable reference oscillator, frequency determining means for determining the frequency of the carrier wave is provided, and the output frequency of the reference signal generating means is controlled by the output of the frequency determining means. A PLL circuit is characterized in that the carrier wave frequency is controlled to be constant by.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a PLL circuit according to the present invention. The same parts as those in the conventional example of FIG. In the present invention, reference numeral 11 compares the carrier wave reproduced by the carrier wave reproduction circuit 2 with the output of the fixed oscillator 12 which transmits at the normal carrier wave frequency fc to determine the frequency, and creates an AFC (automatic frequency) voltage according to the error frequency. The frequency discriminating circuit 13 is a variable reference oscillator, which is arranged in place of the fixed reference oscillator 7 in the conventional example, is applied with the AFC voltage, and controls its oscillation frequency fref.

Next, the operation of this embodiment will be described. Now, assuming that this circuit is a so-called lower heterodyne system in which fvco is lower than the frequency of the RF signal,
When the actual oscillation frequency fvco of the VCO is lower than the oscillation frequency fl of the VCO to obtain the desired IF frequency, the frequency of the IF signal, that is, the reproduced carrier frequency f.
c'becomes higher than the regular carrier frequency fc. In this case, the AFC voltage increases, and the frequency fref of the variable reference oscillator 12 is controlled to increase. As a result, V
The output fvco of CO4 is increased, that is, the deviation Δf from fl is decreased, and the reproduction carrier frequency fc ′ is decreased.

When fvco is higher than fl, the reproduction carrier frequency fc 'is controlled to be higher, contrary to the above. On the contrary, in the case of the upper heterodyne system, the control is reversed.

In this way, the deviation Δf is always controlled to be small by the operation of the AFC loop.
The reproduced carrier frequency fc 'is controlled so as to approach the regular carrier frequency fc.

Further, in the present circuit, the carrier wave is reproduced based only on the IF signal, but it may be reproduced based on the demodulated baseband signal. That is, a VCO that oscillates at the carrier frequency is provided in the carrier reproduction circuit,
The phase of the VCO may be controlled by the carrier frequency component included in the baseband signal.

[0021]

As described above, according to the present invention, even if the frequency step fs of the VCO becomes large, the frequency deviation Δf can be constantly reduced by the operation of the AFC loop, so that the carrier wave having an accurate frequency is reproduced. Can

[Brief description of the drawings]

FIG. 1 shows a block diagram of a PLL circuit according to the present invention.

FIG. 2 shows a block diagram of a PLL circuit in a conventional example.

[Explanation of symbols]

 1 frequency conversion circuit 2 carrier recovery circuit 3 demodulation circuit 4 VCO 5, 8 fixed frequency divider 6 variable frequency divider 9 phase comparator 10 LPF 11 frequency discrimination circuit 12 fixed oscillator 13 variable reference oscillator

Claims (2)

[Claims] 1. A frequency conversion circuit that frequency-converts a received RF signal into an IF signal, a demodulation circuit that demodulates this IF signal into a baseband signal, and a carrier wave is reproduced based on the IF signal and / or the baseband signal. A carrier recovery circuit, a VCO that oscillates a local oscillation signal, and this V
A variable frequency divider that variably divides the oscillation output of the CO based on a channel selection command, a reference signal generator that generates a reference signal, and a phase of the output of the reference signal generator and the output of the variable frequency divider. In a PLL circuit comprising a phase comparison means for comparing, and controlling the oscillation frequency of the VCO by using the output of the phase comparison means as a control voltage, the reference signal generating means is composed of a variable reference oscillator and A frequency discriminating means for discriminating a frequency is provided, and the carrier frequency is controlled to be constant by controlling the output frequency of the reference signal generating means by the output of the frequency discriminating means.
circuit. 2. The frequency discriminating means includes a fixed oscillator that oscillates at a carrier frequency and a frequency discriminating circuit that compares the output of the fixed oscillator with the frequency of the carrier and outputs a control voltage according to the difference. The PLL according to claim 1, wherein
circuit.