JPH09181542A - Differential amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the gain of a differential amplifier circuit from being changed even when output potential is changed by an input signal by controlling an output from a control means by 1st and 2nd input signals and changing the resistance value of a 1st emitter resistor by the output of the control means. SOLUTION: A resistor bias voltage control circuit 62 can change voltage applied to the N type epitaxial layer of an emitter resistor 54 in accordance with output voltage. Thereby the widening of a depletion layer in the resistor 54 which is fixed in conventional technology is changed. The rate of a change in a resistance value due to the widening of a depletion layer in a load resistor 58 can be set up to the same rate as the rate of a change in the resistance value of the emitter resistor 54. Thereby the gain of the differential amplifier circuit 51 can be fixed without depending upon output voltage. Since the thickness of an air layer formed on a P type semiconductor layer is changed by potential applied to an N type semiconductor layer, the resistance value can be changed in accordance with an input signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier circuit used in a monolithic integrated circuit.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram of a differential amplifier circuit 1 which is a typical conventional example. The differential amplifier circuit 1 includes NPN transistors 2 and 3, an emitter resistor 4, current sources 5 and 6.
And a current control circuit 7 and a load resistor 8.

A voltage V1 is applied to the base B of the transistor 2 from the input terminal 9, and a power supply voltage V is applied to the collector C.
cc is given. The emitter E of the transistor 2 is grounded via the current source 5. Base B of transistor 3
Is supplied with the voltage V2 from the input terminal 10, and the collector C is supplied with the power supply voltage Vcc through the current control circuit 7, the output terminal 11, and the load resistor 8. The emitter E of the transistor 3 is grounded via the current source 6. One end of the emitter resistor 4 is connected to the emitter E of the transistor 2 and the other end is connected to the emitter E of the transistor 3.

The differential amplifier circuit 1 converts the voltage generated by the difference between the input voltages V1 and V2 input from the input terminals 9 and 10 into a current by the emitter resistor 4 provided between the emitters E of the transistors 2 and 3. ing. This converted current flows through the current control circuit 7 to the load resistor 8,
The output voltage Vo is output from the output terminal 11. The resistance value of the emitter resistor 4 is r, and the resistance value of the load resistor 8 is R. Further, the current control circuit 7 controls the current flowing in by K (0 <
K) Amplify twice.

The operation of the differential amplifier circuit 1 will be specifically described by ignoring the base currents of the transistors 2 and 3 and assuming that the base-emitter voltage of each of the transistors 2 and 3 is constant. The current value supplied from the current sources 5 and 6 is I, and the current value flowing through the emitter resistor 4 is I1. Also, the voltage Vb
If e1 is the base-emitter voltage of the transistor 2 and the voltage Vbe2 is the base-emitter voltage of the transistor 3, I1 = {(V1-Vbe1)-(V2-Vbe2)} / r = ( V1−V2) / r (1) Therefore, the collector current Ic2 of the transistor 3 is Ic2 = I−I1 = I− (V1−V2) / r (2) Ic2 is amplified K times by the current control circuit 7. Assuming that the output voltage Vo is applied to the load resistor 8, the output voltage Vo is Vo = Vcc-R * Ic2 * K = Vcc-R * K * I + R * K * (V1-V2) / r (3). Therefore, the gain A of the differential amplifier circuit 1 is A = R × K / r (4)

The value that the output voltage Vo can take when the input voltages V1 and V2 change is determined within a range in which the collector current Ic2 flowing through the transistor 3 can change. That is, Ic2 = 0 to 2 × I (5), and at this time, the output voltage Vo changes within the range of Vo = Vcc to (Vcc-2 × I × R × K) (6).

FIG. 6 is a sectional view showing the structure of the load resistor 8 when the differential amplifier circuit 1 is realized by a monolithic integrated circuit, and FIG. 7 is a sectional view showing the structure of the emitter resistor 4. Since the emitter resistor 4 and the load resistor 8 have the same structure, they will be described with reference to FIG. The N-type epitaxial layer 22 is formed on the P-type semiconductor substrate 21, and the P-type diffusion layer 23 is further formed on the N-type epitaxial layer 22. The contacts 2 having conductivity on both ends of the P-type diffusion layer 23.
4, 25 are formed and the P-type diffusion layer 23 is used as a resistor. An N ⁺ type layer 26 is formed between the P type semiconductor substrate 21 and the N type epitaxial layer 22. The contacts 24, 25, 27 are insulated from each other by the insulating layer 29.

P-type diffusion layer 23 and N-type epitaxial layer 2
A reverse bias voltage is applied between 2 and 2 so that the current flowing through the P type diffusion layer 23 does not flow into the N type epitaxial layer 22. Generally, power supply voltage Vcc, which is the highest voltage applied to differential amplifier circuit 1, is applied to N type epitaxial layer 22 through contact 27 and N ⁺ type layer 28.

By applying the reverse bias voltage, a depletion layer 30 shown by a broken line is generated between the P type diffusion layer 23 and the N type epitaxial layer 22. When the depletion layer 30 is generated, the region (thickness) of the P-type diffusion layer 23 that functions as a resistance changes, and the resistance value changes.
Such a phenomenon is generally called a back gate effect.

In the load resistor 8 of the differential amplifier circuit 1, the potential on the output terminal 11 side changes from Vcc to (Vcc-2 as described above.
XIxRxK). Since the output voltage Vo is greatly different when the potential on the output terminal 11 side is Vcc and when it is (Vcc-2 × I × R × K), the contact 24 side and the contact 25 with respect to the reverse bias voltage.
The potential on the side is not constant, the depletion layer 30 spreads in a different manner, and the resistance value of the load resistor 8 changes.

As shown in FIG. 7, in the case of the emitter resistor 4, both ends of the P-type diffusion layer 23, which is the emitter resistor 4, are connected to the transistors 2 and 3 via the contacts 31 and 32, respectively.
Connected to the emitter E of. The N type epitaxial layer 22 is connected to the power supply voltage Vcc via the contact 33 and the N ⁺ type layer 28. P-type diffusion layer 23
The reverse bias voltage between the N-type epitaxial layer 22 and the N-type epitaxial layer 22 is the voltage Vcc-V1 + Vbe1 or the voltage Vcc-V2.
It is + Vbe2. Since the change of the reverse bias voltage is generally sufficiently small with respect to the change of the output voltage Vo, the spread of the depletion layer 30 remains almost unchanged.

As described above, when the diffused resistor formed by the PN junction is used as the resistor provided in the differential amplifier circuit 1, the gain A of the differential amplifier circuit 1 changes the output voltage Vo from the equation (4). Then, it can be seen that the gain changes. That is, there is an essential problem that a differential amplifier circuit having a constant gain A regardless of the output voltage Vo cannot be obtained.

The differential amplifier circuit 1 as described above is used as a driver or the like for applying a voltage to a liquid crystal display panel. When displaying on a liquid crystal display panel, when a direct current voltage is applied to the liquid crystal with respect to a reference voltage of the liquid crystal, the liquid crystal undergoes electrolysis and the quality of the liquid crystal deteriorates. In order to prevent this, the potential serving as the reference of the signal is switched every predetermined period to invert the polarity of the voltage applied to the liquid crystal, and the voltage is applied in an alternating current. By inverting the voltage in this manner, it is possible to prevent the direct current voltage from being applied to the reference potential of the liquid crystal between the reference potential in the non-inversion and the reference potential in the inversion. By the back gate effect in the resistor 8,
Since the gain is different between the non-inversion and the inversion, the amplitude of the signal superimposed on the reference potential of the signal is different, and a DC voltage is applied to the liquid crystal due to the difference in the signal amplitude. If this DC voltage is a little, electrolysis of the liquid crystal is caused, and when an image is displayed on the liquid crystal panel for a long time, the liquid crystal finally stops working. In other words, the life of the liquid crystal is determined by how the DC voltage applied to the liquid crystal is made zero.

FIG. 8 shows a graph for explaining changes in resistance values of the P-type diffusion layer 23 and the N-type epitaxial layer 22 with respect to the reverse bias voltage. In FIG. 8, the vertical axis represents the rate of change in resistance value, and the unit is percentage. The horizontal axis represents the reverse bias voltage, and the unit is volts.

Since the depletion layer 30 spreads differently depending on the concentration of the P-type diffusion layer 23, that is, the sheet resistance ρs of the P-type diffusion resistance, ρs = 1.3, 1.5, 1.7, 2.0 kΩ.
The four types of sheet resistance are shown below. Further, the graph shown in FIG. 8 shows that (voltage applied across the P-type diffusion) << (P
Reverse bias voltage between the type diffusion layer and the N-type epitaxial layer). That is, as shown in FIG. 7, it shows a change in resistance value when the depletion layer 30 spreads uniformly.

However, as for the load resistance of the differential amplifier circuit 1, the reverse bias voltage applied changes greatly as in the case where one end is connected to the power supply voltage Vcc and the other end is connected to the output voltage Vo. In some cases, the depletion layer 30 has an inclination as shown in FIG. P-type diffusion layer 23
If it is approximated that the voltage applied to V is linearly changed from the voltage Vcc to the voltage Vo, the voltage difference between the P-type diffusion layer 23 and the N-type epitaxial layer 22 is Vcc-Vcc (= 0).
To Vcc-Vo. It can be approximated that the thickness of the depletion layer 30 caused by the voltage difference linearly changes from 0 to a certain thickness. Therefore, when the depletion layer 30 is uniformly spread, the reverse bias voltage of (Vcc-Vo) / 2 may be considered to be applied uniformly. From the equation (3), the reverse bias voltage is (Vcc-Vo) / 2 = {R * K * I-R * K * (V1-V2) / r} / 2 (7) Based on the above assumption, how much the gain A changes when the output voltage Vo changes will be described by comparing the gain A in two cases.

(A) In the case of Vo = Vcc The reverse bias voltage applied between the P-type diffused resistor 23 and the N-type epitaxial layer 22 is 0 V from the equation (7), so the resistance value of the load resistor 8 is Is a preset R, and the gain A of the differential amplifier circuit 1 is A = R × K / r (8)

(B) In the case of Vo = Vcc-2 × I × R × K The reverse bias voltage applied between the P-type diffused resistor 23 and the N-type epitaxial layer 22 is I × R from the equation (7). × K (9) In equation (9), for example, I = 100 μ
When A, R = 18 kΩ and K = 5, the reverse bias voltage is 9V. Sheet resistance ρs of load resistor 8 is 2.0 kΩ
Then, from the graph of FIG. 8, the resistance value R of the load resistor 8 is
It becomes about 1.06 × R, and the gain A of the differential amplifier circuit 1 becomes A = 1.06 × R × K / r (10) Therefore, the gain A is 1.06 times different when the output voltage Vo is (A) and when it is (B). That is, there is an inherent problem that the gain changes due to the fluctuation of the output voltage Vo and the accurate amplification operation cannot be performed.

FIG. 9 is a load resistor 8 for explaining a conventional technique for solving the above problems.
FIG. In FIG. 9, the load resistance group 36 is formed by dividing the load resistance 8 into a plurality. In the sectional structure shown in FIG. 9, the same semiconductor layer as the load resistor 8 of FIG.
The same reference numerals are given and explanations are omitted. The characteristic of the load resistance group 36 shown in FIG. 9 is that the load resistance group 36 is formed by the P-type diffusion layer 23 on the N-type epitaxial layer 22 formed independently by the P ⁺ -type layer 37. is there. The load resistance group 36 includes load resistances 38a, 38b,
... (reference numeral 38 is used for generic names).

In the load resistance group 36, each N-type epitaxial layer 22 is not connected to the voltage Vcc but is connected to the contact having the higher potential of the two contacts connected to the load resistance 38. With such a structure, the reverse bias voltage applied to each load resistor 38 is lowered and the change of the depletion layer 30 is suppressed small. That is, the change in gain in the differential amplifier circuit 1 is suppressed to a small level.

[0021]

In the prior art shown in FIG. 9, since the load resistor 38 and the N-type epitaxial layer 22 are connected to each other, floating between the N-type epitaxial layer 22 and the P-type semiconductor substrate 21 is caused. The sum of the capacitance and the stray capacitance between the N-type epitaxial layer 22 and the P-type diffusion layer 23 is connected between the resistor and the ground potential (GND), and as shown in the circuit diagram of FIG. To form.
The formation of the low-pass filter 39 deteriorates the frequency characteristics of the differential amplifier circuit 1.

An object of the present invention is to provide a differential amplifier circuit whose gain does not change even when the output voltage changes.

[0023]

According to the present invention, in a differential amplifier circuit formed on a single semiconductor substrate, a first and a second NPN transistor are used as a differential pair, and a base of the first NPN transistor is used. A first input signal is supplied, a collector is supplied with a predetermined first potential, an emitter is supplied with a predetermined second potential lower than the first potential, and a base of the second NPN transistor is supplied with a first potential. A second input signal is applied to the collector, the first potential is applied to the collector via the first load resistor, the second potential is applied to the emitter, and both ends are applied to the emitters of the first and second NPN transistors. Differential amplifying means for outputting a potential between the collector of the second transistor and the first load resistor;
And a control unit that controls the resistance value of the first emitter resistor based on a second input signal. According to the present invention, the first NPN transistor is rendered conductive by the application of the first input signal, the second transistor is rendered conductive by the application of the second input signal, and the first NPN transistor is rendered conductive by the respective transistors being made conductive. A current flows through the 1-emitter resistor, and a potential based on the current is output. The resistance value of the first emitter resistor is controlled by the control means provided with the first and second input signals. Therefore, it is possible to prevent the gain of the differential amplifier circuit from changing even if the resistance value of the first emitter resistor changes according to the supplied signal and the output potential changes.

According to the present invention, the first emitter resistor is
A P-type semiconductor layer formed on the N-type semiconductor layer,
The control means applies a potential to the N-type semiconductor layer. According to the invention, the first emitter resistor is a P-type semiconductor layer formed on the N-type semiconductor layer. Electrodes for connection are provided at both ends of the surface of the P-type semiconductor layer so as not to contact each other, and the electrodes are connected to the respective emitters of the first and second NPN transistors. The potential output from the control means is supplied to the N-type semiconductor layer. Therefore, since the thickness of the depletion layer generated in the P-type semiconductor layer changes depending on the potential applied to the N-type semiconductor layer, the resistance value of the emitter resistance, which is the P-type semiconductor layer, changes and is input by the output of the control unit. The resistance value can be changed according to the signal.

According to the present invention, the control means comprises a third and a fourth NPN transistor as a differential pair, and a third NPN transistor is provided.
The first input signal is applied to the base of the transistor, the first potential is applied to the collector via the second load resistor, the second potential is applied to the emitter, and the fourth NPN transistor The second input signal is applied to the base, the first potential is applied to the collector, the second potential is applied to the emitter, and both ends are connected to the emitters of the third and fourth NPN transistors. A second emitter resistor, the second emitter resistor being included in the control means.
The load resistance has a resistance value of 1/2 of the first load resistance included in the differential amplifying means, and outputs a potential between the collector of the third NPN transistor and the second load resistance. . According to the invention, in the control means, the third NPN transistor is made conductive by the first input signal, and the fourth transistor is made conductive by the second input signal.
A potential between the collector of the transistor and the second load resistance is applied to the first emitter resistance. That is, as in the case of the differential amplifying means, the third and fourth NPN transistors are turned on to cause a current to flow through the second emitter resistance of the control means, and a potential is supplied to the first emitter resistance based on the current. Therefore, the output of the control means is determined according to the input first and second input signals, and the resistance value of the emitter resistance of the differential amplifying means changes according to the output of the control means, resulting in a difference even if the output potential changes. It is possible to prevent the gain of the dynamic amplification circuit from changing.

Further, the present invention is characterized by including first current control means for controlling the amount of current flowing between the collector of the second NPN transistor and the first potential. According to the invention, the first current control means is the second NPN.
Controls the current flowing between the collector of the transistor and the first potential. Therefore, included in the differential amplifier circuit,
For example, the amount of current flowing through the differential amplifier circuit can be controlled by the current control means without changing the values of the NPN transistor and the load resistance.

In the present invention, first current control means for controlling the amount of current flowing between the collector of the second NPN transistor and the first potential, the collector of the third NPN transistor, and the first And a second current control means for controlling the amount of current flowing between the electric potential and the electric potential. According to the present invention, the first current control means includes the second current control means.
The current flowing between the collector of the NPN transistor and the first potential is controlled, and the second current control means controls the amount of current flowing between the collector of the third NPN transistor and the first potential. Therefore, included in the differential amplifier circuit,
For example, the amount of current flowing through the differential amplifier circuit can be controlled by the current control means without changing the values of the NPN transistor and the load resistance.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram of a differential amplifier circuit 51 which is an embodiment of the present invention. Differential amplifier circuit 5
1 is a transistor 52,53, and an emitter resistor 54
, A current source 55, 56, a current control circuit 57, a load resistor 58, and a resistance bias voltage control circuit 62. The input voltage V1 is supplied to the base B of the transistor 52 from the input terminal 59, and the collector C is connected to the power supply voltage Vcc determined by the first potential.
The emitter E of the transistor 52 is grounded as being connected to the second potential via the current source 55. In this specification, a transistor is an NPN unless otherwise specified.
It is a transistor. The differential amplifier circuit 51 is formed as a monolithic integrated circuit, and is formed on, for example, a P-type semiconductor substrate.

The input voltage V2 is applied to the base B of the transistor 53 from the input terminal 60, and the collector C is supplied through the current control circuit 57 and the load resistor 58 to the power supply voltage Vc.
c. The emitter E of the transistor 53 is grounded via the current source 56. The current sources 55 and 56 supply the current I.

One end of the emitter resistor 54 is connected to the emitter E of the transistor 52, and the other end is connected to the emitter E of the transistor 53. The resistance value of the emitter resistor 54 is r, and the resistance value of the load resistor 58 is R. Since the cross-sectional view of the emitter resistor 54 is the same as that of FIG. 7 shown in the above-mentioned conventional technique, the following description will be given using the same reference numerals. Further, the sectional view of the load resistor 58 is the same as that of FIG. 6 shown in the above-mentioned prior art, and therefore, description will be given using the same reference numerals.

The resistance bias voltage control circuit 62 supplies an output based on the input voltages V1 and V2 supplied from the input terminals 59 and 60 to the emitter resistor 54. The configuration of the resistance bias voltage control circuit 62 will be described later. The current control circuit 57 is a circuit that controls the current flowing through the load resistor 58. The current control circuit 57 controls the inflowing current by K (0 <
K) Amplify twice.

FIG. 2 is a circuit diagram of the resistance bias voltage control circuit 62. The resistance bias voltage control circuit 62 has a configuration similar to that of the differential amplifier circuit 51. The transistors 72 and 73 in the resistance bias voltage control circuit 62 are
Corresponding to the transistors 52 and 53 of the differential amplifier circuit 51,
It has the same operating characteristics. The current sources 75 and 76 correspond to the current sources 55 and 56 and supply the current I. Further, the current control circuit 57 and the current control circuit 77 have the same operating characteristics.

In the resistance bias voltage control circuit 62, a current control circuit 77 and a load resistance 78 are provided between the collector C of the transistor 72 and the power supply voltage Vcc,
The potential between the current control circuit 77 and the load resistor 78 is applied to the emitter resistor 54 as the output voltage Vb from the output terminal 81. In the resistance bias voltage control circuit 62, the resistance value of the emitter resistance 74 is r, and the resistance value of the load resistance 78 is R / 2 which is 1/2 of the load resistance 58.

The output voltage Vb from the resistance bias voltage control circuit 62 will be described. The reverse bias voltage in the load resistor 58 of the differential amplifier circuit 51 is given by the equation (7) as in the above-mentioned conventional technique. The reverse bias voltage and the rate of change of the resistance are in a proportional relationship as shown in FIG. 8 and the load resistance 58 due to the change of the reverse bias voltage.
Considering the purpose of eliminating the change in the gain of the differential amplifier circuit 51 caused by the change in the resistance value of the load resistor 58, it is not necessary to apply the same voltage as the reverse bias voltage in the load resistor 58 to the emitter resistor 54. . The change in the reverse bias voltage in the load resistor 58 due to the change in the output voltage Vo and the change in the reverse bias voltage in the emitter resistor 54 due to the change in the output voltage Vh may be the same.

That is, the load resistance 58 is set to an arbitrary voltage VN.
The reverse bias voltage of the emitter resistor 54 may be a voltage to which the change in the reverse bias voltage in is added. That is,
The reverse bias voltage VR to be applied to the emitter resistor 54 is VR = VN- {R × K × (V1-V2) / r} / 2 (11) The voltage V1-applied to the P-type diffusion layer 23 of the emitter resistor 54.
Since Vbe1 or V2-Vbe2 is considered to be almost constant, the N-type epitaxial layer 22 of the emitter resistor 54 is formed.
The voltage VE to be applied to is VE = VR + V1-Vbe1 = VN + V1-Vbe1- {R * K * (V1-V2) / r} / 2 = VN- {R * K * (V1-V2) / r} / 2 (12) (where VN + V1-Vbe1 = VN (arbitrary voltage)
And). That is, if the voltage VE obtained by the equation (12) is supplied to the epitaxial layer 22 of the emitter resistor 54, the change amount of the reverse bias voltage in the load resistor 58 and the change amount of the reverse bias voltage in the emitter resistor 54 are made equal. You can

The resistance bias voltage control circuit 62 has the same configuration as the differential amplifier circuit 51, and the resistance value of the load resistor 58 is set to 1/2, so that the output voltage Vb of the resistance bias voltage control circuit 62 is set. With reference to formula (3), Vb = Vcc- (R / 2) * K * I-{(R / 2) * K * (V1-V2) / r} (13) Here, if Vcc−R × K × I / 2 = VN (14), the equation (13) is equal to the equation (12). That is, when the voltage Vb = VE and the output voltage Vb of the resistance bias voltage control circuit 62 is applied to the N-type epitaxial layer 22 forming the emitter resistor 54 of the differential amplifier circuit 51, the change amount of the reverse bias voltage in the load resistor 58 is increased. And the amount of change in the reverse bias voltage in the emitter resistor 54 can be made equal.

Next, the effect of applying the voltage VE obtained by the equation (12) to the N-type epitaxial layer 22 of the emitter resistor 54 will be verified. As in the above-mentioned conventional example, there are two cases, (A) when Vo = Vcc, and (B).
Gain A for the case of Vo = Vcc-2 × I × R × K
Will be compared and explained. The sheet resistance ρs of the load resistor 58 and the emitter resistor 54 is 2.0 kΩ.

(A) When Vo = Vcc From equation (7), the reverse bias voltage applied to the load resistor 58 is 0.
It becomes V, and the resistance value R of the load resistor 58 does not change. Further, the equation (7) becomes 0 = {R × K × I−R × K × (V1-V2) / r} / 2 (15), and if this equation (15) is modified, I = (V1 -V2) / r (16) Substituting equation (16) into equation (12), VE = VN−R × K × I / 2 (17) where R = 18 kΩ, K = 5, and I = 100 μA, and R × K × I = 9 V And When the voltage VN = 10.5V, VE = 10.5-9 / 2 = 6V (18) is applied to the N-type epitaxial layer 22 of the emitter resistor 54. When the resistance value of the emitter resistor 54 at this time is r, the gain A of the differential amplifier circuit 51 is A = R × K / r (19) from the equation (4).

(B) In the case of Vo = Vcc-2 × I × R × K The reverse bias voltage applied to the load resistor 58 from the equation (7) is I × R × K, and R = 18 kΩ as described above. , K
= 5 and I = 100 μA, the reverse bias voltage applied to the load resistor 58 is 9V.

The resistance value of the load resistor 58 is 1.06 times larger than that in the case of (A), and becomes 1.06 × R (20).

Further, the equation (7) can be expressed as I × R × K = {R × K × I−R × K × (V1-V2) / r} / 2 (21) By transforming (21), −I = (V1−V2) / r (22) Substituting equation (22) into equation (12), VE = VN + R × K × I / 2 (23) Here, If R × I × K = 9V and VN = 10.5V, then VE = 10.5 + 9/2 = 15V (24), and a voltage of 15V is applied to the N-type epitaxial layer 22 of the emitter resistor 54. When the resistance value of the emitter resistor 54 when VE = 6V is r, VE = 15V
The resistance value at the time of 6 is 6 when referring to the graph of FIG.
% Increase of 1.06 × r.

Therefore, the gain A of the differential amplifier circuit 51 is
From the formula (4), A = 1.06 × R × K / (1.06 × r) = R × K / r (25), and the gain A is the same as in the case of (A). Therefore, even if the output voltage Vo is the voltage Vcc, the voltage Vcc
Even if the gain is −2 × I × R × K, the gain A is the same, and it can be seen that the gain A does not change depending on the value of the output voltage Vo.

FIG. 3 is a circuit diagram of the differential amplifier circuit 51 provided with the current control circuit 91. The current control circuit 91 is configured to include transistors 92 and 93. The input voltage V3 is applied to the base B of the transistor 93 via the input terminal 94, and the base B of the transistor 92 is
The input voltage V4 is applied via the input terminal 95. The power source voltage Vcc is applied to the collectors C of the transistors 92 and 93.
And a load resistor 58 is provided between the collector C of the transistor 93 and the power supply voltage Vcc. The current control circuit 91 controls the collector current Ic flowing through the transistor 53 based on the input voltages V3 and V4, and controls the current flowing through the load resistor 58 in the range of 0 to Ic.

FIG. 4 is a circuit diagram of the differential amplifier circuit 51 provided with the current control circuit 101. The current control circuit 101 is
It is configured to include PNP transistors 102 and 103. Base B of PNP transistors 102 and 103
Is connected to the collector C of the PNP transistor 102, and the emitters E of the PNP transistors 102 and 103 are commonly connected to the power supply voltage Vcc. A load resistor 58 is inserted between the emitter E of the PNP transistors 102 and 103 and the power supply voltage Vcc. PNP transistor 10
The collector C of 2 is connected to the collector C of the transistor 53, and the collector C of the PNP transistor 103 is grounded.

In the current control circuit 101, by providing a plurality of PNP transistors whose terminals are connected similarly to the PNP transistor 103, for example, when n PNP transistors are provided, the collector current Ic flowing through the transistor 53 is Ic ×. It can be changed (n + 1) times.

Although each of the differential amplifier circuits 51 described above has a configuration including the current control circuits 61, 91, 101, it is a differential amplifier circuit that does not include the current control circuits 61, 91, 101. Good. Even when the current control circuit is not included, by setting K = 1, it is possible to perform the same operation as in the case where the current control circuit is provided, based on the above equations.

As described above, according to the embodiment of the present invention, the resistance bias voltage control circuit 62 capable of changing the voltage applied to the N-type epitaxial layer 22 of the emitter resistor 54 according to the output voltage is provided. Since the spread of the depletion layer of the emitter resistor 54, which is constant in the conventional technique, is changed, the rate of change of the resistance value due to the spread of the depletion layer of the load resistor 58 and the resistance value of the emitter resistor 54 are changed. The rate of change can be the same, and the differential amplifier circuit 5
The unity gain can be constant independent of the output voltage.

In the embodiment of the present invention, the transistors forming a differential pair in the differential amplifier circuit 51 are NPN.
Although the transistors 52 and 53 are used, the two transistors may be replaced with PNP transistors. When the transistor forming the differential pair is a PNP transistor, the load resistor 58 and the emitter resistor 54 described above are used.
In this configuration, the conductivity types of the semiconductor layers constituting the above are interchanged between the P type and the N type, and the power supply voltage Vcc and the ground voltage GND are interchanged. Even when the transistors forming the differential pair are PNP transistors, the same effects as those shown in the embodiment of the present invention can be obtained.

[0049]

As described above, according to the present invention, the output from the control means is controlled based on the first and second input signals, and the resistance value of the first emitter resistor is changed by the output of the control means. The first and second input signals can prevent the gain of the differential amplifier circuit from changing even when the output potential changes.

According to the present invention, the first emitter resistor is a P-type semiconductor layer formed on the N-type semiconductor layer, and the potential output from the control means is supplied to the N-type semiconductor layer. Therefore, depending on the potential applied to the N-type semiconductor layer, P
Since the thickness of the depletion layer formed in the p-type semiconductor layer changes, the resistance value of the first emitter resistor, which is the p-type semiconductor layer, changes according to the output potential of the control means, and the resistance value changes according to the input signal. be able to.

Further, according to the present invention, the control means controls the output potential based on the first and second input signals, and the resistance value of the first emitter resistor changes according to the output potential of the control means. The first and second input signals can prevent the gain of the differential amplifier circuit from changing even when the output potential changes.

Further, according to the present invention, the first current control means controls the current flowing between the collector of the second NPN transistor and the first potential, so that it is included in the differential amplifier circuit, for example, the NPN transistor. The amount of current flowing through the differential amplifier circuit can be controlled by the current control means without changing the value of the load resistance.

According to the present invention, the first current control means controls the amount of current flowing between the collector of the second NPN transistor and the first potential, and the second current control means controls the collector of the third NPN transistor. Included in the differential amplifier circuit, because it controls the amount of current flowing between the
For example, the amount of current flowing through the differential amplifier circuit can be controlled by the current control means without changing the values of the NPN transistor and the load resistance.

[Brief description of the drawings]

FIG. 1 is a differential amplifier circuit 51 according to an embodiment of the present invention.
FIG.

FIG. 2 is a circuit diagram of a resistance bias voltage control circuit 62.

FIG. 3 is a differential amplifier circuit 5 provided with a current control circuit 91.
1 is a circuit diagram of FIG.

FIG. 4 is a circuit diagram of a differential amplifier circuit 51 provided with a current control circuit 101.

FIG. 5 is a circuit diagram of a differential amplifier circuit 1 which is a typical conventional example.

FIG. 6 is a sectional view of a load resistor 8 when the differential amplifier circuit 1 is formed of a monolithic integrated circuit.

FIG. 7 is a cross-sectional view of an emitter resistor 4 when the differential amplifier circuit 1 is formed of a monolithic integrated circuit.

FIG. 8 is a graph showing changes in resistance values of P-type diffused resistors and N-type epitaxial layers with respect to reverse bias voltage.

FIG. 9 is a sectional view when the load resistor 8 is divided into a plurality of parts.

[Explanation of symbols]

 51 differential amplifier circuit 52, 53, 72, 73 transistor 54, 74 emitter resistor 55, 56, 75, 76 current source 57, 77 current control circuit 58, 78 load resistor 59, 60, 79, 80 input terminal 61, 81 Output terminal 62 Resistance bias voltage control circuit

Claims (5)

[Claims] 1. A differential amplifier circuit formed on a single semiconductor substrate, wherein a first and a second NPN transistor are a differential pair, and a base of the first NPN transistor receives a first input signal. , A collector is given a first potential, a emitter is given a second potential lower than the first potential, and a base of the second NPN transistor is given a second input signal. The first potential is applied to the collector via the first load resistor, the second potential is applied to the emitter, and the first emitter whose both ends are connected to the emitters of the first and second NPN transistors Differential amplifying means including a resistor for outputting a potential between the collector of the second transistor and the first load resistor; and the first emitter based on the first and second input signals. A differential amplifier circuit which comprises a control means for controlling the resistance value of the motor resistance. 2. The first emitter resistor is composed of a P-type semiconductor layer formed on an N-type semiconductor layer, and the control means applies a potential to the N-type semiconductor layer. The differential amplifier circuit described. 3. The control means uses a third and a fourth NPN transistor as a differential pair, the base of the third NPN transistor receives the first input signal, and the collector receives a second load resistor. Is applied with the first potential, the emitter is applied with the second potential, and the base of the fourth NPN transistor is applied with the second potential.
An input signal is applied, the collector is applied with the first potential, the emitter is applied with the second potential, and the third potential is applied.
And a second emitter resistor whose both ends are connected to the emitter of the fourth NPN transistor, wherein the second load resistor included in the control means has a resistance value that is ½ of the first load resistor included in the differential amplifying means. And the third
3. The differential amplifier circuit according to claim 1, which outputs a potential between the collector of the NPN transistor and the second load resistor. 4. The differential according to claim 1, further comprising first current control means for controlling an amount of current flowing between the collector of the second NPN transistor and the first potential. Amplifier circuit. 5. A first current control means for controlling the amount of current flowing between the collector of the second NPN transistor and the first potential, a collector of the third NPN transistor, and the first potential. 4. The differential amplifier circuit according to claim 3, further comprising second current control means for controlling the amount of current flowing between the two.