JPH09181289A - Partially fabricated silicon wafer and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the size and cost of ICs which are respectively constituted by pluralities of one-dimensionally arranged identical transistors and arranged in a matrix-like state on a partially fabricated silicon wafer through scribed lines. SOLUTION: The minimum machined width of an IC 2 is reduced to <=1.2μm by using a stepper and, at the same time, the width of a chip is reduced to <=400μm by narrowly forming scribed lines 20 in the length direction of the chip by writing the alignment mark of the stepper only on the scribed lines 20 in the width direction of the chip. The butt mark 21 of a defective chip is reduced to a diameter of 100-200μm by irradiating the mark 21 with laser light.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semi-finished silicon wafer product comprising an ultra-fine chip for supplying an original reading IC or a thermal transfer IC used in a fax machine and a method for manufacturing the semi-finished product.

[0002]

2. Description of the Related Art There is a contact image sensor head as an IC mounting substrate on which a plurality of elongated ICs are arranged one-dimensionally. FIG. 2C is a perspective view of the image sensor head. A plurality of image sensor ICs 2 are linearly arranged on the surface of the mounting substrate 6. Image sensor IC2
Signals are electrically connected to the wiring on the substrate 6 by wire bonds 23. The image sensor head is manufactured by the following method.

As shown in FIG. 2A, image sensor ICs 2 are formed in a matrix on the surface of a silicon wafer 1. After that, the electrical characteristics of the IC 2 are measured using a tester, and the bad mark 21 is attached to the defective product. Next, the silicon wafer 1 is separated into each IC 2 along the scribe line 20. Next, the ICs 2 which are good products only are selected and placed on the tray 22 as shown in FIG. Next, FIG.
As shown in (c), the ICs 2 are sequentially arranged on the surface of the mounting substrate 6 from the tray, and bonding is completed.

[0004]

However, such an IC
In the mounting board, there is a problem that cost reduction is difficult because the length of the IC cannot be shortened in principle. I
If the width of C is narrowed, the size of the bad mark is large and the alignment accuracy is low. Further, since the IC generally has a planar shape, it cannot be mounted on a cylindrical mounting board.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an IC mounting substrate which has a low manufacturing cost and which enables a non-planar substrate in order to solve the above conventional problems.

[0006]

In order to solve the above problems, the present invention comprises a semi-finished silicon wafer product and its manufacturing method by the following means. (1) In a semi-finished silicon wafer product in which a plurality of ICs are repeatedly provided on the surface of a silicon wafer in a matrix shape via scribe lines, the ICs are composed of a plurality of identical transistors arranged one-dimensionally and repeatedly. With a diameter of 100 on at least one IC surface
A semifinished silicon wafer product is provided with a bad mark of up to 200 μm.

(2) A plurality of ICs are repeatedly formed on the surface of a silicon wafer in the form of a macrocix via scribe lines.
Forming process, a polishing process for polishing the back surface of the silicon wafer to thin it, a probe test process for measuring the electrical characteristics of the IC, and a marking process for attaching a bad mark to the IC surface for defective products of the IC. In the method of manufacturing a semi-finished silicon wafer, the marking step is performed by laser irradiation to form a bad mark with a diameter of 100 to 2
Controlling the size to 00 μm is a method of manufacturing a semi-finished silicon wafer product.

(3) In the marking step, a step of emitting a laser beam from a YAG laser, a step of transmitting the laser beam to the vicinity of the silicon wafer with an optical fiber having a diameter of less than 100 μm, and a laser beam from the optical fiber are applied to the surface of the IC by an optical lens. The method of manufacturing a semifinished silicon wafer product according to (2) comprises the step of condensing and forming a heat damage region.

[0009]

The present invention enables a silicon wafer composed of ultrafine chips by forming a bad mark small by laser irradiation. Further, the laser irradiation is transmitted to the silicon wafer by a thin optical fiber, and a condenser lens is provided in the vicinity of the silicon wafer so that the laser light can be formed into a small spot and the bad mark can be reduced.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic sectional view of a bad marking step showing a method for manufacturing a semi-finished silicon wafer according to the present invention.

As shown in FIG. 1, before a bad mark 21 is attached to a defective IC chip 2, a plurality of ICs 2 are repeatedly formed in a matrix form on the surface of a silicon wafer through scrub lines 20 by a normal process. On the surface of each IC 2, the same transistors are arranged one-dimensionally in the length direction of the chip.

For example, when the IC2 is a one-dimensional image sensor IC2, phototransistors are provided in the direction of the length of a 4-bit multiple chip. In the case of the IC 2 for a thermal head, high breakdown voltage trouble transistors for resistance heating are provided in a line along the chip length direction in a multiple of four bits. Further, the width of the chip is formed to be narrower than 400 μm in order to reduce the cost. The width of the chip is the length between the scribe line 20 center and the scribe line 20 center.
In order to reduce the chip width, the width of the scribe line 20 is reduced to 60 μm or less. A minimum processing width is 1.2 μm or less using a stepper for photolithography of IC2. The alignment mark required to use the stepper is a scribe line 20 of 60 μm or less.
It is difficult to set up. Therefore, the scribe line 20 in the length direction of the chip is thinned to 60 μm or less, and the scribe line 20 in the width direction of the chip is thickened to 100 μm of the conventional one, and the alignment mark is provided on the thick scribe line 20.

The width of the chip 2 is 2 due to the above-mentioned measures.
It can be made as thin as about 80 μm. The length depends on the required number of bits, but it is generally 4 to 12 times longer than the chip width.
Lengths between mm are common. A circuit or the like is printed on the silicon wafer 1 by a stepper on the surface of the silicon wafer, and subsequently elements are formed. Then, the back surface of the silicon wafer 1 is polished to reduce the thickness of the silicon wafer 1. In the case of the 6-inch wafer 1, the silicon wafer 1 having a thickness of about 600 μm is thinned to about 300 to 400 μm.

Next, the silicon wafer 1 is measured by an IC tester.
The electrical characteristics of all IC2 on the surface are measured. For the defective product, a bad mark 21 is attached to the surface of the defective IC2 chip by a marking process so that the defective product can be identified. FIG.
As shown in, the laser beam emitted by the YAG laser 10 is a thin optical fiber 1 having a diameter of 100 μm or less.
It is guided to the vicinity of the silicon wafer 1 by 1. A condenser lens 12 is provided at the exit of the optical fiber 11 at a distance of 1 to 2 cm from the surface of the silicon wafer 1. The laser beam emitted from the optical fiber 11 is applied to the defective chip of the silicon wafer 1 by the condenser lens. Bad I
When the C2 chip is irradiated with the laser beam, the temperature of the C2 chip locally rises, and a heat damage region is formed on the surface of the defective chip to form the bad mark 21.

FIG. 2A is a plan view of a defective IC chip having a bad mark 21. According to the present invention, the size of the bad mark 21 is much smaller than that of the conventional ink method, and the bad mark 21 can be formed with a diameter of 100 to 200 μm. Therefore, it is possible to form a semi-finished silicon wafer having a chip width of less than 400 μm. The bad mark 21 can be made small by condensing the laser beam by using a condensing lens that is close to the optical fiber 11 and the silicon wafer 1. When the bad mark 21 is attached by the laser beam, there is a problem that fragments due to damage scatter on the adjacent chips. However, by confining the laser beam to a very small area, it is possible to prevent debris from scattering on the adjacent chips. In the examples, Y
The wavelength of the AG laser is 1.06 μm and is 10 per second.
It is carried out by pulse driving of the emission. Oscillation time width is 100
The output energy is 50 mJoule in μsec.

The bad mark 21 caused by laser irradiation is more difficult to distinguish than the bad mark 21 caused by ink. Therefore, as shown in FIG. 3, it is necessary to provide a bad mark identifying pattern 31 similar to the bad mark 21 in the vicinity of the bad mark 21. Generally, pads or thick aluminum wiring are used. The existence of the bad mark 21 can be accurately checked by checking whether the bad mark exists near the bad mark identifying pattern 31.

The bad mark recognition patterns 31 are formed adjacent to each other within a distance of 100 μm from the bad mark formation position. The bad mark recognition pattern 31 is formed of an aluminum film. At the bad mark formation position, aluminum wiring is provided so that the bad mark 21 is formed on the aluminum film. The aluminum film at the bad mark formation position is electrically connected to an element such as a transistor as a wiring. That is, the pad is an aluminum pattern provided in a size of about 100 μm × 100 μm for electrical connection with the outside of the IC 2. However, the aluminum pattern of the bad mark identifying pattern 31 is in an electrically floating state.

FIG. 4 is an electric block diagram of an integrated circuit for a thermal head used for resistance heating the thermal paper. It is an IC that controls the current flowing through a plurality of resistances that resistance-heats the thermal paper. The thermal head (not shown) is provided with a large number of heating resistors having a width of, for example, 10 cm at substantially equal intervals. For each of the plurality of heating resistors linearly provided in the print width direction, a driving high voltage transistor 44 is electrically provided in series between the high voltage power supplies. The high breakdown voltage transistor 44 is a preamplifier circuit 43.
Driven by The preamplifier circuit 43 operates by receiving the signal from the driver strobe input terminal STBX and the output signal from the latch circuit 42. Latch circuit 42
Is the data latch signal LCHX and the flip-flop circuit 41.
It operates by inputting signals from and. As shown in FIG. 4, the preamplifier circuit 43 and the latch circuit 4 are provided in order to sequentially turn on / off each driver transistor 44.
2 and the flip-flop circuit 41 are repeatedly laid out periodically along the length direction of the IC chip 2.
The driver transistor 44 is periodically and repeatedly provided in the chip length direction in the same manner as the heating resistor along the printout direction.

FIG. 5 is a plan view of the ultrafine chip of the present invention. The output of the driver transistor 44 is the pad 9P.
To pad 72P are composed of 64 bits. For the driver transistor 44, the thickness of the gate insulating film is 100Å−200Å, and the optimum value is 150 ± 15Å. A high voltage of 30 V or more is applied to the drain electrode of the driver transistor 44, that is, the pad 9P to the pad 72P. Despite the high breakdown voltage, the current driving capability per unit area is increased by thinning the gate insulating film. By increasing the driving capacity per unit area, the chip width can be reduced to 0.35 mm.

FIG. 6 is a sectional view of the chip width of the thermal head IC taken along the line AA 'in FIG. The present invention
The cost can be reduced by narrowing the chip width of the thermal head IC. In order to reduce the chip width, not only the area of the driver transistor 44 is significantly reduced but also the scribe portion 63 and the distance between the scribe and the pad are shortened. As shown in FIG. 6, the substrate is not grounded by the aluminum wiring 68 on at least one side of the scribe portion 63. In order to shorten the distance between the scribe portion 63 and the pad 69, the scribe portion 63 has
The intermediate insulating film was left on the substrate 61. The passivation film 60 is removed in order to extend the life of the dicing blade during scribing. The scribe portion 63 is provided with an impurity region 65 of the same conductivity type as the substrate 61 to stabilize the substrate potential. The main pattern portion 64 is provided inside the separation region 66.

In the thermal head IC of the present invention, since the chip is extremely thin and long, it is sufficient to ground the substrate potential by the aluminum wiring 768 only on one side of this pattern as shown in FIG. Is. Therefore, it is not necessary to provide the ground of the substrate potential on both sides of the scribe portion, and it is possible to bring about a synergistic effect of forming a chip thinner. The pattern size of the aluminum film for the pad is 90μ
It is about m × 90 μm. Therefore, since there are at least two pads in the chip width direction, the chip width can be reduced to about 180 μm. In the case of a thermal head IC having two pads in the chip width direction, it is possible to realize an IC with a narrow chip width of 180 μm-350 μm.
96-bit or 144-bit thermal head I
In the case of C, the pads are linearly aligned with the puddle in the chip length direction. In this case, since three pads are arranged in the chip width direction, an IC having a thin chip width of 270 μm-440 μm can be realized. The functions of the pad numbers and pad names (terminal names) shown in FIGS. 4 and 5 are shown in Table 1 in FIG.

[0022]

As described above, since the bad mark is formed by the heat damage due to the laser irradiation focused on the small area, the very thin I of 400 μm or less is obtained.
C can now be manufactured. By being able to make it extremely thin, it was possible to reduce the cost and size of the IC.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing a method for manufacturing a semi-finished silicon wafer product of the present invention.

2A to 2C are diagrams showing the order of steps of a conventional method for manufacturing an IC mounting substrate, FIG. 2A is a plan view of a silicon wafer, and FIG.
Is a plan view of a chip placed in a tray, and (c) is a perspective view of an IC mounting substrate at the time of completion.

FIG. 3 is a plan view of a semi-finished silicon wafer product of the present invention.

FIG. 4 is an electrical block diagram of a thermal head IC of the present invention.

FIG. 5 is a plan view of a thermal head IC of the present invention.

6 is a cross-sectional view of the chip taken along the line AA ′ of FIG.

7 is a function list of pad numbers and pad names in the embodiments of FIGS. 4 and 5. FIG.

[Explanation of symbols]

 1 Silicon wafer 2 IC 10 YAG laser 11 Optical fiber 12 Focusing lens 21 Bad mark

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] March 7, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Figure 7

[Correction method] Change

[Correction contents]

FIG. 7 is a table showing a function list of pad numbers and pad names in the embodiments of FIGS. 4 and 5;

Claims (3)

[Claims] 1. A semi-finished silicon wafer product in which a plurality of ICs are repeatedly provided on the surface of a silicon wafer in the form of a macricks via scribe lines, wherein the ICs are composed of a plurality of identical transistors arranged one-dimensionally and repeatedly. A semi-finished silicon wafer product characterized in that a bad mark having a diameter of 100 to 200 μm is provided on the surface of at least one of the ICs. 2. A step of repeatedly forming a plurality of ICs on the surface of a silicon wafer via a scribe line in the shape of a macroix, a polishing step of polishing the back surface of the silicon wafer to make it thin, and an electrical characteristic of the ICs. In a method of manufacturing a semi-finished silicon wafer product, which comprises a probe test step of measuring and a marking step of attaching a bad mark to the surface of the IC for defective products of the IC, the marking step is to irradiate the bad mark by laser irradiation. A method of manufacturing a semifinished silicon wafer product, which is controlled to a size of 100 to 200 μm. 3. The marking step includes the step of emitting a laser beam from a YAG laser, the step of transmitting the laser beam to the vicinity of the silicon wafer with an optical fiber having a diameter of less than 100 μm, and the laser beam from the optical fiber by an engineering lens. 3. The method for manufacturing a semi-finished silicon wafer product according to claim 2, further comprising the step of condensing light on the surface of the IC to form a heat damage region.