JPH09179778A - Method and device for interleaving memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain both of the flexibility of memory constitution and high performance based upon interleaving. SOLUTION: An address boundary register 404 indicating an address area in a memory board group constituting an interleaving group, an interleaving register 405 indicating the number of memory boards belonging to each interleaving group, and a memory board selecting circuit 401 for outputting an access slot number 406 corresponding to a memory board to be accessed in accordance with the address upper bits 402 and address lower bits 403 of an access address to the memory board and the set contents of the registers 404, 405. Plural interleaving groups each of which is obtained by bundling memory boards having equal capacity in each 2's power unit are formed from the memory board group having various capacity and loaded on a slot and interleaving is executed in each interleaving group.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory interleaving technique, and more particularly to a technique effective when applied to a memory access control of an information processing system or the like including a plurality of memory boards having various storage capacities.

[0002]

2. Description of the Related Art For example, Iwanami Shoten Co., Ltd., 1990
"Iwanami Information Science Dictionary" published on May 25, 2013, P43-P4
As described in the literature such as 4, etc., the memory has a multi-bank configuration so that the spatial / temporal locality of the reference memory is relaxed for the purpose of speeding up memory access, particularly improving throughput. A so-called memory address interleaving technique in which memories referred to by continuous addresses are dispersed among banks is generally used.

On the other hand, with the rapid development of semiconductor memory technology, the capacity of semiconductor memory devices mounted on each memory board (bank), which is a unit of mounting, becomes different.
The storage capacity of each board tends to vary, and from the viewpoint of effective use of memory boards, it is desired to be able to mount memory boards of various capacities in a system.

[0004]

In order to realize the above-mentioned interleaving, it is desirable to set the capacities of the banks of the memory to be equal to each other, and it is difficult to realize interleaving in a system in which banks having different capacities are mixed. Met. Further, it is difficult to realize even when the number of banks is not a power of 2, and it is necessary to mount a remainder calculation circuit having a large logic scale.

Regarding the latter technical problem, a general N-way interleave is realized by combining full adders under the condition that the capacities of the banks of the system are equal to each other, thereby reducing the load on the logical scale. A technique to reduce the load is disclosed in Japanese Patent Laid-Open No. 5-113930.
Since there is a constraint that the capacities of the banks must be equal to each other, it is difficult to realize interleaving in a combination of banks having various capacities.

An object of the present invention is to provide a memory interleaving technique capable of easily realizing interleaving in a storage device constructed by a plurality of memory blocks having various capacities without increasing the logic scale more than necessary. To provide.

Another object of the present invention is to facilitate interleaving in a memory device constructed by a plurality of memory blocks having the same capacity and having the same number of constituents that are not powers of 2 without increasing the logical scale more than necessary. It is to provide a memory interleave technology that can be realized.

Still another object of the present invention is to provide a memory interleaving technique capable of improving the performance of an information processing system including a storage device constructed by a plurality of memory blocks having various capacities.

Still another object of the present invention is to provide a memory capable of improving the performance of an information processing system including a storage device constructed by a plurality of memory blocks whose capacities are equal to each other and whose number of constituents is not a power of two. It is to provide interleave technology.

Still another object of the present invention is to provide a memory interleave technique capable of improving the availability of hardware used for constructing a storage device.

[0011]

According to the memory interleaving method of the present invention, one or a plurality of interleaving groups are formed by bundling memory block groups having equal capacities in the system in units of powers of two. Interleaving The interleaving is performed for each group.

Further, the interleaving apparatus of the present invention refers to an address boundary register for indicating an address area of a unit memory block group, an interleave register for indicating the number of interleave blocks, an address boundary register and an interleave register. Memory block selecting means for determining a memory block to be accessed. Further, the memory block selecting means includes a comparator for comparing the address upper bit and the address boundary register to determine the memory block group to which the memory block belongs, and the address lower bit to determine the memory block position in the interleave group. And an adder for adding the interleaved leading block number calculated from the comparison result of 1.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a conceptual diagram for explaining the concept of interleaving realized by a memory interleaving method and apparatus according to an embodiment of the present invention, and FIGS.
FIG. 1 is a conceptual diagram showing an example of a configuration of an information processing system including a memory interleaving device in which a memory interleaving method according to an embodiment of the present invention is implemented.

First, the concept of the memory interleaving method of the present embodiment will be described with reference to FIG. For example, 2GB
4 memory blocks, 1GB memory block 3
When a storage device is constructed by a total of seven memory blocks, the memory interleaving method according to the present embodiment has a 4-way interleave of 2 GB, a 2-way interleave of 1 GB, and a 1-way without interleave.
The combination is GB. As in this example, in the present embodiment, memory blocks that are generally equal to each other are interleaved with a way number as large as a power of 2.

In the following description of the embodiments, the case where the memory blocks to be interleaved are memory boards that are individually attached to and detached from the system will be described as an example, but any independently accessible memory block can be used. It goes without saying that it can be applied to a unit storage medium.

In the present embodiment, in order to realize the above interleaving, an access reception determination unit 203 is provided in the memory board 202 in the bus connection system as shown in FIG.
Further, in the switch coupling type system as shown in FIG. 3, the access destination judging unit 301 is provided in the processor board 201.

FIG. 2 shows a plurality of processor boards 201, and a memory board 202, a processor memory bus 204.
2 is an example of the configuration of a bus-coupled multiprocessor computer system that is linked by. The memory space is address-mapped, and it is determined which of the memory boards 202 the memory to be accessed is mounted on is determined by the processor board 201.
The address output from all memory boards 202
Then, the access reception determination unit 203 provided in the memory board 202 checks whether or not it is an access to its own memory board. In the bus-coupled multiprocessor computer system as shown in FIG. 2, the components described below for implementing the memory interleaving method of this embodiment are arranged in the access reception determination unit 203.

FIG. 3 shows a plurality of processor boards 201, a memory board 202, and a connection switch 302.
2 is an example of the configuration of a switch-coupled multiprocessor computer system that is linked by. Although the memory space is also address-mapped, the access destination determination unit 301 provided in each processor board 201 that is the access request source determines which memory board 202 the access target memory is mounted on. .

That is, the memory board 20 to be accessed
To specify 2, the processor board 201 outputs the transaction header 701 to the connection switch 302 for each transaction 700 as illustrated in FIG. The connection switch 302 transfers the transaction body 702 output from the processor board 201 following the header to the designated memory board 202 according to the header information. The memory board 202 accesses a predetermined memory according to the access address in the transaction body 702. If the access is a read, the return data is returned to the processor board 201 that has made the access. For this purpose processor board 2
The transaction body 702 output from 01 includes a processor ID indicating the processor board 201 that is the access source, and the memory board 202 holds this until the return data is returned. Creates a header for designating the processor of the return destination and outputs it to the connection switch 302. In the switch-coupled multiprocessor computer system as shown in FIG. 3, the constituent elements described below for implementing the memory interleaving method of this embodiment are grouped together in the access destination determination unit 301 or the access destination determination unit 301.
And the connection switches 302 are distributed and arranged.

FIG. 4 is a conceptual diagram showing an example of the configuration of the access reception determination unit 203 in this embodiment. Memory board selection circuit 40 for determining an access destination memory board
An m-bit upper address bit 402 and an n-bit lower address bit 403 are input to 1, and the access slot number 406 of the access destination memory board is output. The access slot number 406 and the slot number register 409 indicating the slot number of the memory board 202 to which the access reception determination unit 203 belongs are compared by the comparator 407.
Access start signal 40 when compared by
8 is output. An address boundary register 404 indicating the boundary of the address area of each memory board 202 is connected to the memory board selection circuit 401. An interleave register 405 is connected to indicate the number of interleave ways of the memory board 202.

FIG. 5 is a conceptual diagram showing a configuration example of the access destination determination unit 301 in this embodiment. Memory board selection circuit 401 for determining access destination memory board
Similar to the configuration of the access reception determination unit 203 shown in FIG. 4, an m-bit upper address bit 402, an n-bit lower address bit 403, and an address boundary register 4
04, the interleave register 405 is connected. The access slot number 406 is output from these values, the access real slot number correspondence register 501 is referenced using this value as a pointer, and the connection switch 3
A transaction header 701, which serves as routing information No. 02, is output.

The access real slot number correspondence register 501 is arranged in the connection switch 302, the transaction header 701 is loaded with the information of the access slot number 406 which is the output of the memory board selection circuit 401, and the destination memory board 202. It is also possible to realize the real slot number of the above by using the access real slot number correspondence register 501 by the connection switch 302. In that case, a plurality of processor boards 201
Since the same access real slot number correspondence register 501 is not shared between the two, and it is sufficient for one location in the connection switch 302, there is an effect that the configuration is simplified.

FIG. 6 is a conceptual diagram showing an example of the configuration of the memory board selection circuit 401 of this embodiment. In the example of FIG. 6, the maximum total memory capacity is 32 GB, the maximum number of memory boards is 8, and the capacity per memory board is 256 kB to 4 GB. Address high-order bit 402 is 8
The lower bit 403 of the address refers to 3 bits. The address boundary register 404 consists of eight registers corresponding to each memory board. Similarly, the interleave register 405 is also composed of eight registers. The access slot number 406 is a 3-bit signal that takes values 0 to 7. Each address boundary register 40
A value indicating the total capacity in the same interleave block is held in 4-0 to 7 as the upper address bits. An example of the set value for the capacity is shown in the table of FIG. That is, the capacity of a certain memory board 202 is 0.25.
If GB is not interleaved, the value 01 is set.
Also, for example, two memory boards each have a total of 0.5 GB each, 1
When interleaving with two units in GB, set the value 04 for both units.

The interleave register 405 holds the number of interleaves. That is, the value of n is set in the interleave register 405 with respect to the number of interleaves of 2 n. An example of set values is shown in the table of FIG. The setting of these registers is performed at the time of initial setting of the system as described later.

The 8-bit address high-order bits 402 are the comparator 601 (eight units 601-0 to 601) and the comparator 60.
2 (seven of 602-1 to 7) are compared with the values of the address boundary registers 404-0 to 404-7, and the address areas are sorted. An AND circuit 603 which is a logical product of a pair of comparators 602 and 601 is whether or not it is within each area.
Output from From the comparator 601-0 indicating that the output of each AND circuit 603-1 to 7 is set to 1 to 7 and that the address is smaller than the setting value of the 0th 404-0 of the address boundary registers 404-0 to 404-7. Is encoded as 3 bits by the encoder 604. The output value of the encoder 604 indicates the youngest memory board in the interleave group when the memory board to be accessed is interleaved in combination with another memory board. The sum of this output and the lower address bit 403 is taken by the half adder 605. The sum of the least significant address bits 403-0 is the half adder 605.
-By 0, the sum of the lower 2 bits is the half adder 605-1
Therefore, the sum of the lower 3 bits is half adder 605-2.
Are calculated respectively.

On the other hand, the output of the encoder 604 is also added to the selector 606, and the interleave register corresponding to the access address area is selected from the interleave register 405 from 405-0 to 405-7. This value is added to the selector 607 and according to the setting of the interleave register 405, the value of the address boundary is output as it is when there is no interleaving, and when the value is 1, it is a two-unit interleave and the value of the half adder 605-0, the value of 2 Is 4 units interleaved, the value of half adder 605-1, value 3
In the case of, eight units are interleaved, and the value of the half adder 605-2 is output. As a result, access slot number 40
An interleaved access slot number 406 having a predetermined lower address bit as an offset address with respect to the youngest number in the interleave group is output to 6.

In the interleave of the present embodiment realized as described above, the memory boards 202 to be accessed are distributed for each interleave group of the memory boards 202 having the same capacity with respect to the sequential access, so that the parallel execution degree is improved. Work to do.

Next, an example of a method of setting each register in the switch coupled multiprocessor computer system as shown in FIG. 5 will be described. FIG. 9 is a flowchart showing an example of the setting procedure. In the following description, it is assumed that the memory board 202 has a capacity of 0.25 GB to 4 GB as in the example described with reference to FIGS. 6, 7, and 8.

In step 1 (S1), the memory slot is temporarily set. That is, the number of the memory boards 202 is substituted for the variable n on the program, and the slot numbers of the memory boards 202 mounted are simply set in the access real slot number correspondence register 501 (S (k)) in the ascending order.

In step 2 (S2), all the memory boards 202 are fully mounted and no interleave is set, and the address boundary register 404 (BND) and the interleave register 405 (i) are set. That is, all 0s are shown in the interleave register 405 (i), and 4 GB each is shown in the address boundary register 404 (BND) up to the number of mounted memories. 10h × (k + 1)
(10h, 20h, ..., n0h) is set.

In step 3 (S3), each memory board 2
Check the capacity of 02. Each memory board from 0 to n is accessed at a boundary address for each 0.25 GB, and the mounted capacity is known from the address in error.
In the case of the present embodiment, since the most significant digit of hexadecimal representation matches the memory board number, memory board 0 has a capacity of 0.
01000000 to see if it is 25 GB
Access 0h. 0 if this is no error
It is checked whether the installed capacity is 0.5 GB depending on whether or not an error occurs by accessing 20000000h. In this way, when there is no error until 0F0000000h is accessed, the mounted capacity is 4 GB. Similarly, address 110000000 is applied to the memory board 1.
Check from h to 1F0000000h. By repeating this, the capacity up to the memory board n is investigated. In the present embodiment, it has been described that each memory board responds with an error when it receives an access exceeding the mounting range. However, the same method can be used for reporting methods other than the error.

At step 4 (S4), the main setting for each register is performed. From the obtained capacities of the respective memory boards 202, the set values of the interleave register 405 are determined by bundling the memory boards 202 having a capacity as large as 2, 4, or 8 and having the same capacity as an interleave group. Further, the following criteria are applied in order to determine the set value of the access real slot number correspondence register 501 so that the memory board 202 is allocated from the lower address. That is, (1) the memory board 202 belonging to the interleave group. (2) The total capacity of the interleave group to which it belongs is large. (3) The number of interleave groups to which it belongs is large. (4) The memory board 202 has a large capacity. (5) It is installed in the youngest slot. The total capacity of the interleave group is set in the address boundary register 404 (BND).

If, as illustrated in FIG. 12, 4 GB
2 memory boards are installed in slot numbers 3 and 4, and a 2 GB memory board is installed in slot 6, 0.5G.
If there are 3 B memory boards and 6 in total installed in slots 0, 7, and 23, 2 4 GB and 0.5 GB
The two units installed in the slots 0 and 7 of the above are two-way interleaves, respectively. So interleave register 4
The setting value of 05 is from i0 (405-0) to i3 (405-
3) is a value of 1 indicating two-way interleaving, the remaining i4
The value i0 (405-7) becomes 0 from (405-4).

Further, as illustrated in FIG. 11, the address boundary register 404 includes BND0 (404-0) and BND0 (404-0).
ND1 (404-1) and 20h, B showing 8GB in total
ND2 (404-2) and BND3 (404-3) with a total of 1 GB and the previous 8 GB added, giving a total of 9 GB 2
Set 4h. Furthermore, 2 for BND4 (404-4)
GB + 9GB 2Ch showing 11GB in total, BND5 (4
04-5) is set to 2Eh indicating 0.5GB + 11GB total 11.5GB. Then, 0 is set to BND6 (404-6) and BND7 (404-7) to indicate that the memory board 202 is not mounted. The access real slot number correspondence register 501 has pointers 0, 1,
03h, 04h, 00 for 2, 3, 4 and 5, respectively
h, 07h, 06h, 17h are set. As a result, in order from the lowest address, slots 3 and 4 have a 2-way interleave of 8 GB in total, and slots 0 and 7 have a 2-way interleave of 1 GB in total.
The address space distribution is set to way interleave, 2 GB no interleave in slot 6 and 0.5 GB no interleave in slot 23.

As described above, according to the memory interleaving method and apparatus of the present embodiment, even in a system in which memory boards 202 having different capacities are mixed, memory boards having the same capacity can be interleaved as a group. , Memory configuration flexibility and data transfer rate (throughput) between the processor board 201 and the memory board 202 by interleaving
It is possible to realize a system that is compatible with the improvement of.

Further, in order to realize interleaving, unlike the conventional case, the capacity of each memory board 202 and the number of mounted boards are not limited to a specific value, and a plurality of memory boards 202 having various capacities are provided. Can be implemented in any combination, and the availability of hardware such as the memory board 202 that constitutes the storage device of the system is improved.

Further, as hardware for realizing interleaving, it suffices to provide simple comparators and half adders and registers in the number of memory boards 202, and a remainder calculation circuit having a large logical scale is not necessary. Yes,
The scale of hardware does not increase more than necessary.

Further, the initial setting of the hardware can be easily and automatically carried out, and the management operation of the interleave device of the system can be simplified and the labor can be saved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say, there is.

[0041]

According to the memory interleaving method and apparatus of the present invention, it is possible to easily realize interleaving in a storage device constructed by a plurality of memory blocks having various capacities.

Further, there is an effect that it is possible to easily realize interleaving in a storage device constructed by a plurality of memory blocks whose capacities are equal to each other and whose number of constituents is not a power of 2.

Further, it is possible to improve the performance of the information processing system including the storage device constructed by a plurality of memory blocks having various capacities.

Further, there is an effect that it is possible to improve the performance of the information processing system including the storage device constructed by a plurality of memory blocks whose capacities are equal to each other and the number of components of which is not a power of 2.

Further, the effect that the availability of the hardware constituting the storage device can be improved is obtained.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram illustrating the concept of interleaving realized by a memory interleaving method and apparatus according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram showing an example of a configuration of a bus-coupled multiprocessor system including a memory interleave device in which a memory interleave method according to an embodiment of the present invention is implemented.

FIG. 3 is a conceptual diagram showing an example of a configuration of a switch-coupled multiprocessor system provided with a memory interleaving device in which a memory interleaving method according to an embodiment of the present invention is implemented.

FIG. 4 is a conceptual diagram showing a configuration example of an access reception determination unit that constitutes the memory interleave device according to the embodiment of the present invention.

FIG. 5 is a conceptual diagram showing a configuration example of an access destination determination unit that constitutes the memory interleave device according to the embodiment of the present invention.

FIG. 6 is a conceptual diagram showing an example of a configuration of a memory board selection circuit that constitutes the memory interleave device according to the embodiment of the present invention.

FIG. 7 is an explanatory diagram showing an example of setting values set in an address boundary register in the memory interleave device according to the embodiment of the present invention.

FIG. 8 is an explanatory diagram showing an example of setting values set in an interleave register in the memory interleave device according to the embodiment of the present invention.

FIG. 9 is a flowchart showing an example of a setting procedure of an address boundary register and an interleave register in the memory interleaving method and device according to the embodiment of the present invention.

FIG. 10 is a conceptual diagram showing an example of a transaction configuration in a switch-coupled multiprocessor system equipped with a memory interleave device for implementing a memory interleave method according to an embodiment of the present invention.

FIG. 11 is a conceptual diagram showing an example of a process of calculating a setting value for an address boundary register in the memory interleaving method and device according to the embodiment of the present invention.

FIG. 12 is a conceptual diagram showing an example of a mounted state of a memory board in the memory interleaving method and device according to the embodiment of the present invention.

[Explanation of symbols]

201 ... Processor board (access request source), 202
... memory board (memory block) 203 ... access reception determination unit 204 ... processor memory bus 301 ...
Access destination determination unit, 302 ... Connection switch, 4
01 ... Memory board selection circuit (memory block selection means), 402 ... Address upper bit, 403 ... Address lower bit, 404 ... Address boundary register, 405 ...
Interleave register, 406 ... Access slot number, 407 ... Comparator, 408 ... Access start signal, 40
9 ... Slot number register, 501 ... Access actual slot number correspondence register, 601, 602 ... Comparator, 603
... AND circuit, 604 ... Encoder, 605 ... Half adder, 606, 607 ... Selector, 700 ... Transaction, 701 ... Transaction header, 702 ... Transaction body.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Naoki Hamanaka 1-280, Higashi Koigakubo, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Inventor Yoichi Tanaka 810 Shimoimaizumi, Ebina-shi, Kanagawa Hitachi, Ltd. Office Systems Division (72) Inventor Masafumi Shibata 810 Shimoimaizumi, Ebina, Kanagawa Prefecture Hitachi Systems Office Systems Division

Claims (6)

[Claims] 1. An interleave group consisting of a power of 2 of the memory blocks having the same storage capacity is generated from a plurality of memory blocks each having an arbitrary storage capacity as much as possible for each storage capacity, A memory interleaving method, characterized in that interleaving is performed for each of the interleaving groups. 2. A memory interleaving device for a storage device in which a plurality of memory blocks each having an arbitrary capacity coexist, wherein an address boundary register for specifying a boundary address of each memory block and the number of memory blocks in the interleave group. An interleave register that specifies the address boundary register and the interleave register, and referring to an access address issued by an access request source, the memory blocks having the same capacity are arranged in the same memory area, and To form one or more interleave groups to which each memory block is cyclically allocated in order,
A memory interleaving device, comprising: a memory block selecting unit that determines a memory block to be accessed. 3. The memory interleave apparatus according to claim 2, wherein the memory block selection means compares the value of a predetermined upper bit of the access address with the value of the address boundary register to determine the access target. An upper address comparator for determining a head memory block in the interleave group to which the memory block belongs, and an interleave group designated by the interleave register corresponding to the head memory block determined by the upper address comparator, Low order address bits corresponding to the logarithm of the number of memory blocks,
A lower address adder for adding the number of the first memory block determined by the upper address comparator, and to associate the output of the lower address adder with the memory block to be accessed one-to-one. A memory interleaver characterized by the above. 4. The memory interleave apparatus according to claim 2, wherein a plurality of the memory blocks are connected to the access request source via a common bus, and the access reception determination unit of each of the memory blocks includes the memory block. A memory interleaving device comprising an address boundary register, the interleave register, and the memory block selection means. 5. The memory interleave apparatus according to claim 2, wherein the plurality of memory blocks are connected to any of the access request sources via a connection switch, are provided at the access request sources, and access destinations are set. A memory interleaving device comprising the address boundary register, the interleave register, and the memory block selection unit in an access destination determination unit for determination. 6. The memory interleave device according to claim 2, 3, 4 or 5, wherein, at the time of initial setting, the address boundary register is temporarily set to have a maximum capacity and the interleave register is set to be not interleaved. After that, an attempt is made to access each of the memory blocks, an actual mounted capacity is determined depending on whether the access can be executed, and the memory blocks having the same capacity are bundled in units of powers of 2 based on the actual mounted capacity. The address boundary registers are set so that they are arranged in the interleave group that configures the same memory area, and a value corresponding to the number of memory blocks belonging to the same memory area is set in the interleave register. Memory interleave device.