JPH0917957A - Fusing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a fusing system which fuses all of desired fusing points selectively by reducing outside pins for fusing. SOLUTION: This fusing system is provided with an interface part 1 for interfacing the signals inputted from a power source and an outside pin, a logic part 2 for receiving the signal outputted from the interface part 1 and receiving information and sending the data to be fused, to a fusing circuit 3, and outputting the data not requiring fusing as it is, and a fusing circuit 3 for fusing the data that it has received from the logic part 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fusing system, and more specifically, in manufacturing an integrated circuit, fusing of fusible links is not performed on a wafer, but three pins are formed on a package. The present invention relates to a fusing system capable of selectively fusing all points to be fusing only.

[0002]

2. Description of the Related Art Generally, in an integrated circuit (IC) manufacturing process, even if the same integrated circuit is manufactured, the manufactured integrated circuits have various electric characteristics. This is because it is difficult to always maintain the same conditions because the manufacturing process of the integrated circuit is complicated due to the characteristics of the manufacturing process and it is completed in several steps.

Therefore, the final electrical characteristics of the manufactured integrated circuit have different characteristic distributions based on the center value of the design target. However, in products to which integrated circuits are applied, there are items that should be managed rather than minimizing the electrical characteristic distribution.

For example, in the NTSC system of the VHS standard of VTR, the FM carrier frequency for the sync chip of the video signal is clearly specified as 3.4 ± 0.1 MHz. Therefore, in order to produce a VTR that conforms to the above standards, the standards specified must be observed.

[0005]

However, there are cases where the integrated circuit target specifications are not met even if the integrated circuit design target is designed and manufactured accurately. Therefore, one of the methods used to solve such a problem is a method of adjusting electric characteristics of an integrated circuit using fusing. That is, the fusing technique is used as one of the methods for adjusting the electric value of the integrated circuit so as to reach the center value by adjusting the resistance value, the current value, and the voltage level. It

[0006] In fusing as required in the manufacture of an integrated circuit, conventionally, before assembling the integrated circuit, pads are set at both ends of a device to be fused on a wafer, and a voltage or a voltage is applied to both ends of the pad when necessary. A method of applying a current and fusing has been used.

However, there is a difference between the electrical characteristics of the integrated circuit that is fused in the wafer state and the electrical characteristics of the integrated circuit that is fused in the assembled package state. Because in the wafer state, ambient temperature, light,
This is because the electrical characteristics of the chip are easily affected by the power supply interconnection state. Therefore, in order to secure more accurate electric characteristics, it is necessary to realize fusing of a necessary portion in a packaged state.

However, on the wafer, it is possible to directly apply voltage or current to both ends of the fuse to be fused by the probing chip, but due to the limited number of pins on the package, the fuse at a desired location can be fused. There is a disadvantage that it is difficult to sing.

That is, the fusing in the package state can be easily realized by connecting the places to be fused with pins, but when there are many places to be fused, the number of pins increases and the package size increases. Proportionally increases,
As a result, the manufacturing cost increases, the size of the PCB (Printed Circuit Board) of the product to which the integrated circuit is applied increases, and the competitiveness of the integrated circuit having the same function decreases.

[0010]

SUMMARY OF THE INVENTION Therefore, the object of the present invention is to solve the disadvantages of the prior art, in which only three pins fuse desired dozens of points,
Provide a fusing system that reduces manufacturing costs.

According to the structure of the present invention to achieve the above object, an interface unit for interfacing signals input from a power source and an external pin, and a signal output from the interface unit to retrieve information, It comprises a logic unit for sending data to be fused to a fusing circuit and outputting data that does not require fusing as it is, and a fusing circuit for fusing the data received from the logic unit.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION A preferred embodiment in which the present invention can be carried out based on the above configuration will be described below with reference to the accompanying drawings. As shown in FIG. 1, the configuration of the fusing system based on the embodiment of the present invention has a set terminal (S) to which an external power source is input and a clock terminal (CK) to which a signal is input, The data terminal (D) becomes the input of the interface section (1), and the signal output from the interface section (1) is the logic section (2).
And the logic part (2) is connected to the fusing circuit.
It consists of a structure linked to (3).

As shown in FIG. 2, the detailed structure of the logic unit (2) is as follows: a data signal (D) and a clock (CK).
The first and second serial data blocks (1
(0, 20) is connected with an end mark decoding block (30) for decoding an end mark, and the serial data block (20) and the end mark decoding block (30) are connected to a serial / parallel converter (40). The output of the address decoding unit 50 is connected to the address decoding unit 50 and the latch unit 60.
The output of the first latch unit 60 and 70 is connected to the first and second latch units 60 and 70, and the output of the first latch unit 60 is connected to the selector 80.

As shown in FIG. 3, the structure of the serial data (D) includes fuse stop and actual data (A).
DJ1, ...., ADJn) and fuse start. The structure of one frame in FIG. 3 is composed of addresses, data and end marks as shown in FIG.

The operation of the fusing system according to the embodiment of the present invention having the above-described structure is as follows. The fusing system according to the embodiment of the present invention operates by being divided into an adjustment mode and a fusing mode depending on how the serial data is configured. First,
In the adjustment mode, it is checked which point in the integrated circuit to which this fusing system is applied, the fusing causes the electrical characteristics to be optimum.

As shown in FIG. 4, in the adjustment mode, if the number of bits forming the data is n, it has information of 2n, and after determining what the optimum information is at each address, the information is used as a header. It is used as data in the zing mode. Further, the serial data is shown in FIG. 3, but the data next to the fuse start signal goes to the fusing circuit (3), and the data next to the fuse start signal is immediately output.

If the serial data (D) as described above is applied together with the clock signal (CK) and the power source and applied to the logic unit (2) through the interface unit (1), it is based on the embodiment of the present invention. The operation of the fusing system begins. The serial data (D) is input to the first serial data block (10) through the data (D) terminal of FIG. 2 and continuously input to the second serial data block (20) next to it.

At this time, the first serial data block (10)
The end mark in the serial data (D) input to is input to the end mark decoding (30) to recognize that one frame has been input. That is, the end mark is located in the first serial data block (10) of FIG. 2, and the address and data are located in the second serial data block (20) next to it.

After the serial data (D) is input to the serial-parallel converter (40) and converted into parallel form,
It is input to the address decoding unit (50). The address decoding unit (50) recognizes the address portion of the parallel data, determines whether the mode is the adjustment mode or the fusing mode, and transmits the data portion to an address that matches the adjustment mode.

That is, in the adjustment mode, it is sent to the selector (80) through the first latch part (60), and in the fusing mode, it is sent through the first latch part (60) and the second latch part (70). Data (CADJ1 ~
CADJn) is transmitted. The data input to the fusing circuit (3) is fused with the optimum information and
Transmit the data (FADJ1 to FADJn) to the selector (80) in (2).

After fusing is completed, set (S
The ET) pin should be tied to ground and logic low so that the integrated circuit can be applied to electronic products for operation.

The fusing system as described above is used as a method for adjusting the integrated circuit, but if a certain point in the electrical characteristics of the integrated circuit is fusing before proceeding with the fusing, the integrated circuit is integrated. Even when applied to electronic products, the manufacturability of electronic products with excellent characteristics is measured without adjusting the electrical characteristics of the integrated circuit.

After that, the measured result is subjected to a step called fusing so that each integrated circuit is always maintained in optimum electric characteristics. As a result, electronic product manufacturing companies do not need to make any fine adjustments in the manufacture of electronic products, so it is possible to significantly reduce manufacturing costs and secure competitiveness due to improved productivity, and increase sales. .

[0024]

As described above, in the embodiment of the present invention, 3
Since it is possible to fuse dozens of desired points with only one pin, it is possible to provide a fusing system having the advantages of reducing manufacturing costs and improving productivity.

[Brief description of the drawings]

FIG. 1 is a block configuration diagram of a fusing system according to an embodiment of the present invention.

FIG. 2 is a detailed diagram of a logic unit of a fusing system according to an embodiment of the present invention.

FIG. 3 is a configuration diagram of serial data.

4 is a data configuration diagram of one frame unit of FIG. 3;

[Explanation of symbols]

 1: Interface part 2: Logic part 3: Fusing part 10, 20: 1st, 2nd serial data block 30: End mark decoding part 40: Serial parallel converter 50: Address decoding part 60, 70: 1st , Second latch 80: Selector

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H03K 19/00

Claims (5)

[Claims] 1. An interface unit for interfacing signals input from a power source and an external pin; a signal output from the interface unit to search for information; and data to be fused is sent to a fusing circuit, A fusing system comprising a logic unit for outputting data that does not require fusing as it is, and a fusing circuit for fusing the data received from the logic unit. 2. The fusing system according to claim 1, wherein the interface unit has three external pins, and a clock signal, data, and power are input to each of them. 3. The logic unit includes: a first serial data block to which an end mark and a clock signal in the serial data signal are input; a second serial data block to which an address and data in the serial data signal and the clock signal are input; A serial data block, an end mark decoding block for decoding the end mark stored in the first serial data block, a second serial data block and the second serial data block connected to the end mark decoding block. A serial-parallel converter that performs serial-parallel conversion of the address and data stored in a data block, first and second latch units that temporarily store the data, data from the first latch unit, and the fusing Stores data from the circuit And a selector for selectively outputting, and an address output from the serial-parallel converter is decoded according to the clock signal to determine whether the mode is the adjustment mode or the fusing mode. In the adjustment mode, the first latch unit Through the selector to the first latch unit and the second latch unit in the fusing mode.
The fusing system according to claim 1, further comprising an address decoding unit that transmits the data to the fusing circuit through a latch unit. 4. The fusing system of claim 3, wherein the serial data is configured to fuse multiple points at a desired location. 5. The serial data structure comprises a structure including a fuse stop, actual data (ADJ1, ..., ADJn), and a fuse start.
Or the fusing system described in 4.