JPH09172679A - Communication control system and coder used for it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a useful technology contributing especially to miniaturization and cost-down of a portable mobile equipment by using part of an encoder block in common. SOLUTION: A bit stream is generated by coding control data SCCH and communication data SACCH according to a communication format specified for each of physical channels for control and communication and the bit stream is sent/received between a base station and a mobile station. In this case, common coding sections 51-57, 70 are provided to code control data SCCH specific to the control physical channel and control data SACCH specific to the communication physical channel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a zone type digital mobile communication control system, and more particularly to a communication control system suitable for application to a portable small mobile device. Digital mobile phone services have various merits such as better communication quality than analog systems, easy encryption such as scrambling to ensure confidentiality, and high-speed transfer of binary data. We are gradually expanding the service area centering around, but in order to obtain more users, the key is to introduce the cheapest mobile device to the market.

[0002]

2. Description of the Related Art In zone type mobile communication, the area around a base station installed on the roof of a building (for example, radius Km)
Becomes one service area (called a cell). The base station is connected to the exchange through a line control station that controls several cells, and the exchange identifies the cell in which the mobile device called from the public line network or another mobile device is located, The mobile station is called through the base station of the cell, or the telephone of the public network called by the mobile station or another mobile station is called.

There is bidirectional communication between the base station and the mobile device. In general, the communication path from the base station to the mobile station is called "downlink", and the communication path from the mobile station to the base station is called "uplink", and one channel is formed by the uplink and the downlink. The channel is
It is divided into a "control physical channel" for exchanging various control information necessary for communication in advance or during communication, and a "communication physical channel" for transferring information such as communication contents.

FIG. 13 shows a function table of both channels. It should be noted that this function table is based on the RCR standard (standard for digital mobile communication systems established by the Radio System Development Center). In the figure, the control physical channel includes cell information (BCCH and SCCH) and mobile unit unique number information (PCH), and the communication physical channel includes voice information (TCH), radio wave quality, and the like. Control information (SACCH, RCH) and auxiliary information (FACCH) indicating that a cell boundary is approached. Note that U
PCH is a future extension.

Each of these functions is coded according to a signal format defined in advance for each of the up / down channels, and is transmitted / received between the base station and the mobile station. FIG. 14 shows a signal format based on the RCR standard. FIG. 14A is a physical channel format for uplink control, FIG. 14B is a physical channel format for downlink control, and FIG. 14C is a physical channel for uplink communication. Channel format, FIG. 3D is a physical channel format for downlink communication.

In each format, the first "R" is the ramp bit, the second "P" is the preamble bit,
"SW" in the center is a sync word for synchronization, "CC"
Is a color code for scrambling, the last "G" is a guard bit, "CAC" is SCCH and UPCH in FIG. 13, and "TCH (FACCH)" is TC in FIG.
H (FACCH) and “SACCH / RCH” are SACCH or RCH in FIG. The ramp bit to the guard bit is one transmission unit (unit), and each format is composed of a bit stream of 280 bits per unit.

FIGS. 15 to 19 are block diagrams of various channel encodes for generating a bit stream (hereinafter referred to as “encoded data”) according to the above format. FIG. 15 is a block diagram for generating “SCCH first unit encoded data (Q0 for convenience)”, and FIG.
Is a block for generating "SCCH second unit encoded data (Q1 for convenience)".
18 is a block for generating “CH encoded data (Q2 for convenience)”, FIG. 18 is a block for generating “RCH encoded data (Q3 for convenience)”, and FIG. 19 is “FACCH encoded data (Q4 for convenience)”. ) ”, And these five types of blocks are provided exclusively for each.

In FIG. 15, the first SCCH to be transmitted
Input unit data into the FIFO memory 1 and
After the output of 1 is converted into a serial string by the parallel-serial converter 2, this serial string and the CRC code string generated by the CRC encoder 3 are combined by the multiplexer 4 and returned to the parallel string again by the serial-parallel converter 5. Then, the 4-bit BCH code calculated by the BCH encoder 6 is written to the interleave buffer 7 of 14 rows × 13 columns in “column” units. Reading from the interleave buffer 7
It is a "line" unit. As a result, so-called interleaved conversion for improving noise resistance is performed. The read data is represented by "Q0". Q0 is "SCCH 1st
This is "unit encoded data", and this data is "CA" of the signal format of the first unit in FIG.
C ”. Here, "CAC" of the same format is 6
There are 6 bits and 116 bits. The total number of two bits is 182, which is equal to the size of the interleave buffer 7 (14 × 13).

The basic configuration of each block in FIGS. 16 to 19 is the same as that in FIG. That is, FIG.
FO11, parallel-serial converter 12, CRC encoder 13, multiplexer 14, serial-parallel converter 1
5, a BCH encoder 16, and an interleave buffer 17, and FIG. 17 includes a FIFO 21, a parallel / serial converter 22, a CRC encoder 23, a multiplexer 24, a serial / parallel converter 25, a BCH encoder 26, and an interleave buffer 27. FIG. 18 shows a FIFO 31,
Parallel-serial converter 32, CRC encoder 33, multiplexer 34, serial-parallel converter 35, BCH
An encoder 36 and an interleave buffer 37 are provided, and FIG.
9 is a FIFO 41, a parallel-serial converter 42, C
An RC encoder 43, a multiplexer 44, a serial / parallel converter 45, a BCH encoder 46, and an interleave buffer 47 are provided.

[0010]

However, in such a conventional technique, since a dedicated encoder block is provided for each of a plurality of physical channels for control and communication, an increase in circuit scale cannot be avoided. In particular, there are problems that not only the downsizing of portable mobile devices is hindered but also cost reduction cannot be achieved.

Therefore, an object of the present invention is to provide a useful technique which contributes to downsizing and cost reduction of a portable mobile device, in particular, by sharing a part of an encoder block.

[0012]

According to a first aspect of the present invention, there is provided a communication control system, wherein control data and communication data are coded in accordance with a communication format defined for each physical channel for control and communication to generate a bit stream, In a communication control method for transmitting and receiving the bit stream between a base station and a mobile station, a common coding unit for commonly coating control data specific to the control physical channel and control data specific to the communication physical channel is provided. It is characterized by

A communication control system according to a second aspect is the first aspect.
In the communication control method described, the common coding unit uses SCCH and SACCH of RCR standard as common coding data. The CRC encoder according to claim 3, wherein the shift register is composed of 1-bit latches of the same number as the target maximum degree, and a plurality of first exclusive-OR gates connected to the output of each of the 1-bit latches. A plurality of first selecting means for selecting either one input or output of each of the first exclusive OR gates and inputting it to the 1-bit latch of the next stage, the input terminal of the signal series and the 1-stage of the last stage. A second exclusive OR gate connected to the output of the bit latch, and a third exclusive OR gate connected to the input terminal of the signal series and the output of the 1-bit latch of any stage other than the final stage, Second selection means for selecting either the output of the first exclusive OR gate or the output of the third exclusive OR gate, the output of the second selection means, and each of the first exhausts Characterized by comprising a switch connected between the inclusive-OR gate the other input of the.

A BCH encoder according to a fourth aspect has a BCH code circuit having the same number of inputs as the maximum number of processing bits of a generator matrix, and the BCH code circuit inputs in response to a predetermined control signal. It is characterized by masking some of the. In the inventions described in claims 1 and 2, some constituent elements can be shared by the control data that do not coexist in the same burst, and in the inventions described in claims 3 and 4, a CRC encoder and a BC are provided.
The H encoder can also be used.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 4 are diagrams showing an embodiment of a communication control system according to the present invention. First, the configuration will be described.
In FIG. 1, 51 is a FIFO, 52 is a parallel-serial converter, 70 is a mask circuit, 53 is a CRC encoder, 5
4 is a multiplexer, these elements are SCCH
It is a component that is used for both data and SACCH data. Further, 61 is a FIFO, 62 is a parallel-serial converter,
72 is a mask circuit, 63 is a CRC encoder, and 64 is a multiplexer, and these elements are components dedicated to RCH data. Further, 71 is a multiplexer, 55
Is a serial-parallel converter, 56 is a BCH encoder, 57
Is an interleaved buffer and these elements are S
It is a constituent element shared by both CCH data (or SACCH data) and RCH data.

When the bit stream of the control physical channel is generated, the communication format of FIG. 14 (a) or 14 (c) is followed. S for the format for these controls
ACCH and RCH are not included. On the other hand, in the case of generating the bit stream of the communication physical channel, FIG.
According to the communication format of (b) or FIG. 14 (d). SCCH is not included in these communication formats.

The present embodiment has been devised by paying attention to the use rule of such control data, and by reducing the circuit scale by sharing some components with the control data that do not coexist in the same burst. Is to try. That is, according to the configuration of this embodiment (FIG. 1), SCCH and S
ACCH, FIFO51, parallel-serial converter 5
2, mask circuit 70, CRC encoder 53, multiplexer 54, serial-parallel converter 55, BCH encoder 5
6 and the interleave buffer 57 can be shared, and the serial / parallel converter 55, the BCH encoder 56, and the interleave buffer 57 can be shared by the SCCH or SACCH and the RCH. (Figs. 15 to 19)
Compared with the one that has,
A particularly advantageous effect that the cost can be reduced can be obtained.

Here, the FIFO 51, the parallel / serial converter 52, the mask circuit 70, the CRC encoder 53, the multiplexer 54, the serial / parallel converter 55, and the BCH.
The encoder 56 and the interleave buffer 57 are SCC
The “common coding unit” for H and SACCH, and the serial-parallel converter 55, the BCH encoder 56, and the interleave buffer 57 are “common coding unit” for SCCH or SACCH and RCH.

In this embodiment, as the FACCH encode block, a dedicated block similar to that of the conventional example shown in FIG. 19 is used. FIG. 2 is a conceptual configuration diagram of the BCH encoder 56 of this embodiment. The number of input bits of the BCH code differs depending on the channel. Therefore, in the configuration of FIG. 5, the circuit is configured according to the maximum number of bits of data, and "0" can be inserted in the upper bits for the data of less than the maximum number of bits. That is, in the example of FIG. 5, the input bits SPI0 to SPI17 correspond to the output bits D11 to D4, but the output bits D1 to D3 corresponding to the upper 3 bits SPI8 to SPI10.
As a result, "0" can be inserted according to the channel type. This allows SCCHs with different bit lengths
(Or SACCH) and RCH can also serve as the BCH encoder 56.

FIG. 3 is a conceptual diagram schematically showing the latch space of the interleave buffer 57 in this embodiment.
One square represents a 1-bit latch. The size of the interleave buffer 57 is (15 rows × 28 columns). This size is the largest interleaved input data,
That is, SACCH data (row size) and FACCH
Corresponds to the data (column size). The number of bits of interleaved data also differs depending on the channel. Therefore, the latch space is mapped according to the channel (see FIG. 3), and the write clock is controlled according to the channel so that the data is written only in the corresponding space. Note that, in FIG. 3, the relationship between the symbols a to i added to each square and the allocation data is as follows.

A: All channels b: SCCH second use c: SCCH first or SACCH d: SCCH first, SCCH second or SACCH e: SCCH first f: SCCH first or SCCH second g: For SACCH h: For SCCH 1st, SACCH or RCH i: For RCH or SACCH FIG. 4 is a timing chart of the encoding process for one unit. The signal TXSLOT is set to an appropriate period capable of counting the same number of clocks as the total number of bits (280 bits) of one transmission unit, and the start of this period,
That is, the start of the encoding process is synchronized with the change (the rising change in the figure) of the signal ENCSTR. Signal DTC
MP is a signal that becomes active when all the data to be transmitted is stored in the FIFO.

If the signal DTCMP is active when the signal ENCSTR changes, the encoding process is started. That is, taking the SCCH as an example, in FIG. 1, the SCCH or SACCH is sequentially taken out from the FIFO 51 one by one (one word, although not particularly limited) and converted into serial data by the parallel / serial converter 52. A CRC code string corresponding to the above is generated by the CRC encoder 53, and the multiplexer 54 combines the serial data and the CRC code string,
After being converted into parallel data by the serial / parallel converter 55, the BCH code corresponding to the parallel data is converted into BCH code.
Generated by the encoder 56, written into the interleave buffer 57 along with the parallel data in column units, and read out from the interleave buffer 57 in row units,
"SCCH first unit encoded data" indicated by Q0
The encoding process of generating is executed.

If the signal DTCMP is negative when the change in the signal ENCSTR is detected, the SCC
H does not perform encoding processing, but RCH and SACC
At H, the mask circuits 70 and 72 are activated to insert idle data (“0”). According to this, since the system control unit (generally a microcomputer) is not involved in the idle data generation process, it is possible to reduce the load on the system control unit and to reduce the number of steps of the system control program. . Note that R
In the case of CH, the idle data insertion mode and
It is preferable to be able to select the retransmission mode of the previously transmitted data. To this end, a retransmission RCH temporary unit buffer (FIFO) is separately prepared, transmission data is stored in this temporary buffer, and when the retransmission mode is selected, the data in the temporary buffer may be encoded.

In addition, in the case of SCCH, since signal transmission is carried out by a partial echo line control random access method, recycling (a process of retransmitting the previously transmitted data) may occur, but it is interleaved. The SCCH read path from the buffer 57 may be fed back to the last latch of the interleave buffer 57, and the data read from the interleave buffer 57 may be cyclically executed.
According to this, since the system control unit (generally a microcomputer) is not involved in the recycling process, it is possible to reduce the load on the system control unit and to reduce the number of steps of the system control program.

FIGS. 5 and 6 are block diagrams of the CRC encoder used in the above embodiment. Figure 5 shows 16-bit CRC
It corresponds to the generator polynomial, and is SCCH / SAC in FIG.
Used by the CRC encoder 53 for CH data. Also,
FIG. 6 corresponds to an 8-bit CRC generating polynomial, and is used in the CRC encoder 63 for RCH data in FIG.

Here, the binary sequence of length n is associated with the polynomial of degree n−1 or less in a one-to-one correspondence. With a linear code,
Assuming that the information point is k, 2 ^k sequences satisfying m = n−k parity check schemes derived from these k binary sequences are used. Since the total number of polynomials is 2 ⁿ , an error correction method that employs only those that can be divided by a specific m-th degree polynomial G (x) as a code word among these polynomials is CRC (cyclic redun).
dancy check), and G (x) is a generator polynomial (genera)
tor polynomial). The order of G (x) is m (= n−
In the case of k), any burst error with a length of m or less can be detected. For example, a 16-order generator polynomial shown in the following equation can be used to detect a burst error of 16 bits or less, and an 8-order generator polynomial shown in the following equation can be used to detect an 8-bit burst error or less.

[0027] In G (x) = 1 + X 5 + X 12 + X 16 ......... G (x) = 1 + X + X 3 + X 4 + X 7 + X 8 ......... FIGS. 5 and 6, S0 to S15 (except 6 S7
Up to) is a 1-bit latch that constitutes a shift register as a whole, plus (+) marks on the ellipse are exclusive OR gates, and SW1 and SW2 are switches.

Now, with SW1 closed and SW2 tilted down, k number of information points (a _n-1 , a _n-2 , ... A _{n-k + 1} ).
When is sent from the input end to the output end at the same time as it is also sent into the shift register, division is performed in the shift register, and x is included in the shift register at the end of sending a _{n-k + 1.} ^m (a _{n-k + 1} + a _{n-k + 2} x + ... a _n-2 x
^k-2 + a _n-1 x ^k-1 ) divided by G (x) leaves a remainder R (x), so SW1 is opened and SW2 is tilted upwards to the remainder R.
It suffices to send (x) to the output end.

By the way, in the above embodiment, since two types of CRC encoders 53 and 63 having different orders are required, a dedicated encoder as shown in FIGS. 5 and 6 is provided, but these are made common. If possible, it is very convenient because the configuration can be simplified and the cost can be reduced, and the power saving can be achieved. FIG. 7 is a block diagram of a novel CRC encoder devised based on such a problem. Note that, here, a configuration in which the 16th order and the 8th order can be commonly used is shown in consideration of application to the above-described embodiment, but it goes without saying that other orders other than the above can be easily configured based on the same idea. .

In FIG. 7, S0 to S15 are 1-bit latches that constitute the shift register 99 as a whole, and the number (bit number) thereof is the maximum order (here, 1).
6th order). Further, 106 to 113 are exclusive OR gates, and SW1 and SW2 are switches (however, the switches described in the gist of the invention are SW1). The insertion positions of these exclusive OR gates 106 to 113 into the shift register follow those of FIGS. 5 and 6.

The feature of FIG. 7 lies in that of FIG. 5 and FIG.
And a means (first selecting means) 100 to 104 for shorting the input and output of the exclusive OR gates (first exclusive OR gates) 106 to 110 in the shift register 99, and S
Means for selecting one of the output of the exclusive OR gate (third exclusive OR gate) 112 after 7 and the output of the exclusive OR gate (second exclusive OR gate) 113 after S15 (Second selection means) 105 is provided. These means 100-
105 is embodied by selectors in FIG. 7, and each selector operates in response to a common signal.
Only one selector 103 after 4 is the other selector 1
The operation is the reverse of that of 00, 101, 102, 104 and 105. SEL and SEL bar (inversion signal of SEL) are switching control signals therefor.

Now, if it is assumed that each of the selectors 100 to 105 selects the path on the upper side of the drawing when SEL = H level (SEL bar = L level), then at this time, 1 after S4 in the shift register. There are only exclusive OR gates, and the exclusive OR gate after S7 is not selected. Therefore, in this case, since the configuration is equivalent to that of FIG. 5, the CRC for 16 bits is used.
It will function as an encoder. On the other hand, SE
When L = L level (SEL bar = H level), there is one exclusive OR gate other than S4 after the exclusive OR gate in the shift register, and the exclusive OR gate after S7 exists. Crucial OR gate is selected. Therefore, in this case, since the configuration is equivalent to that in FIG. 6, it functions as a CRC encoder for 8 bits.

That is, according to the configuration of FIG. 7, two types of CRC encoders having different orders can be realized by one circuit, so that the configuration can be simplified and the cost can be reduced, and the power saving can be achieved. The unique effect of being able to do this is obtained. In the configuration of FIG. 7, the exclusive OR gate and the selector are provided at appropriate positions in the shift register, but the invention is not limited to this. For example, it may be placed in all positions. The selector of the relevant stage may be controlled so that the input / output of the exclusive OR gate of the unnecessary stage is always short-circuited.

FIG. 8 is a block diagram of the BCH encoder used in the above embodiment. FIG. 8A is for SCCH first unit encoded data, FIG. 8B is for SCCH second unit encoded data, FIG. 6C is for SACCH encoded data (and RCH encoded data). Note that the one shown in FIG.
Although the H-encoded data and the RCH-encoded data are provided separately, they are shown in the same drawing because they have the same bit size.

As can be seen from FIGS. 8A to 8C, all BCH encoders have the same number of bits (4 bits).
Although the BCH calculation is performed, the number of input bits varies from 10 bits to 8 bits to 11 bits. That is, for the SACCH and RCH, the BCH shown in FIG.
The generator matrix of (15, 11) is applied as is, but SC
1-bit shortened BCH for CH 1st unit
(14,10) is applied, and the SCCH second unit and subsequent units have a shorter 3-bit shortened BCH (12,8).
Apply

By the way, in the above embodiment, the BCH encoder for each channel is provided, but if these can be shared, the configuration can be simplified and the cost can be reduced, and the power saving can be achieved. , Very convenient. 10 and 11 are block diagrams of a novel BCH encoder devised based on such a problem. Here, in consideration of application to the above-mentioned embodiment, BCH (15,
11) A configuration that can be commonly used for the 1-bit shortened BCH (14, 10) and the 3-bit shortened BCH (12, 8) is shown. Needless to say, other configurations can be easily configured based on the same idea. Yes.

In FIG. 10, the point of the new BCH encoder is to have a BCH code circuit 200 having the same number of inputs as the maximum number of processing bits (11 bits in the figure) of the generator matrix, and this BCH code circuit 200 Is that some of the inputs can be masked (“0” is inserted) in response to a predetermined control signal (for convenience, BCH control signal). FIG.
FIG. 3 is a preferred configuration diagram of the BCH coding circuit 200. FIG.
1, D0 to D10 are 11-bit inputs, BCH
0 to BCH3 are 4-bit BCH output, SC1 and SC
2 is a 2-bit BCH control signal. A 4-bit BCH operation is performed by a logical operation unit 222 including a large number of exclusive OR gates 201 to 221.

Three 3-input AND gates 223 to 225
And an input gate unit 234 composed of eight 2-input AND gates 226 to 233, a BCH operation enable signal BC.
When HEN is active (H level), it is turned on to give D0 to D10 to the logical operation unit 222, and part of it masks the input in response to the BCH control signal. That is, SC1 of the BCH control signal
Is input to the 3-input AND gate 223 of D10 via the NOR gate 235, and SC of the control signal is input.
2 is 3 of D9 and D8 via the inverter gate 236.
The three-input AND gates 223 to 225 are input to the input AND gates 224 and 225, and fix their outputs to "0" when SC1 and SC2 are active (H level).

The BCH operation enable signal BCHE
N becomes active at a timing according to the number of bits of the target data. For example, in the case of the SCCH first unit (10 bits), as shown in FIG. 12, the timing at which bits 1 to 10 are aligned in the output (S / P) of the serial-parallel converter (10th clock in the figure). To activate.

In such a configuration, if only SC1 is activated, a 1-bit shortened BCH (14, 10) with D0 to D9 as an input can be realized.
By making both 1 and SC2 active, a 3-bit shortened BCH (12,8) with D0 to D7 as inputs can be realized, and by making SC1 and SC2 negative,
BCH (15,1) that inputs all of D0 to D10
1) can be realized.

Therefore, in one circuit, BCH (1
5, 11) Since it can be used for both 1-bit shortened BCH (14, 10) and 3-bit shortened BCH (12, 8),
It is possible to obtain a unique effect that the configuration can be simplified and the cost can be reduced, and the power saving can be achieved.

[0042]

According to the first to fourth aspects of the present invention, it is possible to obtain a unique effect that the prior art does not have, that is, the structure can be simplified, the cost can be reduced, and the power saving can be achieved. .

[Brief description of the drawings]

FIG. 1 is a conceptual configuration diagram of a main part of an embodiment.

FIG. 2 is a conceptual configuration diagram of a BCH encoder according to an embodiment.

FIG. 3 is a schematic diagram of a latch space of an interleave buffer according to an embodiment.

FIG. 4 is a timing chart of encoding processing according to an embodiment.

FIG. 5 is a conceptual configuration diagram of a CRC encoder (16th order) according to an embodiment.

FIG. 6 is a conceptual configuration diagram of a CRC encoder (8th order) according to an embodiment.

FIG. 7 is a conceptual configuration diagram of a dual-purpose CRC encoder according to an embodiment.

FIG. 8 is a conceptual diagram of a BCH encoder according to an embodiment.

FIG. 9 is a BCH generator matrix diagram of an embodiment.

FIG. 10 is a conceptual diagram of a dual-purpose BCH encoder according to an embodiment.

FIG. 11 is a specific configuration diagram of a dual-purpose BCH encoder according to an embodiment.

FIG. 12 is a timing chart of a BCH operation enable signal according to an embodiment.

FIG. 13 is a function allocation diagram of a physical channel according to the RCR standard.

FIG. 14 is a communication format diagram based on the RCR standard.

FIG. 15 is a conventional SCCH first unit encoding block diagram.

FIG. 16 is a conventional SCCH second unit encode block diagram.

FIG. 17 is a conventional SACCH encoding block diagram.

FIG. 18 is a conventional RCH encoding block diagram.

FIG. 19 is a conventional FACCH encoding block diagram.

[Explanation of symbols]

 51: FIFO (Common Coding Unit) 52: Parallel-Serial Converter (Common Coding Unit) 53: CRC Encoder (Common Coding Unit) 54: Multiplexer (Common Coding Unit) 55: Serial to Parallel Converter (Common Coding Unit) 56: BCH encoder (common coding unit) 57: interleave buffer (common coding unit) 70: mask circuit (common coding unit) S0 to S15: 1-bit latch SW1: switch 99: shift register 100 to 104: first selecting unit 105: Second selecting means 106 to 110: First exclusive OR gate 112: Third exclusive OR gate 113: Second exclusive OR gate 200: BCH coding circuit

Claims (4)

[Claims] 1. A control data or communication data is coded according to a communication format specified for each physical channel for control or communication to generate a bit stream, and the bit stream is transmitted and received between a base station and a mobile station. In the communication control method described above, a common coding unit is provided for commonly coating control data specific to the control physical channel and control data specific to the communication physical channel. 2. The communication control system according to claim 1, wherein the common coding unit uses SCCH and SACCH of RCR standard as common coding data. 3. A shift register composed of 1-bit latches of the same number as the maximum order of interest, a plurality of first exclusive-OR gates connected to the output of each 1-bit latch, and each of the first A plurality of first selecting means for selecting one input or output of one exclusive OR gate and inputting it to the 1-bit latch of the next stage, an input terminal of the signal series and an output of the 1-bit latch of the final stage A second exclusive OR gate connected to the second exclusive OR gate, a third exclusive OR gate connected to the input terminal of the signal sequence and the output of the 1-bit latch of any stage other than the final stage, and the first exclusive OR gate.
Second output for selecting either the output of the exclusive OR gate or the output of the third exclusive OR gate
A CRC encoder comprising: selecting means; and a switch connected between the output of the second selecting means and the other input of each of the first exclusive OR gates. 4. A BCH code circuit having as many inputs as the maximum number of processed bits of a generator matrix, and the BCH code circuit masks some of the inputs in response to a predetermined control signal. Characteristic BCH encoder.