JPH09172091A - Cmos semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a used capacitor irrespective of a P-type or N-type wafer substrate by a method wherein a capacitor is formed on an element forming area on one conductive and reverse conductive wells formed on a wafer substrate. SOLUTION: After a LOCOS oxide film 8 for element separation is formed on a substrate 1A, by use of the LOCOS oxide film 8 as a mask, the entire face of substrate is thermally oxidized to form a gate oxide film 9. Next, after a polysilicon film is formed on the entire face, it is patterned to form a gate electrode 10 on an element forming area. Then, it is possible to form P, N-type wells 2, 3 on the substrate 1A, an N channel type capacitor 4 on the P well 2, and a P channel type capacitor on the N well 3. When making mask design, it is possible to use the same capacitor irrespective of the P-type or N-type well substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for providing a capacitor that functions in a CMOS semiconductor device, particularly regardless of a P-type or N-type wafer substrate.

[0002]

2. Description of the Related Art Conventionally, a CMOS semiconductor device has a P-type semiconductor device depending on required circuit characteristics, device characteristics, and other purposes.
The type wafer substrate and the N type wafer substrate were used separately. Further, the capacitor is an indispensable device for inspecting the quality of the finished product and the process monitor of the gate oxide film formation and the gate oxide film process.

At present, it has been necessary to change the capacitor shape between the P-type wafer substrate and the N-type wafer substrate. Hereinafter, each capacitor shape of the P-type wafer substrate and the N-type wafer substrate will be described with reference to FIGS. 6 to 9. 6 and 7 are P-type wafer substrates, and FIG.
8A and 9B are N-type wafer substrates,
9 is a sectional view taken along line BB of FIG.

First, when a P-type wafer substrate 51 is used, a P-type well 52 and an N-type well 53 are formed on the substrate 51 as shown in FIGS. An N channel type capacitor 55 is formed on the N type well 53, and a P channel type capacitor 56 is formed on the N type well 53. Then, when the film quality of the gate oxide film is evaluated by a well-known method, on the N-channel capacitor 55 side, electric charge is discharged from the substrate surface through the P-type well 52 and the P-type substrate 51 to the substrate rear surface directly, and P On the channel type capacitor 56 side, charges are transferred from the substrate surface to the N type well 5.
3 through the N + type diffusion layer 58, the metal wiring 59, the P + type diffusion layer 60, and the P type substrate 51 to the back surface of the substrate. Reference numeral 62 is a P + type diffusion layer formed in the P type well 52. The diffusion layer 62 is
This is effective for fixing the potential of the P-type well 52.

Further, when the N-type wafer substrate 71 is used, a P-type well 72 and an N-type well 73 are formed on the substrate 71 as shown in FIGS. An N channel type capacitor 75 is formed on the N type well 73, and a P channel type capacitor 76 is formed on the N type well 73. Then, when the film quality of the gate oxide film is evaluated, on the N-channel capacitor 75 side, charges pass from the substrate surface through the P-type well 72 to the P + -type diffusion layer 78,
Metal wiring 79, N + type diffusion layer 80, and N type substrate 71
Through to the back surface of the substrate, and the P-channel capacitor side 7
6, the charge is transferred from the substrate surface to the N-type well 73, and N
It is formed so as to pass directly through the die substrate 71 to the back surface of the substrate. Reference numeral 82 is an N + type diffusion layer formed in the N type well 73. The diffusion layer 82 is effective for fixing the potential of the N-type well 73.

However, when designing a mask, it has been very troublesome to distinguish the wafer substrate into P type or N type and install the capacitors. Further, if the capacitor is used by mistake, it is inconvenient because it cannot be monitored and many masks have to be corrected.

[0007]

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a CMOS semiconductor device having a capacitor that can be used regardless of whether it is a P-type or N-type wafer substrate.

[0008]

SUMMARY OF THE INVENTION Therefore, according to the present invention, capacitors 4 and 5 are formed on an element formation region on a P-type well 2 and an N-type well 3 formed on a P-type or N-type wafer substrate. A P + type diffusion layer 12A formed so as to surround the peripheral portion of the P type well 2, and the P + type diffusion layer 1
2A, an N + type diffusion layer 13A formed outside the P type well 2, an N + type diffusion layer 13B formed so as to surround a peripheral portion of the N type well 3, and the N type diffusion layer 13B. +
The P + type diffusion layer 12B formed outside the N type well 3 so as to surround the type diffusion layer 13B and the P + type diffusion layers 12A and 12B and the N + type diffusion layers 13A and 13B adjacent to each other. And metal wiring 16 connected by.

Further, according to the present invention, capacitors 4 and 5 are formed on an element forming region on a P-type well 2 and an N-type well 3 formed adjacent to each other on a P-type or N-type wafer substrate, and The P + type diffusion layer 20 or the N + type diffusion layer 21 formed so as to surround the peripheral portion of the P type well 2 or the N type well 3, and the adjacent P + type diffusion layer 20 and N + type. The metal wiring 16 is connected so as to straddle the diffusion layer 21.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a CMOS semiconductor device of the present invention will be described with reference to the drawings of FIGS. 2 and 3 are sectional views taken along the line CC of FIG.
2 uses a P-type wafer substrate 1A, and FIG. 3 uses an N-type wafer substrate 1B. Hereinafter, for convenience, a CMOS semiconductor device formed on the P-type wafer substrate 1A will be described.

First, as shown in FIG. 2, 1A is a P-type wafer substrate, a P-type well 2 and an N-type well 3 are formed on the substrate 1A, and an N-channel type capacitor 4 is formed on the P-type well 2. A P-channel capacitor 5 is formed on the N-type well 3. That is, after the LOCOS oxide film 8 for element isolation is formed on the substrate 1A, the L
Using the OCOS oxide film 8 as a mask, the entire surface of the substrate is thermally oxidized to form a gate oxide film 9. Next, after a polysilicon film is formed on the entire surface, it is patterned by a known method to form the gate electrode 10 on the element formation region.

A P + type diffusion layer 12A is formed so as to surround the peripheral portion of the P type well 2, and an N + type diffusion layer is formed outside the P type well 2 so as to surround the P + type diffusion layer 12A. The layer 13A is formed. The diffusion layer 12A is made of P
This is effective for fixing the potential of the mold well 2. Similarly, an N + type diffusion layer 13B is formed so as to surround the peripheral portion of the N type well 3, and a P + type diffusion layer 12B is provided outside the N type well 3 so as to surround the N + type diffusion layer 13B. Are formed.
The diffusion layer 13B is effective for fixing the potential of the N-type well 3. Next, an interlayer insulating film 15 is formed on the entire surface (a part of the surface of the gate electrode 10 is exposed for a film quality evaluation inspection of a gate oxide film described later), and the interlayer insulating film 15 is formed.
The P + type diffusion layer 12A and the N + type diffusion layer 13 which are adjacent to each other
After a contact hole is formed on the A and N + type diffusion layer 13B and the P + type diffusion layer 12B, the P + type diffusion layer 12A and the N + type diffusion layers 13A and N + are formed through the contact hole.
A metal wiring 16 is formed to contact the type diffusion layer 13B and the P + type diffusion layer 12B. Similarly, a CMOS semiconductor device is also formed on the N-type well substrate 1B as shown in FIG.

Hereinafter, the CMOS thus formed will be described.
The film quality evaluation of the gate oxide film of the semiconductor device will be described. First, in the film quality evaluation of the gate oxide film of the CMOS semiconductor device using the P-type wafer substrate 1A as shown in FIG. 2, on the N-channel capacitor 4 side, the charge is from the substrate surface to the P-type well 2 and then to the P-type well. It passes through the substrate 1A and directly goes out to the back surface of the substrate, and on the P-channel capacitor 5 side,
The charges pass from the surface of the substrate through the N-type well 3, through the N + type diffusion layer 13B, the metal wiring 16, the P + type diffusion layer 12B, and the P type substrate 1A to the back side of the substrate (see the alternate long and short dash line in the drawing). ).

Further, as shown in FIG. 3, an N-type wafer substrate 1
In the film quality evaluation of the gate oxide film of the CMOS semiconductor device using B, on the P-channel capacitor 5 side, electric charge is discharged from the substrate surface through the N-type well 3 and the N-type substrate 1B to the back surface of the substrate directly. Channel type capacitor 4
On the side, the charge passes from the surface of the substrate through the P-type well 2 to P
+ Type diffusion layer 12A, metal wiring 16, N + type diffusion layer 13
It passes through A and the N-type substrate 1B and exits to the back surface of the substrate (see the alternate long and short dash line in the drawing).

As described above, in the present invention, by devising the design rule of the capacitor, it is possible to obtain a capacitor that functions in both P-type and N-type wafer substrates. Also, as shown in FIG. 4 and FIG.
The OS semiconductor device may be miniaturized.
Incidentally, FIG. 5 is a sectional view taken along the line D-D of FIG.

That is, as shown in FIG. 5, the P-type well 2 and the N-type well 3 are formed adjacent to each other on the P-type or N-type wafer substrate 1 to be miniaturized, and then the inside of the P-type well 2 is formed. A P + type diffusion layer 20 is formed in the peripheral portion, and an N + type diffusion layer 21 is formed in the peripheral portion in the N type well 3.

[0017]

As described above, according to the CMOS semiconductor device of the present invention, when designing a mask, the same capacitor can be used regardless of the P type or N type of the wafer substrate.
Workability is improved. Further, when the capacitor is selected incorrectly, the inconvenience that the conventional inspection cannot be performed and the mask has to be corrected is solved.

[Brief description of the drawings]

FIG. 1 is a plan view showing a CMOS semiconductor device of the present invention.

FIG. 2 is a sectional view taken along line CC of FIG.

FIG. 3 is a sectional view taken along line CC of FIG. 1;

FIG. 4 is a plan view showing another CMOS semiconductor device of the present invention.

FIG. 5 is a sectional view taken along the line DD of FIG. 4;

FIG. 6 is a plan view showing a conventional CMOS semiconductor device.

7 is a cross-sectional view taken along the line AA of FIG.

FIG. 8 is a plan view showing a conventional CMOS semiconductor device.

FIG. 9 is a sectional view taken along line BB of FIG. 8;

Claims (2)

[Claims] 1. A capacitor formed on an element formation region on a well of one conductivity type and an opposite conductivity type formed on a wafer substrate, and one formed so as to surround a peripheral portion in the well of one conductivity type. A conductive type diffusion layer, a reverse conductive type diffusion layer formed outside the one conductive type well so as to surround the one conductive type diffusion layer, and a peripheral portion inside the reverse conductive type well. An opposite conductivity type diffusion layer, a one conductivity type diffusion layer formed outside the opposite conductivity type well so as to surround the opposite conductivity type diffusion layer, the adjacent one conductivity type diffusion layer and the opposite conductivity type diffusion layer A CMOS semiconductor device, comprising: a metal wiring connected in such a manner as to straddle over. 2. A capacitor formed on an element forming region on a well of one conductivity type and a well of opposite conductivity formed adjacently on a wafer substrate, and a capacitor in the well of one conductivity type or in the well of opposite conductivity type. A diffusion layer of one conductivity type or a diffusion layer of opposite conductivity type formed so as to surround the peripheral portion, and a metal wiring connected so as to straddle the adjacent diffusion layer of one conductivity type and the diffusion layer of opposite conductivity type. A CMOS semiconductor device characterized by: