JPH09172028A - Manufacture of field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the source-parasitic resistance by forming a gate electrode self-matchedly with a gate opening. SOLUTION: A spacer film 102 and etching stopper film 103 are formed on a semiconductor substrate 101, an opening 102a of specified depth is formed and side wall film 104 is formed. Using the stopper film 103 as a mask, an anisotropic RIE is applied to transfer the shape of the film 104 to the side wall 102b of the spacer film 102 and form a gate opening 102c. A gate electrode material layer is formed and photoresist film 106 is formed flat on the entire surface. The film 106 is etched back to leave only the recessed part of the gate opening. Using the film 106 in the recess as a mask, etching is made to form a gate electrode 105, the film 102 is removed and ohmic metal layer 107 is deposited with the gate electrode used as a mask to form source and drain electrodes.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a method of manufacturing a field effect transistor, and more particularly to a method of manufacturing a MESFET (including a HEMT) having a T-shaped gate electrode structure.

[0002]

2. Description of the Related Art In order to improve the characteristics of a field effect transistor, it is important to reduce the resistance of a gate electrode and the parasitic resistance between a gate electrode, a source electrode and a drain electrode. It must be able to be manufactured. For this purpose, a technique has been proposed in which a so-called T-shaped gate electrode having a mushroom shape is used, and source and drain electrodes are formed in a self-aligned manner with the end of the eave of the gate electrode.

FIG. 11 is a sectional view showing a conventional method of manufacturing a field-effect transistor disclosed in Japanese Patent Application Laid-Open No. 5-326564 in the order of steps. First, as shown in FIG. 11A, a GaAs buffer layer 22, an n-GaAs layer 23a, and an n-AlGaAs are formed on a semi-insulating GaAs substrate 21.
An SiON (silicon oxynitride) film 26 is formed on a semiconductor substrate provided with a crystal structure of a layer 24a, an n-GaAs layer 23b, an n-AlGaAs layer 24b, and an n ⁺ -GaAs layer 25 by about 2 nm.
Deposit 000Å.

Next, as shown in FIG. 11B, a photoresist film 27a having an opening in the gate electrode region is provided to
iON film 26, n ⁺ -GaAs layer 25, n-AlG
The aAs layer 24b is sequentially removed by an anisotropic reactive ion etching (RIE) method. Next, FIG.
After removing the photoresist film 27a, as shown in FIG.
An SiO ₂ film is deposited at a thickness of about 4000 ° by a plasma CVD method, and anisotropically etched by an RIE method to a thickness of about 0.2 μm.
An SiO ₂ sidewall film 28 having a width is formed.

Here, the reticle-sized gate electrode region provided by the photoresist film is miniaturized by the SiO ₂ side wall film 28. Next, as shown in FIG. 11D, the n-GaAs layer 23b and the n-AlGaAs layer 2 are formed.
4a is etched. Next, as shown in FIG. 11E, a Ti / Pt / Au layer 2 for forming a gate electrode is formed.
9 is deposited. Next, as shown in FIG. 11F, a photoresist film 27b is provided, and the Ti / Pt / Au layer 29 is etched by an ion milling method to form a so-called T-type gate electrode having an eave.

Next, as shown in FIG.
AuGe / N serving as an ohmic electrode by removing the N film 26
By depositing the i / Au layer 30 using the gate electrode (29) as a mask, a source / drain electrode separated by the gate electrode is formed, and a field effect in which the source / drain electrode is formed in a self-aligned manner. A transistor can be obtained.

[0007]

However, in the above-mentioned conventional method for manufacturing a field effect transistor, FIG.
In the step of forming the side wall film shown in (c), in order to form the side wall film 28, SiO
_{The second} film 28 'is deposited. When the opening is deep, the deposited film has a width T above the opening as shown in FIG.
1, T2 below, and ΔT1 [= (T2−T1)
/ 2]. The degree of overhang protrusion becomes more pronounced as the depth of the opening increases. Therefore, the gate electrode formed by using this is shown in FIG.
As shown in (1), cracks and voids 31 are likely to occur, and the gate length is increased to T3.

Further, in the step of forming the SiO ₂ side wall film 28 by the etch back shown in FIG. 11C, since there is no end point mechanism of the etching, the controllability is poor. As shown in FIG. 13 (a), it decreases by ΔT2. And in FIG.
As shown in FIG. 2B, since the thickness of the SiON film 26 is reduced, AuGe / Ni / A serving as source / drain electrodes is used.
There is a problem that the short circuit of the u layer 30 with the gate electrode (29) or the close proximity of both electrodes deteriorates the FET characteristics.

In the above-described prior art, in the step of forming the gate opening, the n-A shown in FIG.
RIE for forming an opening up to the lGaAs layer 24b
Steps and RI for Processing the Sidewall Film shown in FIG.
The semiconductor substrate surface is exposed to a plasma atmosphere twice in the E step. For this reason, the crystal is easily damaged, and the FET characteristics may be degraded.

Further, since the photolithography technique is used for patterning the gate electrode, there is a possibility that the gate electrode may be displaced with respect to the gate opening due to the accuracy of figure alignment. That is, as shown in FIG.
The distance between the end of the gate region, which should be T6 and the Schottky junction with the n-AlGaAs layer 23a, and the end of the original gate electrode indicated by the dotted line is reduced to, for example, the distance T7,
The difference ΔT3 occurs. For this reason, the distance between the gate, the source and the drain fluctuates, which causes a problem that a stable source resistance cannot be obtained. When the deviation is further large, as shown in FIG. 14B, the ohmic metal layer (30) is not separated by the gate electrode (29), and the source / drain electrodes are short-circuited to the gate electrode. There was a point.

The present invention has been made in view of the above-mentioned problems of the conventional example, and has as its object the first object of the present invention is to provide a novel T-type gate electrode capable of preventing generation of voids and cracks. The second purpose is to provide a formation method, and the second purpose is to prevent deterioration of characteristics.
Another object is to make the gate electrode self-aligned with the gate opening.

[0012]

According to the present invention, there is provided a method for manufacturing a field effect transistor, comprising:
(1) A spacer film having a large film thickness and a stopper film that serves as an etching stopper when etching the spacer film are provided on a semiconductor substrate, and the spacer film is etched to a predetermined depth through the stopper film to form an opening. And (2) forming a sidewall on the side surface of the opening by depositing an insulating film or a metal film and etching back the same.
(3) A step of etching the spacer film by anisotropic etching using the stopper film as a mask and removing the sidewalls by etching to form a Y-shaped or T-shaped gate opening. And (4) a step of depositing a gate electrode forming material to a thickness that forms a recess in the gate opening and patterning the material to form a gate electrode, and (5) after removing the spacer film, It is characterized in that it has five steps of forming a source / drain electrode by depositing a material that makes ohmic contact with the semiconductor substrate using the gate electrode as a mask.

Preferably, in the step (4), a sub-step of forming a photoresist film having a flat surface, a sub-step of etching back the photoresist film to remove the photoresist film in the flat portion And a sub-step of etching the gate electrode forming material film using the photoresist film left in the recess as a mask.

[0014]

1 (a) to 1 (e) are cross-sectional views in the order of steps for explaining an embodiment of the present invention. In the first step of the method for manufacturing a field effect transistor according to the present invention, as shown in FIG. 1A, a spacer film 102 and an etching stopper film 103 serving as a stopper when the spacer film 102 is etched are formed on a semiconductor substrate 101. An opening 102a is deposited, penetrates through the etching stopper film 103, and reaches a predetermined depth of the spacer film 102.

The semiconductor substrate 102 is a conventional MESFET
With those having an active layer, such as n-GaAs the surface portion in case of forming a. In the case of forming a MESFET of recess structure is ⁿ - -GaAs on the layer n ⁺ -GaAs
One having a layer formed thereon is used. Further, when an FET having a heterojunction is formed, an i-GaAs layer, n
A semiconductor substrate having a laminated structure such as an -AlGaAs layer or an n ⁺ -GaAs layer is used. As the material of the spacer film 102, SiO ₂ , SiON, or Si ₃ N ₄ is used.
When these are used as the material of the spacer film 102, the material of the etching stopper film 103 is Al
Or an insulator such as SiO ₂ .

The depth of the opening 102a is desirably equal to or less than the length of the opening in order to prevent a remarkable overhang when forming a deposited film for forming the side wall film. More preferably, it is equal to or less than half the length of the opening. Photolithography technology and anisotropic RIE (reactive ion etching) are used to form the opening 102a.

In the second step, as shown in FIG.
A side wall film 104 is formed on the side surface of the opening 102a. As a material of the side wall film 104, an insulator such as SiO ₂ , SiON or a metal such as Al is used. After a deposited film is formed using these materials, the side wall film 104 is formed by etching back by RIE or the like.

In the third step, as shown in FIG. 1C, the spacer film 102 is etched by anisotropic etching using the etching stopper film 103 as a mask to form a gate opening 102c. At this time, the side wall film 1
When a material having a similar etching property to that of the spacer film 102 is used as the material 04, the sidewall film 104 is removed, and its shape is transferred to the spacer film 102 as the sidewall 102b. When a material that is hardly etched during the etching of the spacer film 102 is used as the material of the side wall film 104, a separate step of etching and removing the side wall film 104 after the etching of the spacer film 102 is required.

When the surface of the semiconductor substrate 101 is used as an active layer (channel layer), in the final stage of the etching of the spacer film 102, an etching means which has a small etching rate but is less likely to damage the crystal is used. It is desirable. Wet etching can be used for this purpose. Further, when it is necessary to separately etch the side wall film 104, the material of the side wall film may contaminate the substrate, or when the etching of the side wall film may seriously damage the crystal, the spacer film 10 may be used.
It is desirable to stop the etching of Step 2 except for the final part, and to etch the remaining part after removing the sidewall film.

According to the manufacturing method of the present invention, the side wall film 104 is formed.
In the step of forming the gate opening 102c and the step of forming the gate opening 102c, since the etching stopper film fulfills the stopper function, it is possible to prevent the film thickness of the underlying spacer film from being reduced, and it is possible to perform highly accurate processing. Then, the side wall film 1
Since the gap between layers 04 determines the gate length, a gate electrode having a gate length smaller than the size of the reticle can be formed. Further, according to the method for forming a gate opening of the present invention, the semiconductor substrate surface is not exposed to the plasma atmosphere a plurality of times, so that damage to the crystal can be minimized.

In a fourth step, as shown in FIG. 1D, a gate electrode 105 is formed by depositing and patterning a gate electrode forming material at least a lower layer of which is a material forming a Schottky junction with the semiconductor layer. . For this patterning, a normal photolithography technique can be used, but the gate electrode 105 can be aligned with the gate opening 102c using the following self-alignment technique. That is, after depositing a gate electrode forming material, a sub-step of forming a photoresist film 106 having a flat surface, a sub-step of etching back the photoresist film and removing the photoresist film in a flat portion, The sub-steps of etching the gate electrode forming material film using the photoresist film 106 as a mask are performed to form the gate electrode 105.

In the case of forming an FET having a recess structure, the semiconductor substrate 10 may be interposed between the third and fourth steps.
A step of etching the surface of the first substrate to form a recess structure is added.

In a fifth step, as shown in FIG. 1E, after removing the photoresist film 106 and at least the spacer film 102 on the source / drain electrode formation region,
An ohmic metal layer 107 that is in ohmic contact with the semiconductor substrate is formed using the gate electrode 105 as a mask to form source / drain electrodes self-aligned with the gate electrode. In the fourth step, the gate electrode is connected to the gate opening 10.
In the case where the gate electrode is formed by the self-alignment method, the variation in the distance between the end of the gate electrode and the source / drain region where the Schottky junction is formed with the semiconductor can be reduced. The parasitic resistance can be reduced, and the variation can be reduced.

[0024]

Next, embodiments of the present invention will be described with reference to the drawings. [First Embodiment] FIGS. 2 to 4 are process sectional views showing a first embodiment of the present invention. As shown in FIG. 2 (a), a non-doped GaAs layer 2, an n-AlGaAs layer 3, and an n ⁺ -GaAs layer 4 are epitaxially grown on a semi-insulating GaAs substrate 1.
To form Here, the non-doped GaAs layer 2 and the n-A
A two-dimensional electron gas is formed at the interface with the lGaAs layer 3. The n ⁺ -GaAs layer 4 becomes an ohmic contact layer.

The uppermost layer n of the epitaxial substrate 13
On the upper surface of the ⁺ -GaAs layer 4, SiO _{2 is used} as a spacer film.
The film 5a is 6000Å by chemical vapor deposition (CVD) method or the like.
Then, an Al film 6a serving as an etching stopper film is deposited to a thickness of 300 ° by an evaporation method or the like.
Further, a photoresist film 7a having a gate region length of 5000 ° is provided as a mask.

Next, as shown in FIG. 2B, the photoresist film 7a is used as a mask to perform a normal ion milling method using Ar gas or an anisotropic RIE method using CF ₄ gas. Opening 6aK penetrating Al film 6a
And an opening 5 reaching a depth of 2000 ° of the SiO ₂ film 5a.
to form aK '. Further, Al is removed by a wet etching method using phosphoric acid (H ₂ PO ₄ ), and SiO ₂ is removed by RI.
Etching may be performed by the E method.

Next, as shown in FIG. 2C, after removing the photoresist film 7a with a solvent, an SiO ₂ film 8a for forming a sidewall film is formed on the entire surface to a thickness of 200 by CVD.
Form 0Å. At this time, the SiO ₂ film 8a is
_The thickness of the film on the side of the opening of the Al film is 85
%, Grows to a thickness of 1700Å. That is, the grown film thickness on the side surface of the opening is smaller than that on the flat portion. This tendency becomes more remarkable as the depth of the opening increases. Therefore, when the depth of the opening is increased, when a film having a predetermined thickness is to be formed on the side surface of the opening, an overhang at the opening end becomes large. In other words, as the depth increases, the overhang ΔT1 shown in FIG. 12A increases, which causes a dimensional change in the gate length T3 as shown in FIG. 12B. Therefore, it is desirable that the overhang ΔT1 is as small as possible. Although the change of the deposited film is device-dependent and not constant, the change of 200
According to an apparatus capable of obtaining a film thickness of 85% at a depth of 0 °, the film thickness deposited at the opening depth of 5000 ° is 50% of the thickness deposited on the surface.

Next, as shown in FIG. 3 (a), the SiO ₂ film 8a is formed by Al anisotropic RIE using CF ₄ gas.
Etching is performed until the surface of the film 6a is exposed.
W is formed. Since the sidewall films 8aW are formed on the side surfaces of the opening of the SiO ₂ film 5a by 1700 °, the opening size is reduced to 1600 °. At this time, even if the etching time exceeds, the etching resistance of the Al film 6a is extremely large, so that the thickness of the SiO ₂ film 5a under the Al film 6a is not affected.

As shown in FIG. 3B, etching is performed by anisotropic RIE until the sidewall film 8aW disappears.
The shape of the side wall film 8aW is the side wall 5aW of the SiO ₂ film 5a.
Is transferred to Here, in the case where the side wall 5aW is formed and the surface of the n ⁺ -GaAs layer 4 is designed to be exposed at the same time, the etching is finished at this point. As shown in FIG. 3C, anisotropic RIE is further performed, and n ⁺ -GaAs
When the surface of the s layer 4 is exposed, the side wall 5aW of the SiO ₂ film 5a to which the side wall film 8aW has been transferred is formed at a deep portion of the opening. This RIE was performed at a CF ₄ gas flow rate of 100 sccm,
When the etching is performed under the conditions of gas pressure: 6.7 Pa and power: 250 W, the etching rate of SiO ₂ is 380 ° / min, whereas Al is hardly etched. SiO below
_{The second} film 5a is not etched, and its thickness does not change from the original 6000 °.

As described above, the gate length opening width is 16
00Å, gate eaves size 1700Å, the height of the lower part of the gate (dimension from the n ⁺ GaAs surface of the gate opening to the gate eaves) is 2000Å, the eaves height is 4000Å, and a symmetrical T-shaped gate opening 5aK is formed.

As shown in FIG. 4A, after dissolving and removing the Al film 6a with phosphoric acid, the exposed n ⁺ -GaAs layer 4 is
Etching is removed by the IE method so as to be side-etched by a predetermined size, and the entire surface including the gate opening 5aK is removed.
A WSi (tungsten-silicon alloy) film 9 is deposited as a Schottky metal to a thickness of 300 °, and an Au film 10 is deposited thereon as a low-resistance metal film to a thickness of 2000 ° by sputtering. Next, a resist film 7b is applied on the entire surface to fill the gate recess so that the surface becomes flat.

[0032] Next, as shown in FIG. 4 (b), by an etch-back method by conventional RIE using CF ₄ gas is performed, by etching from the surface of the photoresist film 7b, outside the gate region The surface of the Au film 10 is exposed. At this time, the photoresist is left only in the concave portion serving as the gate region. Next, using the resist film left in the gate recess as a mask by ion milling using Ar gas as a mask, the Au film 10 under the mask is left, and the other Au is removed.
The film is removed by etching, and then W
The Si film 9 is etched to form the gate electrode 11 under the mask.
To form At this time, the surface of the SiO ₂ film 5a is exposed.

Next, as shown in FIG. 4C, the SiO ₂ film 5a is masked with the gate electrode 11 by anisotropic RIE using CF ₄ gas with etching selectivity. The surface of the n ⁺ -GaAs layer 4 is exposed by etching so as to leave only the side wall 5aW immediately below the eaves. Next, the photoresist film 7b is removed, and an Au-Ge (gold-germanium) alloy film 12 of an ohmic metal is placed vertically above the semiconductor substrate at a height below the gate (= side wall 5).
aW height) or less, for example, a thickness of 1000 °. As a result, Au.Ge is formed on the gate electrode 11.
An alloy film 12 is deposited, and a source electrode and a drain electrode which are separated in a self-aligned manner by a gate electrode 11 are formed on both sides thereof.

The gate electrode structure of the field effect transistor obtained as described above has a WSi film 9
Electrode 11 made of Au film 10 having a thickness of 2000 .ANG.
An Au—Ge alloy film 12 having a thickness of 1000 Å is deposited thereon. The length T8 of the upper portion of the electrode is 5000 °, the length T9 of the lower portion is 1600 °, and the height H1 of the gate lower portion is H1.
2,000Ｔ, the height H2 of the gate upper part is 4000Å, and the length T10 of the eaves is (1700Å of the length of the gate upper part T8−the lower part length T9) 下部 2, which is obtained in a self-aligned manner. Can be Then, by forming source / drain electrodes using this gate electrode, the gate electrode is formed.
Source and drain electrodes having a source interval and a gate-drain interval of 1700 ° can be obtained in a self-aligned manner.

According to the present embodiment, the length T10 of the eaves of the gate electrode, that is, the distance between the gate and the source and the distance between the gate and the drain can be changed by the film thickness on the side surface of the side wall film 8aW. In addition, the height H1 below the gate electrode
Is SiO ₂ provided for providing the side wall film 8aW.
It is defined by the depth of the opening 5aK 'of the film 5a.

[Second Embodiment] Next, a second embodiment of the present invention will be described with reference to FIGS. In the first embodiment, the case where the etching rate of the side wall film 8aW is equal to that of the SiO ₂ film which is the insulating film on which the side wall film 8aW is formed, however, in this embodiment, the etching rate of the side wall film is lower. This is an example of a case where the etching rate is lower than the etching rate of the insulating film on which is formed. In the following description, steps that are the same as those in the first embodiment will not be repeated.

As shown in FIG. 5A, an SiON film 5b is formed as a spacer film on the upper surface of the n ⁺ -GaAs layer 4 which is the uppermost layer of the epitaxial substrate 13 by a CVD method to a thickness of 6 nm.
Then, an Al film 6a having a thickness of 300 .ANG. Serving as an etching stopper is deposited, and a photoresist film 7a having a gate region length of 5000 .ANG. Is provided as a mask. Next, as shown in FIG. 5B, an opening 6aK penetrating the Al film 6a is formed by a normal ion milling method using Ar gas or an RIE method using CF ₄ gas using the photoresist film 7a as a mask. Is formed, and an opening 5bK 'reaching the depth of 2000 ° of the SiON film 5b is formed.

Next, as shown in FIG. 5 (c), after removing the photoresist film 7a with a solvent, an SiO ₂ film 8a for forming a side wall film is formed on the entire surface by 2,000 .ANG.
To a film thickness of At this time, the SiO ₂ film 8a is
The 85% of the surface of the Al film 6a is 1% on the side surface of the opening of the N film 5b.
It is formed to a thickness of 700 mm.

Next, as shown in FIG. 6A, the SiO ₂ film 8a is formed by anisotropic RIE using CF ₄ gas.
Etching is performed until the surface of the film 6a is exposed.
W is formed. The sidewall film 8aW of SiO ₂ is made of SiON
1700 ° is formed on each side surface of the opening of the film 5b, and the opening size is reduced to 1600 °. At this time, even if the etching time is exceeded, the etching resistance of the Al film 6a serving as an etching stopper film is extremely large.
The thickness of the SiON film 5b under the 1 film 6a is not affected.

Subsequently, as shown in FIG. 6B, etching is performed by anisotropic RIE until the sidewall film 8aW disappears. At this time, the gas pressure was 8 Pa and the gas flow rate was 1
Under the conditions of 00 sccm and power of 250 W, S
The etching rate of iO ₂ is 380 ° / min, SiO 2
N = 800Å / min, SiON
Is twice as fast as SiO ₂ . Therefore,
The etching depth of the side wall 5bW transferred to the SiON film 5b reaches more than twice. That is, the height 2 of the side wall film 8aW
The height (etching depth) of the side wall 5bW formed on the SiON film 5b by this transfer is 40
It is slightly over 00Å. Therefore, when the sidewall film 8aW disappears by etching, n ⁺ -G is formed at the bottom of the gate opening 5bK.
The surface of the aAs layer 4 is exposed.

As described above, the gate length opening is 160
0 mm, gate eave size is 1700 mm, gate lower height is 4000 mm, gate upper height is 2000 mm
Thus, a symmetrical T-shaped gate opening 5bK is formed.

As in the first embodiment, as shown in FIG. 7A, the Al film 6a is dissolved and removed with phosphoric acid, and then the exposed n ⁺ -GaAs layer 4 is removed by etching. A 300 .ANG. WSi film 9 and a 2000 .ANG. Au film 10 are deposited on the entire surface including the gate opening 5bK by sputtering, and a photoresist film 7b is further applied on the entire surface to flatten the surface of the concave portion of the gate. To fill.

Then, as shown in FIG. 7B, first, the photoresist film 7b is etched back from the surface by a commonly used RIE method, and the etch back is stopped when the surface of the Au film 10 is exposed. Then, the photoresist film is left only in the gate recess. Next, using the photoresist film remaining in the gate recess as a mask, the Au film 10 and the WSi film 9 are etched to form a gate electrode 11 under the mask. By this etching, the SiON film 5 is formed.
The surface of b is exposed.

Next, as shown in FIG. 7C, the SiON film 5b is etched by using the gate electrode 11 as a mask by an anisotropic RIE method using CF ₄ gas to directly below the eaves of the gate electrode 11. Side wall 5bW of n ⁺ -GaA
The surface of the s layer 4 is exposed. Next, the photoresist film 7
b is removed, and an Au.Ge alloy film 12, which is an ohmic metal, is vertically deposited from above the gate electrode to a film thickness equal to or smaller than the height of the lower portion of the gate, for example, 1000 Å. Au
The Ge alloy film 12 is deposited on the gate electrode 11, and the separated source / drain electrodes are formed so as to be self-aligned with the gate electrode.

In the field effect transistor obtained as described above, the length of the upper portion of the electrode is 5000 °, the length of the lower portion is 1600 °, and the height H1 of the lower portion of the gate is 4000 °.
{Circle around (2)}, a T-shaped gate electrode having a height H2 of 2000 mm above the gate and a length of the eaves of 1700 ° is obtained in a self-aligned manner. By using the gate electrode of this embodiment, source and drain electrodes having a gate-source distance and a gate-drain distance of 1700 ° can be obtained in a self-aligned manner.

According to the present embodiment, the length of the eaves of the gate electrode, that is, the distance between the gate and the source and the distance between the gate and the drain are reduced by making the etching rate of the side wall film different from that of the insulating film formed thereon. As in the first embodiment, the height of the lower part of the gate can be changed to a high value. Also,
It is possible to reduce the inclination angle θ from the lower part of the gate to the upper part (eave) of the gate.

[Third Embodiment] Next, a third embodiment of the present invention will be described with reference to FIG. In the second embodiment, the case where the etching rate of the insulating film on which the sidewall film is formed is higher than that of the sidewall film has been described. Is slower than that of the side wall film. In the following description, the description of the steps overlapping with those of the first and second embodiments will be appropriately omitted.

As shown in FIG. 8A, on the upper surface of the n ⁺ -GaAs layer 4 which is the uppermost layer of the epitaxial substrate 13,
The SiO ₂ film 5a is grown to a thickness of 6000Å by the CVD method, and then the Al film 6a is deposited to a thickness of 300Å,
Further, a photoresist film having a gate region length of 5000 ° is provided as a mask. Using this as a mask, the Al film 6a is etched to form a through hole, and the SiO ₂ film 5a is etched to a depth of 4000 °. Next, SiON is deposited, and this is etched back by RIE to form a sidewall film 8bW.

As shown in FIG. 8B, RIE is further continued using the Al film 6a as a mask, and the sidewall film 8bW and the SiO ₂ film 5a are etched. As shown in FIG. 8C, when the sidewall film 8bW is completely removed by etching.
At the same time, a gate opening 5aK exposing the surface of the n ⁺ -GaAs layer 4 is formed, and a SiO ₂ film 5a is formed at the bottom of the opening.
Sidewall 5aW is formed. The T-type gate opening 5aK obtained in this manner is used for forming the Si film on which the sidewall film is formed.
Since the etching rate of the O ₂ film 5a is の of the etching rate of the side wall film 8bW, the height of the gate upper part is 400
0 °, the height of the lower gate is 2000 °, and the inclination angle θ at the boundary between the lower gate and the upper gate can be increased.

[Fourth Embodiment] Next, a fourth embodiment of the present invention will be described.
The embodiment is described with reference to FIG.
explain. In the following description, the same as the previous embodiments
The description of the steps to be performed is appropriately omitted. FIG. 9 (a)
Is the uppermost layer of the epitaxial substrate 13 as shown in FIG.
n⁺ -Si on the upper surface of the GaAs layer 4_Three N_Four Film 5a is CV
D method, and Si_Three N _Four When etching
SiO as stopper_Two The film 6b is formed by the CVD method
And then SiO_Two Penetrating through the film 6b,_Three N_Four Membrane 5c
After forming an opening reaching a predetermined depth of
The sidewall film 8cW is formed by the product and the etch back.
Next, using the side wall film 8cW as a mask, Si_Three N_Four Membrane 5c
A predetermined position where the surface of the epitaxial substrate 13 is not exposed.
Etching is performed by RIE method having anisotropy. This
Here, the side wall film 8cW is formed of CF_Four RIE using gas
Since it is hardly etched, it is left as it is.

Next, as shown in FIG. 9B, the side wall film 8 is formed.
cW is removed by etching to form a T-shaped pseudo gate opening 5c.
K ". Next, as shown in FIG.
Si left in gate opening 5cK ″ _Three N_Four Membrane 5c
Etching by RIE method
Is exposed to form a T-type gate opening 5cK.
You. According to the method of this embodiment, the removal of the sidewall film
The substrate 13 is contaminated or etched
Even if it is performed by the processing method,_Three N_Four Membrane 5c
The epitaxial substrate 13 is protected by
Does not hurt. The sidewall film is etched by RIE
The gate lower dimension is smaller and the gate upper dimension
There is an advantage that adjustment to enlarge the law can be performed.

[Fifth Embodiment] Next, a fifth embodiment of the present invention will be described with reference to FIG. As shown in FIG. 10A, an SiO ₂ film 5a is provided on the upper surface of the n ⁺ -GaAs layer 4 which is the uppermost layer of the epitaxial substrate 13 by the CVD method, and A
1 film 6a, further penetrates the Al film 6a,
₂ After forming an opening reaching a predetermined depth of the film 5a,
The sidewall film 8cW is formed by depositing the l film and etching it back. Next, using the side wall film 8cW as a mask, SiO ₂
The film 5a is etched by RIE to a predetermined depth that does not expose the surface of the epitaxial substrate 13. here,
The side wall film 8cW is hardly etched by RIE using CF ₄ gas, and thus is left as it is.

Next, as shown in FIG. 10B, the sidewall film 8cW and the Al film 6a are removed by etching to form a T-shaped pseudo gate opening 5aK ″.
As shown in (c), the entire surface of the SiO ₂ film 5a is etched by the RIE method to remove the SiO ₂ film remaining in the pseudo gate opening 5aK ″, and the epitaxial substrate 13 is removed.
Is exposed to form a T-type gate opening 5aK. According to the method of the present embodiment, the gate lower dimension can be adjusted to be small while the gate upper dimension is kept constant.

[0054]

As described above, according to the present invention, a spacer film and an etching stopper film are formed on a semiconductor substrate, an opening having a predetermined depth is formed, and then a side wall film is formed on a side surface of the opening. Since the gate opening is formed by etching the spacer film, according to the present invention, the deposited film for forming the side wall film can be prevented from overhanging on the opening. Thus, according to the present invention,
Cracks and voids can be prevented from occurring in the gate electrode, and the accuracy can be improved.
In addition, since the spacer film can be prevented from being reduced by the etching stopper film, the gate electrode and the source electrode can be prevented.
Contact and short circuit with the drain electrode can be prevented.
Furthermore, since the gate electrode is formed so as to be self-aligned with the gate opening, the contact between the gate electrode and the source / drain can be reduced.
In addition to preventing the short circuit, the variation in the distance between the gate electrode end and the source / drain electrode can be reduced, the source parasitic resistance can be reduced, and the variation can be reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view in a process order for describing an embodiment of the present invention.

FIG. 2 is a part of a process order cross-sectional view for explaining the first embodiment of the present invention.

FIG. 3 is a part of a process order cross-sectional view in a step that follows the step of FIG. 2 for explaining the first embodiment of the present invention;

FIG. 4 is a sectional view illustrating a first embodiment of the present invention in the order of steps following the step of FIG. 3;

FIG. 5 is a part of a process order sectional view for explaining a second embodiment of the present invention.

FIG. 6 is a part of a process order sectional view in a step that follows the step of FIG. 5 for explaining a second embodiment of the present invention.

FIG. 7 is a step-by-step sectional view in a step that follows the step of FIG. 6 for explaining the second embodiment of the present invention.

FIG. 8 is a process order sectional view for explaining a third example of the present invention.

FIG. 9 is a process order sectional view for explaining a fourth embodiment of the present invention.

FIG. 10 is a sectional view illustrating a fifth embodiment of the present invention in order of process.

FIG. 11 is a sectional view of a conventional example in the order of steps.

FIG. 12 is a sectional view for explaining a problem of the conventional example.

FIG. 13 is a sectional view for explaining a problem of the conventional example.

FIG. 14 is a sectional view for explaining a problem of the conventional example.

[Explanation of symbols]

Reference Signs List 1 semi-insulating GaAs substrate 2 non-doped GaAs layer 3 n-AlGaAs layer 4 n ⁺ -GaAs layer 5a SiO ₂ film 5aK, 5bK, 5cK gate opening 5aK ', 5bK' opening 5aK ", 5cK" pseudo gate opening 5aW, 5bW side wall 5b SiON film 5c Si ₃ N ₄ film 6a Al film 6aK Opening 6b SiO ₂ film 7a, 7b Photoresist film 8a SiO ₂ film 8aW, 8bW, 8cW Side wall film 9 WSi film 10 Au film 11 Gate electrode 12 Au / Ge alloy film 13 epitaxial substrate 21 a semi-insulating GaAs substrate 22 GaAs buffer layer 23 n-GaAs layer 24 n-AlGaAs layer 25 n ⁺ -GaAs layer 26 SiON film 27a, 27b photoresist film 28 SiO ₂ side wall film 28 'SiO ₂ film 29 Ti / Pt / Au layer 30 AuGe Ni / Au layer 31 void 101 semiconductor substrate 102 spacer film 102a opening 102b side walls 102c gate opening 103 etching stopper film 104 sidewall film 105 gate electrode 106 photoresist film 107 ohmic metal layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/778

Claims (6)

[Claims] (1) A spacer film having a large film thickness and a stopper film serving as an etching stopper at the time of etching the spacer film are provided on a semiconductor substrate, and the spacer film is etched to a predetermined depth through the stopper film. And (2) depositing an insulating film or a metal film and etching back the sidewall to form a side wall on the side surface of the opening, and (3) anisotropically etching using the stopper film as a mask. The spacer film is etched by the above method, and when the side wall remains, it is removed by etching to form a Y-shaped or T-shaped gate opening. (4) A recess is formed in the gate opening. A step of depositing a gate electrode forming material to a film thickness to be formed and patterning this to form a gate electrode, (5) after removing the spacer film, Method of manufacturing a field effect transistor having a step of forming a source and drain electrode by depositing a material which is in ohmic contact with the gate electrode as a mask to the conductor substrate. 2. The method according to claim 1, wherein in the step (3), a gate opening is formed by two-stage etching of anisotropic etching that leaves a part of the spacer film and etching that removes the remaining portion. The method for manufacturing a field-effect transistor according to claim 1. 3. The spacer film is SiO_Two Membrane, SiON
Membrane or Si_Three N_FourDepending on the film, the stopper film is an Al film
Or SiO_Two Due to the film, the side wall is made of SiO 2. _Two , SiO
It is formed of N or Al.
1. The method for manufacturing the field effect transistor according to 1. 4. A sub-step of forming a photoresist film having a flat surface by patterning in the (4) step, and a sub-step of etching back the photoresist film to remove the photoresist film in a flat portion. 2. The method for manufacturing a field effect transistor according to claim 1, further comprising a sub-step of etching the gate electrode forming material film using the photoresist film remaining in the concave portion as a mask. 5. The semiconductor substrate includes a channel layer, an electron supply layer, and a contact layer, which are stacked in order from the lower layer, and is provided between the step (3) and the step (4). 2. The field effect transistor according to claim 1, further comprising a step of etching the contact layer to a predetermined depth by using the spacer film as a mask and the electron supply layer as an etching stopper. Method. 6. The method for manufacturing a field effect transistor according to claim 1, wherein, in the step (1), the length of the opening formed in the spacer film is larger than the depth of the opening.