JPH0917184A - Semiconductor storage - Google Patents

Abstract

PURPOSE: To reduce the power consumption of a semiconductor storage by arranging n pieces of memory cells in series between first second power supplies and reducing power consumption per memory cell. CONSTITUTION: Memory cells MC12 and MC22 consist of two transfer gates consisting of Depletion type FET and Enhanced type FET, respectively. In this state, signals L and H (or H and L) are fed to bit wires BL12 and BL22 and inversion bit wires/BL12 and /BL22. Then current flows between a power supply V1 and a voltage wiring N1 or between a voltage wiring N1 and a power supply V2 via both or either of the memory cells MC12 and MC22. Therefore, a voltage applied to the MC12 and MC22 is half the voltage between the power supplied V1-V2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device using an SRAM, and more particularly to a semiconductor memory device in which a plurality of memory cells are serially incorporated between two power supplies to reduce power consumption. It is about.

[0002]

2. Description of the Related Art FIG. 6 (a) is a block diagram of a semiconductor memory device using a conventional SRAM, and FIG. 6 (b) is an example of a circuit diagram of an SRAM composed of field effect transistors. , Tr1 and Tr2 are depletion type FETs
(DFET), Tr3, Tr4, Tr5, Tr6 are enhancement type FETs (EFET), BL is a bit line, / BL is an inverted bit line, WL is a word line, V1 is a power supply for generating a reference voltage, and V2 is a negative voltage. It is a power source that is generated.

Such an SRAM has a transistor Tr1.
And Tr3, an inverter INV1 and an inverter INV2, which includes transistors Tr2 and Tr4, and a latch circuit, and a bit line pair BL,
Transfer gate Tr for connecting / BL respectively
5 and Tr6.

Next, the operation of the SRAM will be described by taking the case of writing "L" data as an example. Bit line pair BL, / B
When "L" and "H" signals are applied to L and "H" signal is applied to the word line WL, transistors Tr5 and T5 are applied.
Since r6 becomes conductive, the node N11 becomes "L" and the node N12 becomes "H". After that, when the word line WL becomes "L", the transistors Tr5 and Tr6 become non-conductive and become "L".
The data is held in the latch circuit. "L" in the latch circuit
The principle of data retention is as follows. That is, when the "L" signal of the node N11 is input to the input I2 of the inverter INV2, the transistor Tr4 becomes non-conductive and the output O2 of the inverter INV2 (the same potential as the node N12) becomes "H". Since the output O2 of the inverter INV2 is input to the input I1 of the inverter INV1, the transistor Tr3 becomes conductive, a current flows between the power sources V1 and V2 via the transistors Tr1 and Tr3, and the output O1 of the inverter INV1 ( The same potential as the node N11) becomes "L".

[0005]

The conventional semiconductor memory device using the SRAM is configured as described above, and only one memory cell is incorporated in series between the two power supplies. If the power supply voltage is fixed due to the relationship with the peripheral circuits, a voltage higher than the voltage required to operate it will be applied to the memory cells, and the power consumption of the semiconductor memory device will increase more than necessary. There was a problem that it would end up.

The present invention has been made in order to solve the above problems, and a semiconductor memory capable of reducing the running cost by suppressing the power consumption of each memory cell constituting the semiconductor memory device. The purpose is to provide a device.

[0007]

A semiconductor memory device according to the present invention (claim 1) is a semiconductor memory device having a memory cell array formed of an SRAM, wherein the memory cell array is a first power source. Between the first power supply and the second power supply, n × m (m and n are integers of 2 or more) memory cells are arranged in an array in n stages between the second power supply and the second power supply. And n memory cells are connected in series with each other.

A semiconductor memory device according to the present invention (claim 2) is the semiconductor memory device according to claim 1, wherein the n × m memory cells are connected to different bit line pairs. Is.

A semiconductor memory device according to the present invention (claim 3) is the semiconductor memory device according to claim 1, wherein the first power supply and the second power supply are included in the n × m memory cells.
The n memory cells connected in series with the power supply of 1 are connected to a common bit line pair.

A semiconductor memory device according to the present invention (claim 4) is the semiconductor memory device according to claim 1, wherein the memory cell array has m memory cells in each of the n stages. Each of them is composed of n sub-arrays arranged in an array in a plurality of memory areas.

A semiconductor memory device according to the present invention (claim 5) is the semiconductor memory device according to claim 4, wherein m memory cells forming the sub-array are connected to different bit line pairs. There is something.

A semiconductor memory device according to the present invention (claim 6) is the semiconductor memory device according to claim 4, wherein among the m memory cells forming the sub-array, a straight line in a direction perpendicular to the word line is formed. The memory cells arranged in 1 are connected to a common bit line pair.

A semiconductor memory device according to the present invention (claim 7) is the semiconductor memory device according to claim 1, wherein the memory cell array is for one stage of the n stages (1 is 2 or more and n or less). (Integer of) memory cells of a memory array between power supplies are arranged on a straight line perpendicular to the bit line.

A semiconductor memory device according to the present invention (claim 8) is the semiconductor memory device according to claim 7, wherein each of the memory cells is connected to a different bit line pair.

A semiconductor memory device according to the present invention (claim 9) is the semiconductor memory device according to claim 7, wherein the memory cells among the memory cells are arranged linearly in a direction perpendicular to the word line. The cells are connected to a common bit line pair.

[0016]

In the semiconductor memory device according to the present invention (claim 1), the semiconductor memory device has a memory cell array formed of SRAM, and the memory cell array includes a first power supply and a second power supply. N × m (m, n is an integer of 2 or more) of the above memory cells are arranged in an array in n stages, and n number of the above memory cells are provided between the first power supply and the second power supply. Since the memory cells are connected in series with each other, the power consumption of each memory cell can be reduced.

Further, in the semiconductor memory device according to the present invention (claim 2), in the semiconductor memory device according to claim 1, the n × m memory cells are connected to different bit line pairs. Since this is the case, all memory cells can be accessed at the same time.

Further, in the semiconductor memory device according to the present invention (claim 3), in the semiconductor memory device according to claim 1, a first power source and a second power source out of the n × m memory cells are provided. Since the n memory cells connected in series with each other are connected to the common bit line pair, the number of bit lines can be reduced.

Further, in the semiconductor memory device according to the present invention (claim 4), in the semiconductor memory device according to claim 1, the memory cell array includes m memory cells in each of the n stages. Since each sub-array has n sub-arrays arranged in a plurality of memory areas in an array, it is possible to apply a memory cell array having a conventional memory arrangement as a sub-array.

Further, in the semiconductor memory device according to the present invention (claim 5), in the semiconductor memory device according to claim 4, m memory cells forming the sub-array are connected to different bit line pairs. Since it is assumed that all memory cells can be accessed at the same time.

Further, in the semiconductor memory device according to the present invention (claim 6), in the semiconductor memory device according to claim 4, among the m memory cells forming the sub-array, a straight line in a direction perpendicular to the word line. Since the memory cells arranged above are connected to a common bit line pair, the number of bit lines can be reduced.

Further, in the semiconductor memory device according to the present invention (claim 7), in the semiconductor memory device according to claim 1, the memory cell array corresponds to one of the n stages (1 is 2 or more and n or more). Since the memory cells of the memory array between power supplies of (the following integers) are arranged on a straight line in a direction perpendicular to the bit lines, the area of the memory cell array can be reduced.

Further, in the semiconductor memory device according to the present invention (claim 8), in the semiconductor memory device according to claim 7, the memory cells are connected to different bit line pairs. , All memory cells can be accessed simultaneously.

Further, in the semiconductor memory device according to the present invention (claim 9), in the semiconductor memory device according to claim 7, the memory cells are arranged linearly in a direction perpendicular to the word line. Since the memory cells are connected to the common bit line pair, the number of bit lines can be reduced.

[0025]

【Example】

Embodiment 1 FIG. FIG. 1 (a) is a schematic diagram of a semiconductor memory device according to the first embodiment of the present invention, and FIG. 1 (b) is a schematic view of A in FIG. 1 (a).
The detailed figure of a part is shown. The semiconductor memory device of the first embodiment is
Memory cell array 100 and first sense amplifier 110
, The second sense amplifier 120, and the column decoder 13
0 and a row decoder 140. In the memory cell array 100, memory cells MC11 and MC21, MC12 and M are provided.
C22, and MC13 and MC23 are the power sources V1 and V2, respectively.
They are connected in series with a voltage wire N1 interposed therebetween, and have two stages of a power supply memory array VL1 composed of memory cells MC11, MC12 and MC13 and a power supply memory array VL2 composed of memory cells MC21, MC22 and MC23. It has a memory array between power supplies. In addition, memory cells MC11, MC12,
And MC13 are connected to the word line WL1 and memory cells MC21, M
C22 and MC23 are connected to the word line WL2, respectively. Further, the memory cell MC11 has a bit line pair BL11,
/ BL11 has a bit line pair BL21, /
The memory cell MC12 is connected to BL21 by a bit line pair BL12, / B.
The memory cell MC22 is connected to the bit line pair BL22, / BL at L12.
At 22, the memory cell MC13 has a bit line pair BL13, / BL13.
In addition, the memory cell MC23 has a bit line pair BL23, / BL23.
, Respectively.

FIG. 2 is a circuit diagram of the memory cells MC12 and MC22. In the figure, Tr12-1, Tr12-2, Tr22-1,
Tr22-2 is a depletion type FET (DFET), Tr1
2-3 to Tr12-6, Tr22-3 to Tr22-6 are enhancement type FET (EFET), INV12-1 is transistor Tr1.
INV12-2 is an inverter composed of 2-1 and Tr12-3, INV12-2 is an inverter composed of transistors Tr12-2 and Tr12-4, IN
V22-1 is an inverter composed of transistors Tr22-1 and Tr22-3, and INV22-2 is transistors Tr22-2 and Tr22-4.
, BL is a bit line, / BL is an inverted bit line, WL is a word line, V1 is a power supply for generating a reference voltage, V2 is a power supply for generating a negative voltage, N1 is a wiring between power supplies, and a memory cell MC12 , MC22 each include a latch circuit including two inverters and two transfer gates including transistors.

Next, the operation of the semiconductor memory device according to the first embodiment will be described by taking the case of writing "L" data in the memory cells MC12 and MC22 as an example. First, the bit line BL
When the "L" signal is applied to 12 and BL22, the "H" signal is applied to the inverted bit lines / BL12 and / BL22, and the "H" signal is applied to the word lines WL1 and WL2, the transistor Tr12-5 is supplied. , Tr12-6, and Tr22-5, Tr22-6 become conductive, so that the nodes N12-1, and N22-1 are "L",
The nodes N12-2 and N22-2 become "H". After that, when the word lines WL1 and WL2 become "L", the transistors Tr12-5, Tr12-6, Tr22-5 and Tr22-6 are turned off.

First, the operation of the memory cell MC12 will be described. The "L" signal of the node N12-1 is input to the input I12-2 of the inverter INV12-2, and the transistor T
The r12-4 becomes non-conductive, and the output O12-2 (the same potential as the node N12-2) of the inverter INV12-2 becomes "H". The output O12-2 of the inverter INV12-2 is the inverter I
Since it is input to the input I12-1 of NV12-1, the transistor Tr12-3 becomes conductive, and the transistor Tr12-1
Current flows between the power source V1 and the voltage wiring N1 via the inverter INV12-1 composed of the inverter Tr2 and Tr12-3,
The output O12-1 of 12-1 (the same potential as the node N12-1) becomes "L". The memory cell MC12 is connected to the inverter I
Since the latch circuit composed of NV12-1 and INV12-2 is configured to invert the input of one of the inverters and feed it back to the input of the other inverter, the transistor Tr1
As long as power is supplied to the latch circuit even after 2-5 and Tr12-6 are turned off, nodes N12-1, N12-2
Will be stable in the state of holding the initially given data "L" and "H", respectively, and store the data.

The same operation is performed in the memory cell MC22, and a current flows between the voltage wire N1 and the power supply V2 via the inverter INV22-1 composed of the transistors Tr22-1 and Tr22-3. That is, since the inverters INV12-1 and INV22-1 are connected in series between the power sources V1 and V2, the voltage between the power sources V1 and V2 is divided, so that the voltage applied to each of the memory cells MC12 and MC22. Is half the voltage between V1 and V2.

The above description of the operation is made in the bit line BL12.
And "L" signal to BL22, inverted bit lines / BL12 and / B
Although the "H" signal is applied to L22 respectively, any other combination of signals is applied to each of the memory cells MC12 and MC22 through one of the inverters. Power supply V
Since a current flows between 1-the voltage wire N1 or between the voltage wire N1-the power supply V2, the voltage applied to each of the memory cells MC12 and MC22 is half of the voltage between the power supply V1-V2.

In the semiconductor memory device according to the first embodiment, the memory cell array 100 is connected to the power source V1 −
N × m (n = 2 in this embodiment) memory cells are arranged in an array of n stages (n = 2) between V2 and the power source V
Since n (n = 2) memory cells are connected in series between 1 and V2, the voltage applied to each memory cell can be suppressed to half the voltage between the power sources V1 and V2. Therefore, if the number of bits is the same as that of the conventional one, the power consumption of the semiconductor memory device can be halved.

Embodiment 2 FIG. FIG. 3 (a) is a schematic diagram of a semiconductor memory device according to the second embodiment of the present invention, and FIG. 3 (b) is FIG.
3 is a detailed view of a B part and a B ′ part in FIG. The semiconductor memory device according to the second embodiment includes a first sub array 210 and a second sub array 210.
Memory cell array 200 including a sub-array 250 of
And the first sense amplifier 2 for the first sub-array 210
20, a first column decoder 230, a first row decoder 240, a second sense amplifier 260 for the second sub-array 220, a second column decoder 270, and a second row decoder 280, Sub array 21
At 0, the memory cells MC11, MC12 and MC13 are connected between the power source V1 and the voltage wire N1, respectively, and are also connected to the bit line pair BL10, / BL10, respectively.
One sub-array is formed with other memory cells. On the other hand, in the sub-array 250, the memory cell MC21,
MC22 and MC23 are respectively the voltage wiring N1-power source V
It is connected between the two, and each bit line pair BL20, /
It is connected to BL20 and constitutes one sub-array with other memory cells. Each memory cell is the same as the SRAM described in the section of the related art.

That is, the semiconductor memory device according to the second embodiment is different from the semiconductor memory device according to the first embodiment in that it replaces the memory cell array 100 shown in FIG. 1, that is, between the power supply V1 and V2 which is the drive voltage of the memory cells. , N × m memory cells (n = 2 in the above embodiment) are arranged in an array of n stages, and n memory cells are connected in series between the power sources V1 and V2. 3, the memory cell array 200 is replaced by m memory cells in each of the n stages (n = 2) arranged in a plurality of memory regions in each stage as shown in FIG. It is made up of n (n = 2) sub-arrays 210 and 250 arranged in a matrix.

In the semiconductor memory device according to the second embodiment as described above, since the sub-array 210 has the above-mentioned configuration, the sub-array 210 is between the drive voltages of the memory cells, that is, the power source V.
The memory cells are arranged so that only one memory cell is connected in series between the 1-voltage line N1 and the sub-array 250.
Can be arranged such that only one memory cell is connected in series between the drive voltages of the memory cells, that is, between the voltage wiring N1 and the power supply V2.
As 0 and 250, a memory cell array arranged in the same configuration as a conventional memory cell array, that is, a memory cell array in which only one memory cell is connected in series between drive voltages of the memory cells can be used. ,
It is possible to obtain a semiconductor memory device capable of halving the power consumption by using only the conventional memory cell array without manufacturing a memory cell array having a special memory cell arrangement.

Embodiment 3 FIG. FIG. 4 (a) is a schematic diagram of a semiconductor memory device according to the third embodiment of the present invention, and FIG. 4 (b) is FIG. 4 (a).
3 shows a detailed view of a C part in FIG. The semiconductor memory device of the third embodiment includes a memory cell array 300, a first sense amplifier 310, a second sense amplifier 320, a column decoder 330, a first row decoder 340, and a second row decoder 340.
Row decoder 350 of the memory cell array 3
In 00, the inter-power supply memory array VL1 composed of the memory cells MC11, MC12 and MC13 is connected between the power supply V1 and the voltage wire N1 and the word line WL1 and connected between the power supplies composed of the memory cells MC21, MC22 and MC23. The memory array VL2 is connected between the voltage wire N1 and the power supply V2 and to the word line WL2, respectively, and the memory cell MC11 is connected to the bit line pair BL11, / BL11 and the memory cell MC21 is connected to the bit line pair BL21, /. BL21, the memory cell MC12 is a bit line pair BL12, / BL12, the memory cell MC22 is a bit line pair BL22, / BL22, a memory cell M.
C13 is connected to the bit line pair BL13, / BL13 and is connected to the memory cell MC
23 is connected to the bit line pair BL23, / BL23. Each memory cell is the same as the SRAM described in the section of the related art.

That is, the semiconductor memory device according to the third embodiment is the same as the semiconductor memory device according to the first embodiment except that n stages (n = 2).
The memory cells for two stages of the inter-power supply memory arrays VL1 and VL2 are laid out on a straight line in a direction perpendicular to the bit line. This is an n-stage (n is an integer of 2 or more) inter-power supply memory. In a memory cell array having an array, the n
The memory cells of the inter-power supply memory array for one stage (l is an integer of 2 or more and n or less) of the inter-power supply memory array of stages may be laid out on a straight line in a direction perpendicular to the bit line.

Since the semiconductor memory device according to the third embodiment is configured as described above, in the first embodiment, n connected in series between drive voltages in one memory cell. Bit line pairs of n (2) memory cells, that is, n bit line pairs are wired, but only one bit line pair is wired in one memory cell. Therefore, the area of each memory cell forming the semiconductor memory device can be reduced, and as a result, the chip area of the semiconductor memory device that can reduce the power consumption to half can be reduced.

Embodiment 4 FIG. FIG. 5 (a) is a schematic diagram of a semiconductor memory device according to the fourth embodiment of the present invention, and FIG. 5 (b) is FIG. 5 (a).
3 shows a detailed view of a section D in FIG. The semiconductor memory device according to the fourth embodiment includes a memory cell array 400, a sense amplifier 410, a column decoder 420, and a row decoder 43.
0, and in the memory cell array 400, memory cells MC11 and MC21, MC12 and MC22, and MC13 and MC.
23 and 23 are connected in series between the power supplies V1 and V2 with the voltage wire N1 interposed therebetween, and memory cells MC11 and MC1 are connected.
An inter-power supply memory array VL1 composed of 2 and MC13 is connected to a word line WL1 and memory cells MC21, MC22, and MC23.
The memory array VL2 between the power supplies is connected to the word line WL2, the memory cells MC11 and MC21 are connected to the bit line pair BL11, / BL11, the memory cells MC12 and MC22 are connected to the bit line pair BL21, / BL21, and the memory cell MC13 is connected. MC
Reference numeral 23 is connected to the bit line pair BL21, / BL21, respectively. Each memory cell has the SR described in the section of the related art.
Same as AM. That is, the semiconductor memory device according to the fourth embodiment is the same as the semiconductor memory device according to the first embodiment described above except that the bit line pairs of the memory cells located in the same column are shared. The same as 1.

In the semiconductor memory device according to the fourth embodiment, the bit line pair of n (n = 2) memory cells connected in series between the power supplies V1 and V2 is shared in this way. The chip area of the semiconductor memory device that can reduce the power consumption to half can be reduced, and the total number of bit lines can be reduced by using a common bit line pair. Therefore, peripheral circuit parts such as sense amplifiers can be reduced. The number of points can be reduced.

[0040]

As described above, according to the semiconductor memory device of the present invention (Claim 1), in the semiconductor memory device having the memory cell array formed by the SRAM, the memory cell array is the first memory cell. N × m (m, n is an integer of 2 or more) memory cells arranged in an array of n stages between the first power supply and the second power supply. And n memory cells are connected in series with each other, the power consumption of each memory cell can be reduced, and thus the power consumption of the semiconductor memory device can be significantly reduced. effective.

According to the semiconductor memory device of the present invention (claim 2), in the semiconductor memory device according to claim 1, the n × m memory cells are connected to different bit line pairs. Since all the memory cells are simultaneously accessed, there is an effect that all the memory cells can be simultaneously accessed.

According to the semiconductor memory device of the present invention (claim 3), in the semiconductor memory device according to claim 1, a first power source and a second power source out of the n × m memory cells. Since the n memory cells connected in series with each other are connected to the common bit line pair, it is possible to reduce the number of bit lines. There is an effect that the degree of improvement can be improved and the number of parts of peripheral circuits such as a sense amplifier can be reduced.

According to the semiconductor memory device of the present invention (claim 4), in the semiconductor memory device according to claim 1, the memory cell array includes m memory cells in each of the n stages. Since each sub-array has n sub-arrays arranged in a plurality of memory areas in each row, a memory cell array having a conventional memory arrangement can be applied as the sub-array, and power consumption can be further simplified. There is an effect that a semiconductor memory device that can reduce the

According to the semiconductor memory device of the present invention (claim 5), in the semiconductor memory device according to claim 4, the m memory cells forming the sub-array are connected to different bit line pairs. Since it is assumed that all memory cells are accessed at the same time, there is an effect.

Further, according to the semiconductor memory device of the present invention (claim 6), in the semiconductor memory device according to claim 4, of the m memory cells forming the sub-array, the memory cells in the direction perpendicular to the word line are arranged. Since the memory cells arranged in a straight line are connected to a common bit line pair, the number of bit lines can be reduced, which improves the integration degree of the semiconductor memory device and sense amplifiers. This has the effect of reducing the number of parts of peripheral circuits such as.

According to the semiconductor memory device of the present invention (claim 7), in the semiconductor memory device according to claim 1, the memory cell array is one of the n stages.
Since the memory cells of the inter-power supply memory array of the number of stages (l is an integer of 2 or more and n or less) are arranged on a straight line perpendicular to the bit lines, the area of the memory cell array can be reduced. Therefore, there is an effect that the degree of integration of the semiconductor memory device can be improved.

According to the semiconductor memory device of the present invention (claim 8), in the semiconductor memory device of claim 7, the memory cells are connected to different bit line pairs. Therefore, there is an effect that all the memory cells can be simultaneously accessed.

According to the semiconductor memory device of the present invention (claim 9), in the semiconductor memory device according to claim 7, the memory cells are arranged in a straight line in a direction perpendicular to the word line. Since the existing memory cells are connected to a common bit line pair, the number of bit lines can be reduced, which improves the integration degree of the semiconductor memory device and parts of peripheral circuits such as sense amplifiers. There is an effect that the number of points can be reduced.

[Brief description of the drawings]

1 is a schematic view of a semiconductor memory device according to a first embodiment of the present invention (FIG. 1 (a)), and a detailed view of a portion A in FIG. 1 (a) (FIG. 1 (b)).

FIG. 2 is a circuit diagram of a memory cell in the semiconductor memory device according to the first embodiment.

FIG. 3 is a schematic view of a semiconductor memory device according to a second embodiment of the present invention (FIG. 3 (a)), B portion and B ′ in FIG. 3 (a).
3 is a detailed view of the part (FIG. 3 (b)).

FIG. 4 is a schematic view of a semiconductor memory device according to a third embodiment of the present invention (FIG. 4 (a)), a C portion and C ′ in FIG. 4 (a).
FIG. 4 is a detailed view of the part (FIG. 4 (b)).

FIG. 5 is a schematic view of a semiconductor memory device according to a fourth embodiment of the present invention (FIG. 5 (a)), a C portion and C ′ in FIG. 5 (a).
FIG. 6 is a detailed view of the part (FIG. 5 (b)).

FIG. 6 is a block diagram of a semiconductor memory device using a conventional SRAM (FIG. 6A), and a circuit diagram of an SRAM configured using field effect transistors (FIG. 6B).

[Explanation of symbols]

MC memory cell, memory array between VL power supplies, BL, /
BL bit line pair, WL word line, V1 reference voltage,
V2 power supply voltage, N1 voltage wiring, Tr12-1, Tr12-2, T
r22-1, Tr22-2 Depletion type FET, Tr12-3 ~
Tr12-6, Tr22-3 to Tr22-6 enhancement type FE
T, INV inverter.

Claims (9)

[Claims] 1. A static memory cell (hereinafter, SR
In a semiconductor memory device having a memory cell array formed of AM), the memory cell array has n × m pieces (m and n are 2 or more) between a first power supply and a second power supply. (Integer) memory cells are arranged in an array of n stages, and n memory cells are connected in series between the first power supply and the second power supply. A semiconductor memory device characterized by: 2. The semiconductor memory device according to claim 1, wherein the n × m memory cells are connected to different bit line pairs. 3. The semiconductor memory device according to claim 1, wherein among the n × m memory cells, n memories connected in series between a first power supply and a second power supply. A semiconductor memory device characterized in that cells are connected to a common bit line pair. 4. The semiconductor memory device according to claim 1, wherein the memory cell array has m memory cells in each of the n stages arranged in an array in a plurality of memory regions for each stage. A semiconductor memory device characterized by comprising n sub-arrays. 5. The semiconductor memory device according to claim 4, wherein the m memory cells forming the sub-array are connected to different bit line pairs. 6. The semiconductor memory device according to claim 4, wherein among the m memory cells forming the sub-array, memory cells arranged on a straight line in a direction perpendicular to a word line have a common bit line. A semiconductor memory device characterized by being connected in pairs. 7. The semiconductor memory device according to claim 1, wherein the memory cell array includes one of the n stages (l
Is an integer of 2 or more and n or less), and the memory cells of the memory array between power supplies are arranged on a straight line in a direction perpendicular to the bit line. 8. The semiconductor memory device according to claim 7, wherein the memory cells are connected to different bit line pairs. 9. The semiconductor memory device according to claim 7, wherein among the memory cells, memory cells arranged linearly in a direction perpendicular to a word line are connected to a common bit line pair. A semiconductor memory device characterized by the above.