JPH0916968A - Information reproducing circuit - Google Patents

Abstract

PURPOSE: To obtain the information reproducing circuit which can stably obtain a binarized signal having low-frequency components compensated in spite of an increase or decrease in the amplitude of a reproduced signal. CONSTITUTION: A DC component removing circuit 1 generates a signal (reproduced signal) a1 by removing DC components from a read signal a0. A timing generating circuit 2 detects a specific pattern from the reproduced signal a1 and generates a timing signal a2. A control voltage generating circuit 3 samples and holds the amplitude intermediate potential of the reproduced signal a1 according to the said timing signal a2 to generate a slice level a3 for the comparator of a quantization feedback circuit 4, and detects the amplitude of the reproduced signal a1 to generate an amplitude level b3. The feedback signal of the quantization feedback circuit 4 has its signal potential gain-adjusted according to the amplitude level b3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is, for example, provided in an optical recording / reproducing apparatus for optically reproducing information digitally recorded on a recording medium, and binarizes a reproduced signal to generate a digital reproduced signal. It relates to a reproducing circuit.

[0002]

2. Description of the Related Art Generally, in a recording medium such as a magneto-optical disk, a sector format including a header portion and a data portion is formed on a track, and information is recorded / reproduced in sector units. FIG. 5 is a schematic diagram showing an example of a sector format of a recording medium. In the figure, sector mark (SM)
Reference numeral 50 represents the beginning of the sector. Reference numeral 51 is a clock pull-in area (VFO section), which is arranged in the header section and at the beginning of the data section. 52, 53, 54, 55, 56, 5
7 are address marks (AM) and addresses (I
D), post-ambleless (PA), sync signal (Syn)
c), buffer, and data.

In an apparatus for recording / reproducing information on / from a recording medium such as a magneto-optical disk, an optical head for irradiating a laser beam on the recording medium and a read signal by photoelectrically converting a change in the amount of reflected light from the optical disk are provided. And an information reproducing circuit for extracting a reproduced signal from the read signal and binarizing the reproduced signal to reproduce the original digital signal. Since the photodetector detects a constant amount of reflected light and a weak change in the amount of reflected light due to digital information, when the photodetection result is converted into an electric signal, a DC component corresponding to the constant amount of reflected light is obtained. , And a weak reproduction signal corresponding to a slight change in the amount of reflected light appears in a superimposed manner. Here, the reproduction signal is a weak signal buried in noise, and it is necessary to amplify the signal in order to reproduce the signal. At this time, in consideration of the dynamic range of the amplifier, it is more effective to remove the DC component superimposed on the read signal. Therefore, conventionally, the DC component of the read signal is removed by AC coupling. However, when the DC component is removed by AC coupling, there is a problem that a part of the low frequency component of the reproduction signal is lost.

A circuit using quantized feedback is known as a reproducing circuit for compensating for the above-mentioned lost low frequency component (Journal of the Institute of Electronics and Communication Engineers, 86/5, Vol. J69-C, N.
o. 5, p. 644-652, "Improvement of low-frequency reproduction characteristics of digital magnetic recording using identification signal"). FIG. 6 is a block diagram showing this reproducing circuit (here, a DC component removing circuit such as AC coupling is omitted). This is composed of a high pass filter (hereinafter referred to as HPF) 101, an adder 102, a comparator 103, a constant voltage generator 104, and a low pass filter (hereinafter referred to as LPF) 105. There is.

FIG. 7 is a spectrum diagram for explaining the operation of FIG. 6, and FIG. 8 is a waveform diagram for explaining the operation of FIG. The quantization feedback circuit will be described below with reference to FIGS.

FIG. 7A shows the spectrum of the reproduction signal a100 input to the input terminal 110 of FIG. The reproduction signal a100 is a signal after the DC component of the read signal is removed by AC coupling, and some low frequency components are lost. This reproduction signal is input to the HPF 101, and A
Unwanted low-frequency components that could not be removed by C-bonding are removed,
The spectrum is as shown in FIG. Waveform is Figure 8
(A). Output a101 of this HPF101
The spectrum of the signal in which the low frequency component of is compensated is as shown in FIG. 7D, and the waveform is as shown in FIG. 8C.

In order to compensate the low frequency component by the quantization feedback, the output a102 of the adder 102 is shown in FIG.
It must be as shown in (d) and FIG. 8 (c). For this purpose, the spectrum of the returned signal a105 must be as shown in FIG. 7C (waveform is FIG. 8B). Here, it is the comparator 103 and the LPF 105 in FIG. 6 that generate the signal a105 having the spectrum shown in FIG. 7C. In the comparator 103, the output a102 of the adder 102 and the constant voltage generator 10
2 is compared with the slice level Vthd which is the output of 4
The binarized signal a 103 is obtained, and the LPF 105 binarizes the binarized signal a 103.
The high frequency component of 103 is removed, and the feedback potential a105 is generated. Normally, the slice level Vthd is the reproduction signal a100.
Is set to 1/2 of the reproduction signal amplitude Va. This is because digital information exists at the center of the data signal amplitude in general high-density recording in which mark edge recording is performed. As a result, the adder output a102 is as shown in FIG.
It has a spectrum in which the low-frequency component is compensated as shown in. That is, the waveform is as shown in FIG.

[0008]

However, in the above-mentioned conventional example, it is caused by the properties of the recording medium (specifically, the nonuniformity of the magnetic film or the solid difference between the recording media) and the environmental conditions such as the ambient temperature. As a result, the reproduction signal amplitude fluctuates, and instability occurs such as the duty of the binarized signal a103 output from the comparator 103 fluctuating.

This means that, for example, the binarized signal a103
Data synchronization clock from PLL (Phase Loc)
It becomes a big problem when it is generated by a ked loop). In the PLL, the input digital signal a10
The phase difference between 3 and the clock signal is detected, and the frequency of the clock signal is controlled so that the phase difference becomes zero. At this time, when the input digital signal a103 has a duty variation and is edge-shifted, the phase relationship established with the clock signal is not established and the synchronous clock becomes unstable. As a result, a reproduction error may occur.

In addition, PRML (Partial Res)
pose Maximum Likelihood)
Therefore, even when a digital signal is obtained from the adder output a102, a highly accurate signal cannot be extracted.

The above problems become more prominent as the recording density increases. That is, when the reproduction signal amplitude of the minimum mark becomes small as a result of the high density by OTF, the influence of the amplitude fluctuation becomes larger.

Hereinafter, it will be described with reference to FIG. 8 that the binarized signal a103 becomes unstable due to the fluctuation of the reproduction signal amplitude.

FIG. 8 (d) shows that the amplitude of the output a101 of the HPF 101 changes from Va to Vb as a result of the decrease of the reproduction signal amplitude.
FIG. 9 is a waveform diagram showing a case where (Vb <Va) is satisfied. In this case, the relationship between the signal amplitude Vb and the slice level Vthd is Vthd> Vb / 2. Therefore, if binarization is performed at this slice level Vthd, the obtained digital reproduction signal a103 will be different from the digital signal on the recording medium. Specifically, the slice level a104
Is relatively increased, the duty of the digital reproduction signal a103 after binarization is reduced. as a result,
The feedback potential a105 after passing through the LPF 105 becomes small,
The adder output a102 is a signal with insufficient feedback as shown in FIG. 8 (e).

It is known to use an automatic gain control circuit (hereinafter referred to as an AGC circuit) for increasing / decreasing the amplitude of the reproduction signal so as to control the amplitude of the reproduction signal in order to suppress the fluctuation of the reproduction signal. , JP-A-63-124266, JP-A-4-11361).

The AGC circuit detects the amplitude of the input reproduction signal and determines the amplification factor from the detection result. As a method of detecting the amplitude, there are a method of using an envelope detection circuit and a method of sampling / holding the amplitude in a predetermined pattern in the reproduced signal.

However, the method (1) has a high possibility of causing a malfunction due to the influence of impulse-like noise caused by defects existing on the recording medium.

Further, although the above method can avoid the influence of the above-mentioned noise, since the reproduced signal is amplified or attenuated, a transient phenomenon occurs in the reproduced signal. To avoid the effects of this transient, for example,
It is necessary to detect the amplitude at the head of the reproduced signal of the sector (SM50 in FIG. 5) to determine the amplification factor, and apply the amplification factor from the time of reproducing the next sector. Therefore, there is a problem that the reproduction signal cannot be controlled in real time because of a large delay time.

The present invention has been made to solve the above problems, and an object of the present invention is to provide an information reproducing circuit capable of generating a stable binarized signal regardless of the fluctuation of the amplitude of the reproduced signal. And

[0019]

According to the present invention, a DC component remover for generating a reproduced signal by removing a DC component from a signal read from a recording medium, and a high-pass filter for removing a low-frequency component of the reproduced signal. The filter, an adder that adds the output of the high-pass filter and the feedback signal, and the output of the adder are 2
In an information reproducing circuit including a comparator that digitizes a digital reproduced signal and a low-pass filter that removes a high frequency component of the output signal of the comparator to generate a feedback signal, a timing from the reproduced signal is generated. At the timing indicated by the timing signal and the timing signal generating the signal, the center potential of the amplitude of the reproduced signal is sampled / held to the slice level, and the amplitude potential of the reproduced signal is sampled / held to the amplitude level. And a gain adjuster that adjusts the gain of the signal potential of the feedback signal based on the amplitude level.

The gain adjuster includes a multiplier that multiplies the amplitude level and the output of the low pass filter.

Further, it comprises a delay element for delaying the reproduction signal input to the high pass filter or the output signal of the high pass filter for a predetermined time.

[0022]

In the present invention, the timing signal is generated from the reproduction signal by the timing generator. Then, at that timing, the control voltage generator samples / holds the amplitude intermediate potential of the reproduction signal and sets it as the slice level of the comparator. Therefore, the slice level of the comparator also increases or decreases as the amplitude of the reproduction signal increases or decreases. Therefore, the output of the comparator can always be a digital reproduction signal having a pulse width substantially equal to the recording mark length.

At the above timing, the control voltage generator samples / holds the amplitude of the reproduction signal to obtain the amplitude level. Then, the gain adjuster adjusts the feedback signal potential based on the amplitude level. Therefore, the maximum value of the signal potential of the feedback signal can always be set to approximately 1/2 of the amplitude of the reproduction signal. Therefore, it is possible to accurately compensate the low frequency component.

Further, since the amplitude of the reproduced signal is not increased or decreased and the slice level is increased or decreased, there is no transient response and it is possible to deal with the amplitude fluctuation of the reproduced signal in almost real time.

According to another aspect of the information reproducing circuit of the present invention, the gain adjuster has a multiplier for multiplying the amplitude level by the output of the low pass filter. Therefore, the feedback signal potential can be increased / decreased as the amplitude of the reproduction signal is increased / decreased.

In the information reproducing circuit according to the third aspect, the reproduction signal is delayed by the delay element until the slice level and the amplitude level generated by the control voltage generator become stable. Therefore, the reproduced signal can be binarized more accurately.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The information reproducing circuit of the present invention will be described below. Here, the case where the information reproducing circuit of the present invention is applied to an optical disk device will be described.

FIG. 1 is a conceptual diagram showing the structure of the information reproducing circuit, and FIG. 2 is a circuit block diagram showing an example of the circuit.

In FIG. 1, a0 is a read signal, which is a signal obtained by photoelectrically converting the reflected light from the optical disk device. The read signal a0 is processed by a DC component removing circuit (DC component removing device in the claims) 1 including an AC coupling, an amplifier, a low pass filter, an equalizer, etc., and a reproduced signal a1 is processed.
Becomes The reproduction signal a1 is input to a timing generation circuit (timing generator in claims) 2, a control voltage generation circuit (control voltage generator in claims) 3, and a quantization feedback circuit 4.

The timing generation circuit 2 detects the signal portion of the reproduction signal a1 and generates the timing signal a2.

The control voltage generating circuit 3 generates a slice level a3 and an amplitude level b3 based on the timing signal a2 from the timing generating circuit 2. The slice level a3 is set to the intermediate potential of the signal amplitude of the reproduction signal a1,
It increases / decreases as the amplitude of the reproduction signal a1 increases / decreases. The control voltage b3 is a signal representing the amplitude level of the reproduction signal.

The quantizing feedback circuit 4 is basically the same as that shown in the conventional example, but the slice level a3 from the control voltage generating circuit 3 is used as the slice level of the comparator 44. Therefore, the slice level a3 of the comparator 44 increases or decreases according to the increase or decrease of the reproduction signal a1, and the binarized signal output from the comparator 44 has a stable pulse width having a pulse width substantially equal to the recording mark length. Become a signal.

The signal potential of the feedback signal a47 is changed by the gain adjuster (amplifier 47 and multiplier 46) according to the amplitude level b3. Specifically, the maximum value of the signal potential of the feedback signal a47 is set to a potential that is approximately ½ of the amplitude of the reproduction signal a1. Therefore, it is always possible to accurately perform the compensation of the low frequency component of the reproduction signal a1.

The above is the outline of the information reproducing circuit of this example.
The information reproducing circuit of this example will be described below in detail with reference to the waveform chart shown in FIG.

First, the timing generation circuit 2 will be described. The timing generation circuit 2 of this example includes a comparator 21, a retriggerable one-shot vibrator 23, and a one-shot multivibrator 24.
The timing signal a2 is output at the header of the reproduction signal a1 and the beginning of the data part.

The comparator 21 outputs the reproduction signal a1 (FIG. 3A).
Reference) and the constant voltage signal a22, and outputs "H" when a signal is present. Retriggerable one shot
The vibrator 23 maintains "H" for a certain time T from the rising edge (hereinafter, referred to as "↑ edge") of the output a21 of the comparator 21. Further, when the ↑ edge is input again within the time T from the ↑ edge, “H” is maintained for a further time T from the ↑ edge input later (FIG. 3).
(B)). Here, the time T is set to be longer than the longest period of the reproduced signal a1 and shorter than the interval (gap) between the header section and the data section. The one-shot multivibrator 24 outputs "L" for a predetermined time from the input of the ↑ edge of the output a23 of the retriggerable one-shot vibrator 23, and then outputs "H" again (see FIG. 3 (c)). ). This output a2 is a timing signal and is input to the control voltage generation circuit 3.

Next, the control voltage generating circuit 3 will be described. The reproduced signal a1 is input to the equalizer 31, where only the high frequency component is amplified so that the signal amplitude difference due to the mark length is eliminated. That is, it is converted into the signal a31 having no signal amplitude difference between the VFO part and the data part (FIG. 3).
(D)).

This signal a31 is supplied to the envelope detection circuit 3
2 is input. The envelope detection circuit 32 receives the signal a3
The upper envelope potential and the lower envelope potential of 1 are detected. Then, based on the detected upper and lower envelope potentials, an amplitude intermediate potential (hereinafter, referred to as an envelope intermediate potential) a of the reproduction signal a1.
32 detection, sample / hold circuit (S / H circuit)
Output to 33. The above-mentioned envelope intermediate potential a32 is obtained by halving the sum signal of the detected upper and lower envelopes.

The S / H circuit 33 samples / holds the envelope intermediate potential a32 based on the timing signal a2. Specifically, the timing signal a
When 2 is "L", it is in the sample state, and when it is "H", it is in the hold state. Therefore, the S / H circuit 33
Becomes a sampling state when a signal arrives and holds the envelope intermediate potential a32 of the reproduction signal a1 for a predetermined time. The output of the S / H circuit 33 is the slice level a.
3 (see FIG. 3E) is output to the quantization feedback circuit 4.

The S / H circuit 34 receives the difference signal b32 between the upper and lower envelope potentials from the envelope detection circuit and samples / holds the difference signal b32 based on the timing signal a2. Specifically, when the timing signal a2 is "L", the sampling state is set. On the contrary, "H" is set.
At the time of, it becomes a hold state. Therefore, the S / H circuit 3
4 becomes a sampling state when a signal arrives, and holds the difference signal b32 of the equalizer output a31 at a predetermined time. The output of the S / H circuit 34 is the amplitude level b3 (see FIG.
(See (f)) is output to the quantization feedback circuit 4.

Next, the quantizing feedback circuit 4 will be described. Since the quantizing feedback circuit 4 is basically the same as that shown in the conventional example, the HPF 42, the adder 43, L
The description of the PF 45 is omitted. The difference from the conventional one is that the slice level a3 generated by the control voltage generation circuit 3 is input to the comparator 44, and L
That is, the output of the PF 45 is multiplied by the amplitude level b3 by the multiplier 46, and the gain is adjusted by the amplifier 47. Incidentally, the amplifier 47 is an amplifier having a fixed amplification (or attenuation) rate, and a certain reference signal is used in advance,
The amplification (attenuation) rate is adjusted so that the maximum value of the output a47 of the amplifier 47 is approximately 1/2 of the output of the HPF 42.

In the quantized feedback circuit 4, when the reproduction signal a1 having a certain amplitude is input, the slice level a3 of the comparator 44 is about 1/2 of the reproduction signal amplitude in the control voltage generating circuit 3 described above. Is adjusted to the potential of. Therefore, the binarized signal a44 always has a pulse width substantially equal to the recording mark length.

When the amplitude of the reproduced signal a1 increases or decreases,
Accordingly, the amplitude level b3 input to the multiplier 46 increases or decreases. Therefore, the binarized signal a44 (the amplitude of this signal is a substantially constant voltage regardless of the increase / decrease of the reproduction signal a1).
Passes through the LPF 45 and is multiplied by the amplitude level b3 to be converted into the feedback signal a47 whose signal potential changes according to the amplitude of the reproduction signal a1. For example, when the amplitude of the reproduction signal a1 becomes 1.5 times, the amplitude level b3 becomes 1.5 times, and the signal potential of the feedback signal a47 becomes 1.5 times. Therefore, even if the amplitude of the reproduced signal a1 is increased or decreased, the low-frequency component of the reproduced signal a1 can be accurately compensated by the feedback signal a47, and the adder output a43 as shown in FIG. 3 (g) is obtained. Is possible.

As described above, according to the present example, it is possible to stably generate the binarized signal in which the low frequency component is compensated, regardless of the increase / decrease in the amplitude of the reproduction signal a1.

Even when the HPF 42 has a high cutoff frequency and a strong transient response, a stable binarized signal a44 is obtained.
Therefore, it is possible to remove the influence of AC coupling and low noise more than before by using the HPF 42 having a high cutoff frequency.

Further, even when reproducing by PRML using the output a43 of the adder 43, a highly accurate digital signal can be obtained.

In the above example, it takes some time for the slice level a3 and the amplitude level b3 generated by the control voltage generating circuit 3 to stabilize. In order to eliminate the influence of this time, a delay element may be provided in the preceding stage of the quantization feedback circuit 4. FIG. 4 is a circuit block diagram showing an information reproducing circuit provided with the delay element 41. According to this circuit, the signal input to the adder 43 is delayed by the time τ, and quantization feedback can be performed in a state where the slice level a3 and the amplitude level b3 are stable, resulting in a more stable binarized signal. Can be obtained. FIG. 3 (h) is a waveform diagram showing the input a42 to the adder 43 at this time.

[0048]

According to the present invention, even if the amplitude of the reproduced signal is increased or decreased due to a defect of the recording medium, the slice level in the comparator is always at the intermediate potential of the reproduced signal amplitude. It is possible to obtain a stable binarized signal. Further, since the signal potential of the feedback signal is adjusted based on the amplitude level, it is possible to always accurately compensate the low frequency component of the reproduction signal by the quantization feedback.

Further, since the amplitude of the reproduced signal is not increased or decreased and the slice level is increased or decreased, there is no transient response and it is possible to cope with the amplitude fluctuation of the reproduced signal in almost real time.

Further, since the HPF cutoff frequency can be set to a high value, it is possible to remove low frequency noise generated due to various causes such as the influence of AC coupling and reflectance fluctuation, thereby increasing the detection margin. It will be possible.

Furthermore, even when reproducing by PRML using the output of the adder, a highly accurate digital signal can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a configuration of an information reproducing circuit of the present invention.

FIG. 2 is a circuit block diagram showing a circuit example of an information reproducing circuit.

FIG. 3 is a waveform diagram illustrating the operation of FIG.

FIG. 4 is a circuit block diagram showing another example of the information reproducing circuit.

FIG. 5 is a schematic diagram showing a sector format of a recording medium.

FIG. 6 is a circuit block diagram showing a conventional information reproducing circuit.

FIG. 7 is a spectrum diagram illustrating the operation of FIG.

FIG. 8 is a waveform diagram illustrating the operation of FIG.

[Explanation of symbols]

 1 DC component removal circuit 2 Timing generation circuit 3 Control voltage generation circuit 4 Quantization feedback circuit 32 Envelope detection circuit 33, 34 S / H circuit 41 Delay circuit 44 Comparator 46 Multiplier 47 Amplifier a0 Read signal a1 Reproduction signal a2 Timing signal a3 Slice level b3 Amplitude level

Claims (3)

[Claims] 1. A DC component remover for producing a reproduced signal by removing a DC component from a signal read from a recording medium, a high-pass filter for removing a low-pass component of the reproduced signal, and the high-pass filter. An adder for adding the output of the filter and the feedback signal, a comparator for binarizing the output of the adder to generate a digital reproduction signal, and a high-frequency component of the output of the comparator for removing the feedback signal And a low-pass filter that generates a low-pass filter, and a timing generator that generates a timing signal from the reproduction signal, and a center potential of the amplitude of the reproduction signal at a timing indicated by the timing signal. A control voltage generator that holds / holds the slice level of the comparator and samples / holds the amplitude potential of the reproduction signal to the amplitude level; Based on the width level, information reproduction circuit characterized in that it comprises a gain adjuster for gain adjusting the signal potential of the feedback signal. 2. The information reproducing circuit according to claim 1, wherein the gain adjuster includes a multiplier that multiplies the amplitude level and an output of the low pass filter. . 3. The information reproducing circuit according to claim 1 or 2, further comprising a delay element for delaying the reproduced signal or the output signal of the high pass filter for a predetermined time. Information reproduction circuit.