JPH06223508A - Signal reproducing method for recording medium - Google Patents

Abstract

PURPOSE:To make the binarization of a signal at the same slice level possible by replacing a reproducing signal having the fluctuation of a low frequency component with another signal in an area other than a demodulation area, a non-recorded part and a relatively long default signal area. CONSTITUTION:The default and non-recorded areas of the reproducing signal are detected by a waveform shaping circuit 9. The output (c) of a DC correction circuit 2 is inputted to a signal compensation circuit 3 and replaced with a compensation signal (d) whose average potential is equal to a reference voltage Vr before a reproducing area, the non-recorded area in the reproducing area being reproduced and in the relatively long default signal area. Also even in the condition that a read gate (e), that is, a signal reproducing area from a system controller 14, is negative, when the non-recorded area being reproduced and the relatively long default signal area are detected by default detection circuits 10 and 11, it is replaced with the compensation signal (d) by the default detection signal (f) of the circuits 10 and 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal reproducing method for a recording medium. More specifically, the present invention relates to a signal reproduction method for binarization without removing frequency components lower than the recording signal band, and particularly for signal reproduction of an optical recording medium in which a recorded portion and a non-recorded portion of the signal are mixed. The present invention relates to a suitable signal reproducing method and apparatus.

[0002]

2. Description of the Related Art As information storage devices, there are known optical disk devices and magneto-optical disk devices that irradiate a light beam and reproduce the signal from a recording medium on which recording marks are recorded by utilizing the irradiation heat. In this type of information storage device,
The shape of the recording mark recorded on the recording medium changes due to variations in the emission power of the semiconductor laser, variations in sensitivity of the optical disc medium, variations in sensitivity due to the environment, etc., and this variation in the shape of the recording mark becomes even-order distortion during reproduction, There is a problem that the duty of the reproduction signal varies.

In order to remove this distortion, it is necessary to properly control the slice level of the comparator that binarizes the reproduction signal. An example of this method is described on pages 116 to 118 supervised by Kunimaro Tanaka, signal processing technology for optical recording, 1989, published by Trikeps Co., Ltd.

FIG. 3 shows a conventional signal reproducing circuit. A recording medium recorded by mark length recording in which information is provided at the edge position of the recording mark is irradiated with laser light, the reflected light is detected to obtain a reproduction signal, and the amplifier 15 amplifies it to a desired amplitude. The reproduced signal has low-frequency component fluctuations due to fluctuations in the reflectance and birefringence of the recording medium and deviations of the laser beam from the track center. In order to remove this fluctuation, it is passed through a high-pass filter (hereinafter referred to as HPF) 5 and input to a waveform shaping circuit 8 which is a reproduction signal binarizing means for demodulating the recorded data. On the other hand, the upper and lower envelope detection circuits 16 and 17 for detecting the upper and lower envelopes of the amplified reproduced signal are input to the lower envelope detection circuit 17, and the difference between the respective outputs is detected by the difference circuit 18, and the waveform shaping circuit 8 Obtain half the level of the signal amplitude input to. The slice level of the waveform shaping circuit 8 is provided at each head of a recording area (hereinafter referred to as a sector) obtained by dividing the recording medium into a large number along a track, and a sync signal area (for synchronizing the phase of the demodulation clock). (Hereinafter referred to as VFO section), the level is set to half the level of the reproduced signal. Therefore, the sample-hold circuit 19 is controlled by the VFO gate showing the VFO section, and the level of one half of the reproduction signal obtained from the VFO section is input as the slice level of the waveform shaping circuit 8. The reproduction signal of the VFO section is used to set the slice level because the signal duty of the reproduction waveform of the VFO section is 50% in mark length recording, and the center level of the reproduction signal is obtained by binarizing the reproduction signal. This is because the slice level becomes appropriate.

It is to be noted that the reason why the setting of the slice level is limited to the VFO section is a reference for the VFO section to perform phase synchronization of the reproduction signal, and the duty of the reproduction signal other than the VFO section is different, so that the upper envelope detection is not performed. This is because the sensitivities of the lower envelope detection are different and not all signals have proper slice levels.

[0006]

FIG. 4 shows the waveform of each part of the circuit shown in FIG. Hereinafter, the state of signal reproduction in the case where the signal is recorded in only one portion in one track as shown in FIG. 4A will be described. In order to simplify the explanation, the waveform of the VFO section has a signal duty of 50.
%, And the center level, which is a proper slice level for binarization, has the same average level of the unrecorded level and the DC recorded level.

The signal a passes through the HPF 5, and the waveform shaping circuit 8
The signal input to is a waveform b. On the other hand, the outputs of the upper envelope detection circuit 16 and the lower envelope detection circuit 17 are waveforms c and d, respectively, and the output of the comparison circuit 18, which is the difference waveform between them, is e in FIG. The waveform e in FIG. 4 is the VFO of the reproduced signal.
While the VFO gate shown in FIG. 4F is at a high level, it is not always equal to the DC level fluctuation caused by the HPF5, and is not necessarily equal to the DC level fluctuation caused by the HPF5 in other portions. Therefore, the sampling operation is performed while the VFO gate f is at the high level, and the VF gate is provided except for the VFO section.
The O gate f is set to low level, the output of the comparison circuit 18 is held at the final part of the VFO section, and the waveform represented by g in FIG. 4 is sent to the other input of the waveform shaping circuit 8. The broken line g in FIG.
The waveform shown by is the other input signal of the waveform shaping circuit 8 shown in b.

As shown in FIG. 4, when the VFO section is shorter than the over-response time for the HPF 5 to settle the DC level fluctuation, the slice level of the waveform shaping circuit 8 is held before the DC level fluctuation is settled. Therefore, since the slice level deviates from the proper value (dotted line g in FIG. 4) by the DC level fluctuation of the HPF 5 after the hold, there is a problem that the signal cannot be correctly read when only one portion of the signal is recorded in the track. Occurs.

This is not only the case where a signal is recorded in only one part in one track, but also when the reproduced signal has an instantaneous DC level fluctuation, for example, a boundary between an address signal part and a data signal part in a magneto-optical disk device. The same problem occurs immediately after a seek operation for searching the reproduction signal portion, immediately after reproducing a large defective portion, immediately after recording or erasing a signal, and the like. In the first case, the address signal is recorded on the unevenness of the recording medium, and the data signal is recorded as the change of the magnetic field of the recording medium. Therefore, the signal detection method is different, and thus the DC level of the reproduction signal is also different. In the case of the 2nd to 4th, at the time of seek, reproduction of the defective portion and recording / erasing,
Since the correct signal is not detected, the DC level of the reproduced signal varies, and when the correct signal is reproduced thereafter, the DC level changes.

Further, if there is a defect in the VFO portion which is the specific pattern portion, the means for controlling by the signal of the VFO portion cannot perform proper control.

In view of the above point, the present invention provides a method of binarization without removing frequency components lower than the recording signal band.
It is an object of the present invention to provide a signal reproducing method and device for a recording medium, which can always read a normal signal stably even if there is an unrecorded portion or a defect.

[0012]

According to the signal reproducing method of the present invention, the voltage detected in the specific pattern portion is replaced with an arbitrary signal having an average potential and interpolation is performed except during the period for reproducing the recording signal. Characteristically, the information storage device of the present invention has a signal reproducing circuit provided with a circuit for generating this interpolation signal.

Further, the present invention has means for detecting an abnormality of the signal by the binarizing means different from the binarizing means for performing the signal demodulation, and means for controlling the specific pattern portion by the detected signal. To suspend.

Further, the present invention is an information storage device having a signal reproducing circuit provided with a reproduced signal DC level correction circuit, a gain control circuit, a low frequency cutoff compensation circuit, and a slice level control circuit.

[0015]

According to the present invention, since the interpolation signal is replaced except during the reproduction period of the recording signal to be read, even if there is an unrecorded portion or a defect in the recording medium, it is possible to suppress the DC fluctuation of the signal and stabilize the signal. The signal can be played back.

Further, a defect of the reproduction signal in the specific pattern portion is detected by a binarizing means different from the binarizing means for demodulating the reproduction signal, and the means for controlling in the specific pattern portion is interrupted. It is possible to prevent the control from performing an improper operation.

Further, according to the present invention, the reproduced signal is processed in the order of the direct current level correction means, the gain control means, the low frequency cutoff compensation means and the slice level control means to stably binarize the reproduced signal with respect to the direct current level fluctuation. can do.

[0018]

1 is a block diagram of a signal reproducing circuit for carrying out the signal reproducing method of the present invention, showing a first embodiment of the present invention. FIG. 2 illustrates the operation by referring to FIG.
The waveforms of the respective parts are shown.

The reproduced signal a from the recording medium is amplified by a gain control amplifier 1 which controls the amplitude of the reproduced signal according to the reflectance information of the recording medium which has been recorded in advance on the recording medium, and a DC signal.
Input to the correction circuit 2 and the waveform shaping circuit 9. The DC correction circuit 2 corrects the DC level of the reproduced signal, and
Controlled by a control signal b from the O section control circuit 12,
The center potential or average potential of the upper and lower envelope potentials of the FO portion is made to match the reference potential Vr.

FIG. 5 shows an example of the DC correction circuit 2. The difference circuit 16 calculates the upper envelope potential m and the lower envelope potential n obtained by the upper envelope detection circuit 16 and the lower envelope detection circuit 17 to obtain the central potential p, and the central potential p and the reference potential Vr. The difference circuit 20 obtains the difference potential q. Then, the sample hold 1 is performed by the VFO gate t from the system controller 14.
9 is controlled to form a correction signal r, which is added to the input signal by the adder 21 to perform the correction. It is also possible to obtain an average potential with a low-frequency cutoff filter and use this average potential instead of the center potential p in FIG.

The waveform shaping circuit 9 is used to detect a defective area or an unrecorded area of the reproduced signal.

The output c of the DC correction circuit 2 is the signal interpolation circuit 3
Is input to the control signal g from the signal interpolation control circuit 13 and the average potential is equal to the reference potential Vr in the unrecorded area before the reproduction area or in the reproduction area and the relatively long defective signal area. Replace with. In the output signal h of the signal interpolation circuit 3, the output c of the DC correction circuit 2 is VFO.
Since the average potential of the interpolation signal d is equal to the reference potential Vr, it is a signal centered on the reference potential Vr, so that a signal with a very small fluctuation in the DC potential is input to the gain control amplifier 4.

The interpolation signal d is a signal with a duty of 50% and its frequency is equivalent to that of the reproduced signal. For example, it is a signal obtained by dividing the frequency synchronization signal of the PLL, and this makes it possible to simplify the configuration of the signal reproducing circuit without using an oscillator for an interpolation signal, and to mount it on a single-chip LSI.

The gain control amplifier 4 is a VFO control circuit 12
The automatic gain control amplifier is controlled by the control signal e from the signal interpolation control circuit 13 and detects the signal levels of the VFO section and the interpolation signal section to control the amplitude of the VFO section to be constant. This suppresses the signal amplitude fluctuation between sectors, resulting in a signal i having an amplitude of a substantially constant level,
After that, the low-frequency noise is removed by the HPF 5 to obtain a signal h, which is input to the quantization feedback circuit 6.

The quantized feedback circuit 6 compensates for low frequency cutoff in the HPF 5. FIG. 6 shows an example of the quantization feedback circuit 6. The output k of the quantization feedback circuit 6 is binarized by the waveform shaping circuit 22 using the bias potential Vb of the HPF 5 as a slice level, and the binarized signal is subjected to frequency conversion of the HPF 5 to obtain a low-pass filter (hereinafter referred to as LPF). ) 2
At 2, the low frequency component s is extracted. Then, the low frequency component s is fed back by the subtracter 24 so as to be subtracted from the input j of the quantization feedback circuit 6, so that the low frequency cutoff lost in the HPF 5 is compensated. The output of the quantization feedback circuit 6 has a very small DC fluctuation, and there is no amplitude fluctuation between sectors, and becomes a reproduction signal k from which low-frequency noise is removed, and can be binarized at a constant slice level. However, depending on the control performance of each circuit, there is a case in which a certain slice level is not always appropriate between sectors.

Therefore, the slice level control circuit 7 controls the V
Controlled by a control signal g from the FO control circuit 12,
The VFO unit detects an appropriate slice level 1 for each sector, and the waveform shaping circuit 8 performs binarization for demodulating a reproduced signal.

The operation of the VFO control circuit 12 will be described in detail. Basically, it is controlled by the VFO gate that is active in the VFO area, but the defect detection signal from the defect detection circuit 10 and the RAW from the system controller are controlled.
Limited by the gate. The RAW gate represents a reproduction period for RAW Read After Write that confirms the recording state immediately after recording the recording signal. The defect detection circuit 10 detects a defect in the reproduction signal when the pulse period or pulse width of the binarized signal from the waveform shaping circuit 9 is out of a predetermined range, and outputs a defect detection signal.

FIG. 9 is a block diagram showing an example of the defect detection circuit 10. The binarized signal from the waveform shaping circuit 9 becomes a signal synchronized by the latch 51 using a clock proportional to the recording signal frequency. Also, a signal is generated by delaying it by the number of the clocks n by the DL 52 formed of a shift register. The delayed signal and the synchronized signal are compared and calculated by the arithmetic circuit 53 to detect a defect. The defect detection circuit 10 considers that the pulse width of the synchronized signal becomes a defect when the pulse width exceeds a predetermined width, the arithmetic circuit 53 operates like a retriggerable monoslave multivibrator, and the synchronized signal corresponds to n clocks. When the state does not change until after the delay, the defect detection signal is output. If a signal for PLL synchronization is used as the clock, a uniform defect detection operation can be performed on the inner and outer circumferences even for a recording medium of the ZCAV system in which the recording frequency changes on the inner and outer circumferences.

If there is a signal defect in the VFO area, the DC correction circuit 2, the gain control amplifier 4, and the slice level control circuit 7 malfunction in the defective portion, and proper control cannot be performed. Therefore, each control operation is stopped by a defect detection signal that detects a signal defect, and a malfunction due to a signal defect is prevented. However, in the case of a sector having a recording medium defect in the VFO area originally, the defect becomes large due to aged deterioration, and even if preventive measures are taken over time, malfunction cannot be suppressed sufficiently and demodulation of a reproduction signal may not be possible. Therefore, at the time of RAW processing, R
The above-mentioned preventive measures by the defect detection signal are prohibited by the AW gate, and the sector having the recording medium defect in the VFO area originally is recognized as a defective sector because the reproduction signal cannot be demodulated, and is recorded again in the alternate sector. To do.

The waveform shaping circuit 9 may limit the band of the input signal or control the slice level according to the level of the input signal so that the defect can be detected well.

In FIG. 1, the DC correction circuit 2, the gain control amplifier 4, and the slice level control circuit 7 are controlled by the same control signal from the VFO section control circuit 12, but they are control signals of different timings. I don't care. Each of the DC correction circuit 2, the gain control amplifier 4, and the slice level control circuit 7 has a response time, and during the transient response of the means of the preceding stage, the means of the latter stage is not an appropriate signal, so that it does not operate normally. Therefore, it is possible to perform better control by using a control signal in which the timing of activation of the latter stage is the same as that of the former stage or delayed.

In the magneto-optical disk device, VF
The O section control circuit 12 controls the VFO section of each of the address signal section and the data signal section. As described above, the address signal portion and the data signal portion are recorded by different methods, and the signal reading method from the disc is also different, and since the signals have no correlation with each other, they are the reference VFO.
Parts are provided, and it is necessary to control each independently.

The operation of the signal interpolation control circuit 13 will be described in detail. Not only the unrecorded area but also the area where the reproduced signal is not demodulated even in the recorded area are replaced with the interpolated signal to suppress the DC fluctuation as much as possible. This signal interpolation operation is basically controlled by the read gate e from the system controller 14.

In particular, the following two cases are special notes and will be described clearly. In the area pre-formatted on the recording medium, the read gate e is not activated and is not replaced with the interpolation signal. This is because the reproduction signal in the pre-formatted area includes address information of each sector and the like, which is always required by the system controller 14. Next, when recording / erasing and reproducing are not performed at the same time, the read gate e becomes active during the recording / erasing period and is replaced with the interpolation signal. This is because a normal reproduction signal cannot be obtained during recording and erasing.

Even when the read gate e, which is the signal reproduction area, is in the negative state, if the defect detection circuit 10 and the defect detection circuit 11 detect the unrecorded area and the relatively long defective signal area in the reproduction area, the defect detection is performed. The defect detection signal f of the circuit 10 and the defect detection circuit 11 is replaced with the interpolation signal d. This is to prevent malfunction of the quantization feedback circuit 6. H in the unrecorded area and the relatively long defective signal area
A large DC fluctuation occurs at the output of PF5. The quantized feedback circuit 6 suppresses this DC fluctuation. In the relatively long defective signal area, the quantized feedback 6 circuit generates a signal to be fed back to the quantized feedback 6 circuit, although the amplitude of the input signal is not uniform. Since the output amplitude of the waveform shaping circuit 22 is constant, an appropriate feedback amount cannot be obtained, and DC fluctuation cannot be suppressed completely. The unrecorded area in the playback area is a buffer area between sectors, a gap area between the preformatted area and the data area, and an area where recording is interrupted for some reason during recording. Quantity and LPF23 and HPF
If there is a characteristic disagreement of 5, it cannot be suppressed completely. Therefore, to prevent DC fluctuations in the HPF5 as much as possible,
It is necessary to replace the unrecorded area and the relatively long defective signal area in the reproduction area with the interpolation signal.

The defect detection circuit 10 operates as described above,
A relatively short defective area is also detected, but the HPF is detected in that area.
Since the DC fluctuation at 5 is extremely small, it is not necessary to replace it with an interpolation signal. Therefore, it is necessary to limit the defect width to be detected so that the short defect area is ignored. The size of the width is determined by the balance between the time constant of the HPF 5 and the width that can be restored by error correction.

The defect detection circuit 11 detects a defective area from the amplitude fluctuation of the reproduction signal, and is effective for detection when the reproduction signal amplitude is lowered for a relatively long time due to a scratch or dust on the disk surface of the optical disk. is there. Since such a signal defect has a signal component, the defect detection 10 may cause an omission of detection. Therefore, the defect detection circuit 11
Is also useful for defect detection.

FIG. 10 shows a block diagram of the defect detection circuit 11. It has upper envelope detection circuits 41 and 42 and lower envelope detection circuits 43 and 44 that detect the upper and lower envelopes of the reproduction signal. The upper envelope detecting circuit 41 and the lower envelope detecting circuit 43 are circuits with a short time constant and relatively high responsiveness, and respond to the waveform fluctuation of the defective portion, and the upper envelope detecting circuit 42 and the lower envelope detecting circuit 44 are It is a circuit with a long time constant and relatively slow response, and it is difficult to respond to the waveform fluctuation of the defective portion. The outputs of the upper envelope detection circuit 42 and the lower envelope detection circuit 44 are input to shift registers 45 and 46, respectively, and the upper envelope detection circuit 42 is input.
The output shifts in the negative direction and the output in the lower envelope detection circuit 44 shifts in the positive direction, and the upper envelope detection circuit 41 and the lower envelope detection circuit 4 shift.
3 and the comparison circuits 47 and 48 are used for comparison, and the upper envelope detection circuit 42 is higher than the output of the upper envelope detection circuit 41.
When the output of the lower envelope detection circuit 44 has a lower potential than the output of the lower envelope detection circuit 43, it is determined as a defect, and the OR of each of them is taken by OR49. This is the defect detection signal.

Incidentally, only one of the defect detection circuit 10 and the defect detection circuit 11 may be used to detect the unrecorded area and the relatively long defective signal area in the reproduction area.

Since the phase of the area replaced with the interpolation signal is different from the phase of the reproduction signal, the phase synchronization of the PLL is deviated, and even if it becomes the reproduction signal area again, it takes time for the phase synchronization to coincide with each other and the error increases. Therefore, the PLL does not operate in the area replaced with the interpolation signal, and the state immediately before replacement is maintained. As an example of the method, a PLL VC
Some hold the voltage for controlling the oscillation frequency of O at the voltage immediately before replacement.

FIG. 7 shows a second embodiment of the present invention and is a block diagram of a signal reproducing circuit for carrying out the signal reproducing method of the present invention. Those having the same numbers as in FIG. 1 operate in the same manner, so only the parts different from FIG. 1 will be described. In this embodiment, the signal interpolation operation is performed in two stages. The signal interpolation circuit 3 is controlled by the read gate e to replace the output c of the DC correction circuit 2 with the interpolation signal d. The gain control amplifier 4 is controlled only by the VFO control circuit 12. In this case, the amplitude of the signal interpolator is not constant and the quantization feedback circuit 6 malfunctions. Therefore, the signal interpolator 36 is provided between the gain control amplifier 4 and the HPF 5, and the interpolated signal area is set by the signal interpolator control circuit 13. By replacing the interpolation signal with a constant amplitude again, the amplitude of the interpolation signal input to the quantization feedback circuit 6 is kept constant. The detection of the unrecorded area and the relatively long defective signal area in the reproduction area is performed by the defect detection circuit 11 by the output signal i of the gain control amplifier 4 and replaced by the interpolation signal by the signal interpolation circuit 36. This is because the quantization feedback circuit 6 malfunctions due to the unrecorded area and the relatively long defective signal area in the reproduction area. If signal interpolation is performed before the input, there is no problem. This is because the detection of a relatively long defective signal region can be performed better by making the amplitude of the reproduced signal constant by the gain control amplifier 4.

FIG. 8 is a schematic block diagram of an optical disk reproducing apparatus using the present invention. The spindle motor 26 rotates the optical disc medium 25. The optical pickup 28 moves to a region on the rotated optical disc 25 in which desired information is written, and irradiates a laser beam 29 to read recorded information. The read information is amplified by the RF amplifier, and is sent as a reproduction signal to the reproduction signal binarization processing circuit 31 for carrying out the signal reproduction method of the present invention to become a binarization signal, and the PLL 3
Generate a clock that is phase-synchronized in 3 and compare the clock with the binarized signal.
1 "OR" 0 "determination is performed, source information recorded by the demodulation circuit 34 is obtained and sent to the system controller 35. The system controller 35, the spindle motor 26, the servo circuit 27 for driving the optical pickup 28, and the reproduction signal two. The digitization processing circuit 31 is controlled.

[0043]

As described above, according to the present invention,
By replacing the reproduced signal having the fluctuation of the low frequency component with another signal in the areas other than the demodulation area, the unrecorded portion and the relatively long defective signal area, even if the fluctuation of the low frequency component is removed by the HPF, the signal at the same slice level is obtained. Binarization is possible, and signals can be discriminated stably.

[Brief description of drawings]

FIG. 1 is a block diagram of a signal reproducing circuit showing a first embodiment of the present invention.

FIG. 2 is an operation explanatory diagram of FIG.

FIG. 3 is a block diagram showing a conventional signal reproduction method.

FIG. 4 is an operation explanatory diagram of FIG.

FIG. 5 is a block diagram and operation explanatory diagram of a DC correction circuit 2.

FIG. 6 is a block diagram and operation explanatory diagram of a quantization feedback circuit 6.

FIG. 7 is a block diagram of a signal reproducing circuit showing a second embodiment of the present invention.

FIG. 8 is a schematic block diagram of an optical disk device according to the present invention.

FIG. 9 is a block diagram of the defect detection circuit 10.

FIG. 10 is a block diagram of the defect detection circuit 10.

[Explanation of symbols]

 2 DC correction circuit 3 Signal interpolation circuit 4 Gain control amplifier 5 HPF 6 Quantization feedback circuit 7 Slice level control circuit 8 Waveform shaping circuit 10 Defect detection circuit 11 Defect detection circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masanori Matsuzaki Inventor Masanori Matsuzaki, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Within Hitachi Imaging Information Systems Co., Ltd. Factory Storage Systems Division

Claims (2)

[Claims] 1. A reproduction signal obtained from a recording medium in which a recording signal having information at an edge position is recorded by mark length recording is detected from a specific pattern portion of the recording medium except during a period in which the recording signal is reproduced. Interpolating by replacing the potential with a signal set to be an average potential, and binarizing the interpolated reproduction signal at a slice level automatically set by the potential detected from a specific pattern portion of the recording medium. And a method for reproducing a signal from a recording medium. 2. The signal reproducing method for a recording medium according to claim 1, wherein the replacement signal has a duty of 50% and its frequency is equal to the frequency of the reproduction signal.