JPH09167805A - Mask rom and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the degree of integration of a mask ROM. SOLUTION: Transistor cells comprised in a mask ROM comprises a common source line 30 formed on the base of a groove 16, word lines 20A consisting of gate electrodes formed on the side walls of the groove 16, and drain regions 22 formed on the upside of a protrusion sandwiched between the grooves 16. The drain regions 22 are separated from each other in the direction of the groove 16, and the source line 30 is made to extend in the direction of the groove 16 due to the structure of the groove 16 deeper than an element isolation region 12. The mask ROM is programmed depending on whether it is connected to a bit line 36 through the intermediary of a contact hole 38 or not. The mask ROM can be also programmed by adjustment of the transistor cells in Vt H. A gate electrode is formed on the side wall of a groove, whereby a channel can be set vertical to the surface of a substrate, and the mask ROM can be enhanced in degree of integration. Gate lines 20A located on both the sides of a protrusion can be connected together in parallel, so that the transistor cells can be enhanced twice as much in driving capacity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask ROM and a method for manufacturing the same, and more specifically, a NAND type or N type.
The present invention relates to a mask ROM particularly suitable for an OR type mask ROM and capable of improving the degree of integration, and a manufacturing method thereof.

[0002]

2. Description of the Related Art A mask ROM is a read-only memory for writing user data in a mask used during a wafer manufacturing process. Each cell of the mask ROM can be composed of one transistor, and its structure is simple, so that high integration is easy, and it has the features of large capacity and low bit cost. Mask R
In the OM, in addition to the improvement in the degree of integration, it is extremely important to shorten the turn around time (TAT) from receiving the data from the user and writing the data to deliver the product.

As a typical structure of the mask ROM, a NOR type cell in which cells are connected in parallel to a bit line and a NAND type cell in which cells are connected in series are known. Conventionally, in any of these types, a transistor is generally formed on a Si substrate in a planar manner.
Therefore, the degree of integration is determined by the resolution of the photoresist used as a mask for processing.

[0004]

SUMMARY OF THE INVENTION A first object of the present invention is to provide a mask ROM capable of improving the degree of integration and a method of manufacturing the same.

A second object of the present invention is to provide a mask ROM capable of shortening the turnaround time and a method for manufacturing the same.

[0006]

In order to achieve the first object, the mask ROM of the present invention is a mask RO having a plurality of transistor cells arranged in an array on the main surface of a semiconductor substrate.
M, a plurality of grooves extending parallel to each other on the main surface are provided, and each transistor cell has one of a source and drain region at a bottom of the groove, a gate electrode on a sidewall of the groove, and a groove of the groove. It is characterized in that the convex portion arranged between them has the other of the source and drain regions, respectively.

According to the mask ROM of the present invention, since the gate electrode is formed on the side wall of the groove, the channel of the transistor cell can be arranged in a direction substantially vertical to the substrate surface, so that the transistor cell occupies an area of the substrate. The area can be reduced.

In a preferred aspect of the mask ROM of the present invention, a plurality of element isolation regions extending in a direction orthogonal to the groove and partitioning at least the other of the source and drain regions of the transistor cells formed in the convex portion from each other are formed. Further prepare. In this case, it is easy to separate the transistor cells.

By arranging the source region at the bottom of the groove and making the depth of the groove deeper than that of the element isolation region, the source region can be connected in the groove direction to form a source line. In this case, a NOR type mask ROM can be easily obtained. In this case, the word line can further be configured by connecting gate electrodes arranged on both sides of one convex portion in parallel with each other. In this case, the driving capability of the transistor cell can be improved.

By making the depth of the groove shallower than that of the element isolation region, both the source and drain regions can be isolated by the element isolation region, and each transistor cell can be partially isolated in the groove direction. In this case, a NAND mask ROM in which the transistor cells are connected in series in the direction orthogonal to the groove can be easily obtained.

Further, the method of manufacturing the mask ROM of the present invention is the method of manufacturing the mask ROM of the present invention, in which the transistor cell of the transistor cell is selected depending on whether the bit line extending in the direction orthogonal to the groove is connected to the drain region. It is characterized by executing a program. In this case, the turn around time can be shortened.

Another method of manufacturing the mask ROM of the present invention is the method of manufacturing the mask ROM of the present invention, in which the transistor cells are programmed by adjusting the threshold voltage at the sidewall portion of the groove. It is characterized by In this case, it is possible to manufacture a mask ROM having a high degree of integration.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan pattern diagram showing the structure of a mask ROM according to the first embodiment of the present invention. In the mask ROM of this embodiment, the source line 30 is formed in the groove 16, and each transistor cell is separated by a large number of element isolation regions 12 extending in parallel with the bit line 36. By forming the groove 16, a step is provided between the source line 30 extending in the direction orthogonal to the bit line 36 and the drain region 22 of each transistor cell. A common source line 30 and each drain region 2 constituting a transistor cell
A word line 20 </ b> A formed on the side wall of the groove 16 is provided between the word line 20 and the word line 2.

2 to 4 are sectional views showing the detailed structure of the above-described embodiment and the manufacturing method thereof for each stage of the mask ROM manufacturing process. In these drawings, each of the partial views (a1) to (a11) shows the AA ′ cross section of FIG. 1 sequentially for each step, and each of the partial views (b1)-(b11).
Shows the BB ′ cross section of FIG. 1 sequentially for each step. Each number attached to a and b indicates a process step. The manufacturing procedure of the mask ROM of the present embodiment will be described with reference to these drawings.

First, a plurality of rows of isolation trenches are formed on the silicon (Si) substrate 10 so as to be parallel to the bit lines 36 to be formed later, and an insulator such as SiO ₂ is sputtered therein. Embed. As a result, the element isolation region 12 that isolates the respective element formation regions from each other is formed. Then, a SiO ₂ insulating film 14 is formed on the exposed portion of Si by a thermal oxidation method. As a result, (a1) and (b
The structure shown in 1) is obtained. Subsequently, a large number of vertical grooves 16 extending in a direction orthogonal to the element isolation region 12 are formed by etching (a2, b2). The depth of the vertical groove 16 is formed shallower than the depth of the isolation trench, as shown in the figure. As a result, Si is exposed in the vertical groove 16 in the element forming region, and Si is covered with the insulating film in the vertical groove 16 in the element isolation region 12.

A thermal oxide film 18 to be a gate insulating film later is formed on the entire surface of the exposed portion of Si (a3). Further, a polysilicon film 20 is deposited on the entire surface by a CVD method (a4,
b4), and then etch back this. As a result, the polysilicon film is left only on the sidewalls on both sides of the vertical groove 16 to form the word line 20A extending in the groove direction (FIGS. 3A5 and 3B5). The oxide film at the bottom of the vertical groove 16 is removed (a6), and the Si substrate portion 22 is exposed at the bottom of the groove. Next, the Si substrate portion 22 exposed at the bottom of this groove is etched to form the vertical groove 1 more than the element isolation region 12.
6 is deepened (a7), and a Si exposed region 24 is formed at the bottom. Subsequently, the oxide film 12 at the bottom of the vertical groove 16 of the element isolation region 12 is removed to remove the vertical groove 1 of the element isolation region 12.
A Si exposed region 26 is formed in the substrate 6. As a result, inside the vertical groove 16, the element isolation region 12 disappears and an exposed portion of Si extending in the vertical groove direction is obtained. At the same time, by removing the oxide film on the upper surface other than the inside of the vertical groove 16 in the element formation region,
Si exposed regions 28 are formed on the upper surfaces of the protrusions on both sides of the groove (a
8, b8).

Subsequently, impurities are introduced into both the Si exposed regions 24 and 26 at the bottom of the vertical groove 16 and the Si exposed region 28 at the upper surface of the convex portion. As a result, a source line 30 that constitutes a source region that passes through the element isolation region 12 and is connected in a row is obtained in the Si exposed regions 24 and 26 at the bottom of the groove, and the Si exposed faces of the convex portions on both sides thereof are exposed. In the area 28,
A drain region 32 of each transistor cell, which is isolated from each other by the element isolation region 12, is obtained (FIG. 4 (a9),
(B9)). Further, an insulating film 34 such as BPSG is formed on the entire surface and is flattened by reflow (a10, b10).
Mask ROMs in this state are stocked as semi-finished products.

When there is an order from the user, FIG. 4 (a1)
As shown in 1) and (b11), a finished product is manufactured from a semi-finished product. In this case, a mask is created based on the data supplied by the user, and an opening 38 is formed above the drain region 32 in the cell in which data is written based on the mask.
This opening 38 is formed in a cell in which
Al is sputtered on the entire surface without forming. Al
Are patterned to form the bit line 36, so that the write cell is formed through the contact hole 38.
A NOR type mask ROM connected in parallel with respect to is obtained. The gate electrodes 20A on both sides of one protrusion are connected in parallel to each other to form one word line. Therefore, the word line 20A is separated from the source line 30 and the element isolation region 12 on both sides of the protrusion. The drain region 32 on the upper surface of the raised portion constitutes one transistor cell.

In the mask ROM of this embodiment, since the gate electrode is formed on the side wall portion, the channel of the transistor cell can be arranged in a direction substantially perpendicular to the substrate surface, so that the area occupied by the mask ROM can be reduced. Becomes Further, in the present embodiment, the program is executed at the final stage, so that the TAT for making a semi-finished product into a finished product can be shortened.

In the above-mentioned embodiment, the description was made based on the method of programming depending on the presence or absence of the contact hole. Instead, however, the threshold voltage (V _th ) of the cell transistor is changed by ion implantation of impurities. By adjusting, it is possible to program depending on whether or not the V _th of the transistor cell is raised above the line voltage of the word line. In this case, in the state shown in a3 and b3 of FIG. 2, the V _{th of} each cell is selected based on the data to be written by implanting impurities for V _th adjustment from the upper portions of the oxide films 14 and 18. .

FIG. 5 is a plan view showing the pattern of the mask ROM according to the second embodiment of the present invention. The difference from the embodiment of FIG. 1 is that no contact hole is formed in FIG. 5 because the ROM is programmed by controlling the threshold voltage (V _th ).
Further, FIGS. 6 and 7 show the manufacturing method of this embodiment in the same manner as FIGS. 2 to 4. In this manufacturing method, NA
An ND type mask ROM is manufactured.

First, as shown in FIG. 6 (b1), a bit line 56 to be formed later on the silicon (Si) substrate 40.
Multiple rows of isolation trenches are formed so that they are parallel to
An insulator such as SiO _{2 is} embedded in the inside by a CVD method or the like. As a result, the element isolation region 42 that isolates the element formation regions from each other is formed. Subsequently, a vertical groove 44 extending in a direction orthogonal to the element isolation region 42 is formed by etching (a2, b2). The depth of the vertical groove 44 is formed shallower than the depth of the isolation trench, as shown in the figure. As a result, Si is exposed in the element formation region and the element isolation region 12
Then Si is covered with an insulating film.

A thermal oxide film 46, which will later become a gate insulating film, is formed on the entire surface of the exposed portion of Si (a3). Then V
Impurity implantation for _th adjustment is performed. This state will be described with reference to FIG. The transistor cell includes a source formed on the bottom of the vertical groove 60, a gate electrode formed on the groove side wall 62, and a drain formed on the upper surface of the convex portion 64 on both sides of the vertical groove 60. Here, in each element formation region sandwiched by the element isolation regions, two cells are formed per column of the vertical groove 60. Here, an example will be described in which impurities are injected into the three cells 66 shown in FIG. 7A to adjust V _th , and programming is performed.

First, a groove 60A in which V _th adjusting implantation is performed on both side wall portions of the vertical groove 60, a groove (not shown) in which V _th adjusting implantation is performed on the left side wall portion of the groove in the drawing, and A photoresist layer 68 having an opening is formed in a half portion of the upper surface of the convex portion 64 adjacent to these grooves on the side close to the injection groove. Then, ion implantation is performed at an angle of about 60 degrees with respect to the substrate surface by impurity ions 70 that are directed in a direction tilting from right to left in the drawing. As a result, ion implantation for V _th adjustment is performed on the sidewall on the left side of the groove in the drawing and on the open upper surface of the convex portion adjacent thereto.

Next, in the drawing, V is formed on both side wall portions of the groove.
grooves 60A _{which th} adjustment implant is performed, a groove 60B which figures on V _th adjustment injected into the right side walls of the groove is performed, and an opening in the half close to the injection groove of the protrusion upper surface adjacent to the grooves Forming a photoresist layer 72 having Next, ion implantation is performed at an angle of about 60 degrees with respect to the substrate surface by the impurity ions 72 that are inclined in the direction from left to right in the drawing. As a result, V on the right side wall of the groove in the drawing and on the open upper surface of the convex portion adjacent to the side wall
Ion implantation for _th adjustment is performed.

Returning to FIG. 6, when the V _th adjusting ion implantation is completed, a polysilicon film 48 is deposited on the entire surface by a CVD method or the like (a4, b4), and this is etched back to form both sides of the vertical groove 44. The word line 48A forming the gate electrode is formed by leaving the polysilicon film only on the side wall of the (FIG. 7 (a5), (b5)). Next, ion implantation for forming a diffusion layer is performed from the direction perpendicular to the substrate surface through the oxide films 46 on the bottoms of the grooves and the upper surfaces of the projections. As a result, the source or drain region 5 is formed at the bottom of each vertical groove 44.
0, the drain or source region 52 is formed on the upper surface of the convex portion on both sides thereof. Furthermore, an insulating film 5 such as BPSG is formed on the entire surface.
8 is formed and flattened by reflow (a7, b
7).

After forming an opening in the drain region of each of, for example, eight transistor cells in a row parallel to the element isolation region 12, Al is sputtered on the entire surface of the BPSG film 58, and this is patterned to form a bit line. 56 is formed. As a result, 8
NAN with a structure in which individual transistor cells are connected in series
The D-type mask ROM is completed. By arranging the word lines forming the gate electrodes on the sidewalls of the vertical grooves, as in the first embodiment, the channels can be arranged substantially in the direction perpendicular to the substrate surface, so that the occupied area can be reduced. .
Further, in the present embodiment, each gate electrode independently constitutes a word line, so that the integration degree is further doubled as compared with the previous embodiment.

Although the present invention has been described above based on its preferred embodiments, the mask ROM and its manufacturing method of the present invention are not limited to the configurations of the above-mentioned embodiments, but the above-mentioned embodiments. A mask ROM in which various modifications and changes are made from the configuration of the embodiment and a manufacturing method thereof are also included in the scope of the present invention.

For example, tungsten polycide can be adopted instead of the polysilicon film forming the gate line.

The structure of the gate electrode formed on the side wall of the groove adopted in the present invention is applicable not only to the mask ROM but also to the reduction of the occupied area of other semiconductor devices.

[0032]

As described above, the mask R of the present invention is used.
According to the mask ROM manufactured by the OM and the method of the present invention, the degree of integration per substrate area is improved by adopting the gate electrode having the sidewall structure. Therefore, the present invention is a mask ROM particularly suitable for increasing the capacity and a method of manufacturing the same. Has a remarkable effect.

[Brief description of the drawings]

FIG. 1 is a plan pattern view of a mask ROM according to a first embodiment of the present invention.

2 (a1) to (a4) and (b1) to (b4)
2A and 2B are cross-sectional views taken along the lines AA 'and BB' of FIG. 1 at respective manufacturing process stages of the mask ROM of FIG.

3 (a5) to (a8) and (b5) to (b8).
2A and 2B are cross-sectional views taken along the lines AA 'and BB' of FIG. 1 at respective manufacturing process stages of the mask ROM of FIG.

4 (a9) to (a11) and (b9) to (b1)
1) are cross-sectional views taken along the lines AA 'and BB' of FIG. 1 at respective manufacturing process steps of the mask ROM of FIG.

FIG. 5 is a plan pattern view of a mask ROM according to a second embodiment of the present invention.

6 (a1) to (a4) and (b1) to (b4)
FIGS. 6A and 6B are cross-sectional views taken along the lines AA ′ and BB ′ of FIG. 5 at respective manufacturing process stages of the mask ROM of FIG.

7 (a5) to (a8) and (b5) to (b8).
FIGS. 6A and 6B are cross-sectional views taken along the lines AA ′ and BB ′ of FIG. 5 at respective manufacturing process stages of the mask ROM of FIG.

8A to 8C are cross-sectional views for explaining the programming in the mask ROM of FIG. 5, respectively.

[Explanation of symbols]

 10, 40 Substrate 12, 42 Isolation region 14 Oxide film 16, 44 Vertical groove 18, 46 Gate oxide film 20, 48 Polysilicon 20A, 48A Gate electrode 22 Si exposed portion of groove bottom 24 Si exposed region of groove bottom 26 Element isolation Area Si exposed area 28 Si exposed area on convex upper surface 30 Source line 50 Source area 32, 52 Drain area 34, 54 PSG film 36, 56 Bit line

Claims (9)

[Claims] 1. A mask ROM having a plurality of transistor cells arranged in an array on a main surface of a semiconductor substrate, wherein a plurality of grooves extending in parallel to each other are provided on the main surface, and each transistor cell has a plurality of grooves. A mask ROM having one of a source region and a drain region at the bottom, a gate electrode on the side wall of the groove, and the other of the source region and the drain region at a convex portion arranged between the grooves. 2. The device further comprises a plurality of element isolation regions extending in a direction perpendicular to the groove, the element isolation regions partitioning the other of the source and drain regions of the transistor cell from each other. Mask RO described in 1.
M. 3. A source region is located at the bottom of the trench,
3. The mask ROM according to claim 2, wherein the source region extends in the direction of the groove beyond the element isolation region to form a source line. 4. The mask ROM according to claim 3, wherein the gate electrodes arranged on both sides of one convex portion are connected in parallel to each other to form a word line. 5. The mask ROM according to claim 3, wherein the groove is formed deeper than the element isolation region. 6. The mask ROM according to claim 2, wherein the one of the source and drain regions is isolated by the element isolation region. 7. The mask R according to claim 6, wherein the groove is formed shallower than the element isolation region.
OM. 8. The method of manufacturing a mask ROM according to claim 1, wherein the transistor cell is formed according to whether or not a bit line extending in a direction orthogonal to the groove is connected to the drain region. A method for manufacturing a mask ROM, which is characterized by performing a program. 9. A method of manufacturing a mask ROM according to claim 1, wherein the threshold voltage at the sidewall portion of the groove is adjusted.
A method of manufacturing a mask ROM, which comprises programming a transistor cell.