JPH09167060A - Signal processor for disk reproduction - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce circuit scale by a minimum storage circuit, to always execute stable error detecting and correcting processing regardless of reproducing speed of CD and to reduce power consumption. SOLUTION: This device is provided with an error detecting and correcting circuit 5 and a RAM 4 for storing regenerative data and error correction data and corresponding to a reproducing clock correspondent to the reproducing speed of CD, the write of regenerative data into the RAM 4 and the read of error correction data out of the RAM 4 are performed. Further, each time the regenerative data for one frame are stored in the RAM 4, a storage end flag FF is set, the error detecting and correcting operation is started corresponding to the detection of this flag FF, an error detecting and correcting sequencer is operated by a reference clock CL in a fixed cycle and until the storage of regenerative data for next one frame is detected by the storage end flag FF after the completion of error detecting and correcting processing, the supply of reference clock to the sequencer is stopped.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing apparatus for an optical disc such as a CD, and more particularly to a signal processing apparatus having an error detecting / correcting function.

[0002]

2. Description of the Related Art In an apparatus for reproducing an optical disk such as a CD, the reproduced data is once written in a storage circuit such as a RAM, the data is read out and an error detection and correction process is performed, and the corrected data and the error flag are described above. The memory circuit is written again, and the corrected data and error flag are read from this memory circuit at the time of output.

Conventionally, two techniques have been used as this type of signal processing device. First, the first technology is based on the reproduction clock corresponding to the reproduction speed of the CD,
It writes the reproduced data to the storage circuit, and performs error detection and correction processing and reads the corrected data and error flag from the storage circuit based on the reference clock of a fixed cycle from the crystal oscillator, etc. The fluctuation was absorbed by the memory circuit. The second technique is to write reproduction data to a storage circuit, perform error detection / correction processing, and read correction data and an error flag from the storage circuit based on a reproduction clock, and synchronize with fluctuations in reproduction speed. I was trying to do all the processing.

[0004]

In the first conventional technique, as shown in FIG. 3A, although the reproduction data storage period of one frame changes in synchronization with the reproduction speed of the CD, error correction processing and As shown in FIGS. 3A and 3B, the correction data is always read at a constant cycle. Therefore, in order to absorb the difference between the data writing speed and the data reading speed, a memory having a capacity larger than that required for error detection and correction is stored. Circuitry is required, thus increasing the scale of the device.

Further, in the second technique, the
As shown in (a) and (c), the reproduction data storage cycle of one frame, the error correction processing cycle, and the correction data read cycle all change in synchronization with the reproduction speed of the CD. However, when the disc with large eccentricity is reproduced, when a scratch passes, and immediately after the track jump, the reproduction clock cycle becomes unstable, and as a result, the error detection and correction sequence is adversely affected and accurate error detection and correction processing is performed. Can not.

Further, conventionally, even if there is no error data in one frame, the sequencer for error detection and correction always continues to operate. Especially, in the above-mentioned first technique, the reproduction speed of the CD is low. Even if there is, the sequencer operates with a high-speed clock, so there was a problem that the maximum power was always consumed.

[0007]

According to the present invention, there is provided a clock reproduction circuit for generating a reproduction clock corresponding to a reproduction speed of a disc, an error detection / correction circuit for detecting and correcting an error in reproduction data, and the reproduction data. A storage circuit for storing data after error correction; a read / write control circuit for controlling writing of the reproduction data into the storage circuit and reading of the data after the error correction according to the reproduction clock; A storage detection circuit that detects that one frame of reproduced data has been stored, and a sequencer that operates with a reference clock of a fixed cycle and starts the sequence control of the error correction circuit in response to the detection output of the storage detection circuit. , After the completion of error detection and correction processing, until the storage of the next one frame of reproduction data is detected by the storage detection circuit,
And a clock stop circuit for stopping the supply of the reference clock to the sequencer.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of the present invention, in which 1 is a clock reproduction circuit for generating a reproduction clock SCL corresponding to a reproduction speed from an EFM signal reproduced from a CD, and 2 is a clock reproduction circuit. An EFM signal is input and an EFM signal is demodulated based on the reproduction clock SCL to output demodulated data in 8-bit units, and at the same time, an EFM decoder 3 that outputs a signal EFMEN indicating that the demodulated data is 8 bits is a crystal vibration. A reference oscillator for connecting a child and outputting a reference clock CL having a constant cycle, 4 is an EFM decoder 2
RAM for storing demodulated data output from the RAM 5, 5 is composed of a syndrome calculator 51 and an error detection / correction arithmetic unit 52, and performs an error detection / correction circuit for performing error detection / correction processing on the demodulation data read from the RAM 4, and 6 is an error detection / correction processing. A sequencer for performing sequence control of 7), a read / write control circuit 7 for controlling writing and reading of data to and from the RAM, and a counter 8 for counting the signal EFMEN to detect that one frame of data is stored in the RAM 4. , Set storage end flag FF 1
It is a frame data storage end detection circuit.

The error detection / correction sequencer 6 performs sequence control based on the reference clock CL regardless of the reproduction clock SCL, and starts and starts error detection / correction processing when the storage end flag FF is set. rear,
A reset signal RST for resetting the storage end flag FF is generated. Further, when the storage end flag FF is set, an H level control signal CTL is output, and when the error detection and correction process is completed, this signal CTL is output.
To L level. The control signal CTL and the storage end flag FF are input to the OR gate 9, the output of the OR gate 9 is input to the AND gate 10 to which the reference clock CL is applied, and the reference clock CL is error-detected and corrected via the AND gate 10. It is supplied to the sequencer 6. That is, the OR gate 9 and the AND gate 10 form a clock stop circuit.

The error detection / correction sequencer 6 uses the RA
To read the demodulated data from M4 or write the demodulated data, the corrected data and the error flag in RAM4,
A read request RREQ and a write request WREQ are issued to the read / write control circuit 7. The read / write control circuit 7 has a reference clock CL, a reproduction clock SCL, and a signal E.
FMEN, read request RREQ, and write request WREQ
When writing the demodulated data to the RAM 4 and reading the corrected data and the error flag from the RAM 4, the error detection and correction circuit performs writing and reading in synchronization with the reproduction speed of the CD based on the reproduction clock SCL. Writing and reading between the RAM 5 and the RAM 4 are performed in synchronization with the reference clock CL.

The operation of this embodiment will be described in detail below with reference to FIG. The reproduced EFM signal is EFM
The signal EFMEN is output when the data input to the decoder 2 and demodulated on the basis of the reproduction clock SCL has 8 bits. That is, this signal EFMEN is output every eight reproduced clocks. Since the read / write control circuit 7 gives a control signal and an address for writing to the RAM 4 each time the signal EFMEN is output, the 8-bit unit demodulated data from the EFM decoder 2 is sequentially stored in the RAM.
4 will be written. Meanwhile, the signal EFMEN
Is counted by the one-frame data storage end detection circuit 8, and when the count value reaches one frame, the storage end flag FF is set as shown in FIG.

2A shows the storage cycle of the demodulated data for one frame as in FIGS. 3 and 4. This cycle is synchronized with the reproduction speed of the CD, and the storage end flag FF of FIG.
Matches the cycle of. When the storage end flag FF is set, the output of the OR gate 9 becomes the H level, so AND
The reference clock CL is supplied to the error detection / correction sequencer 6 via the gate 10, and the error detection / correction sequencer 6 performs sequence control based on the reference clock CL in response to the storage end flag FF being set. The error detection / correction circuit 5 starts the error detection / correction process. Further, when the error detection / correction sequencer 6 detects that the storage end flag FF is set, it sends the reset signal RST to the one-frame data storage end detection circuit 8, whereby the storage end flag FF is set.
Is reset. However, the storage end flag FF
Since the control signal CTL becomes H level in response to the setting, the H level signal is continuously applied to the AND gate 10 even if the storage end flag FF is reset, and the reference clock CL is used as the error detection / correction sequencer 6 Will continue to be supplied to.

In accordance with the start of the sequence control, in the error detection / correction circuit 5, first, the syndrome calculator 51.
Then, the demodulated data for one frame is read from the RAM 4 and the syndrome is calculated here. Then, the syndrome and the C1 and C2 flags are set to the error detection and correction calculator 52.
And the C1 and C2 flags are also input to the error detection and correction sequencer 6. Error detection and correction sequencer 6
Reads the demodulated data from the RAM 4 according to these flags and operates the error detection / correction calculator 52 to perform error correction processing. Then, the corrected data and the error flag are written in the RAM 4. Since such an error detection / correction process is executed based on the reference clock CL, the CD
Even if the reproduction speed of F changes, the processing is always advanced in a constant sequence, and accurate error detection and correction processing is executed. As shown in FIG. 2C, the error detection / correction period will be completed within a substantially constant period although there are some changes depending on the processing contents.

When the error detection / correction processing for the demodulated data of one frame is completed, the error detection / correction sequencer 6 sets the control signal CTL to the L level, so that the output of the OR gate 9 becomes the L level and the AND gate 10 performs the error detection / correction. The supply of the reference clock CL to the sequencer 6 will be stopped. That is, as indicated by the diagonal lines in FIG. 3C, the reference clock CL is set until the storage end flag FF is set by storing the reproduced data of the next frame for one frame after the error detection and correction process is completed. Supply is stopped.

The read / write control circuit 7 counts the reproduction clock SCL and supplies a control signal and an address for reading to the RAM 4 every time when it reaches a predetermined value, so that it is synchronized with the reproduction clock, that is, the reproduction speed of the CD. At the same time, as shown in FIG. 2D, the correction data and the error flag are read. Therefore, as is clear from FIGS. 2A and 2D, writing demodulated data to the RAM 4 and the RAM 4
The reading of the correction data from is performed synchronously. Therefore, it is not necessary for the RAM 4 to absorb the fluctuation of the reproduction speed of the CD, and the minimum storage capacity is required.

[0016]

According to the present invention, since the minimum storage circuit can be used, the circuit scale can be reduced, and the error detection / correction processing is performed based on the clock of a constant cycle that is not affected by the reproduction speed of the CD, and therefore, the error detection and correction processing is always performed. Stable error detection and correction processing can be executed. Further, even if the reference clock is made high in order to increase the reproduction speed of the CD, the supply of the reference clock to the sequencer is stopped after the error detection / correction processing is completed, so that the power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of the first conventional technique.

FIG. 4 is a timing chart for explaining the operation of the second conventional technique.

[Explanation of symbols]

 1 clock reproduction circuit 2 EFM decoder 3 reference oscillator 4 RAM 5 error detection / correction circuit 6 error detection / correction sequencer 7 read / write control circuit 8 1 frame data storage end detection circuit 51 syndrome calculator 52 error detection / correction calculator

Claims (1)

[Claims] 1. A clock reproduction circuit for generating a reproduction clock corresponding to a reproduction speed of a disk, an error detection / correction circuit for detecting and correcting an error in reproduction data, and the reproduction data and the data after the error correction are stored. A storage circuit, a read / write control circuit for controlling the writing of the reproduction data to the storage circuit and the reading of the data after the error correction according to the reproduction clock, and the reproduction data for one frame is stored in the storage circuit. A storage detection circuit that detects that the error detection and correction processing has been completed, a sequencer that operates with a reference clock of a fixed cycle and that starts the sequence control of the error correction circuit in response to the detection output of the storage detection circuit, and after completion of error detection and correction processing. Stop the supply of the reference clock to the sequencer until the storage detection circuit detects the storage of the next one frame of reproduction data. And a clock stop circuit for controlling the disk reproduction signal processing device.