JPH09160891A - Multiprocessor interruption control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To distribute an interruption load equally to respective processors fast by making an I/O device control means control the transmission of an interruption request to a processor having the lightest interruption load according to the contents of a transaction. SOLUTION: This system is provided with processor control circuits 200-1 to 200-4 corresponding to processors 100-1 to 100-4 and I/O device control circuits 300-1 and 300-2 which accept interruptions from plural I/O devices 500-1 to 500-6 through interruption lines 600-1 and 600-2. Processor control circuits 200-1 to 200-4 inform the I/O device control circuits 300-1 and 300-2 of the interruption loads of the corresponding processors and the I/O device control circuits 300-1 and 300-2 controls the transmission of the interruption request to the processor having the lightest interruption load according to the contents of the transaction.

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor interrupt control system connected by a shared bus, and more particularly to a multiprocessor interrupt control system capable of uniformly distributing loads to each processor.

[0001]

2. Description of the Related Art Conventionally, in this type of technology, an input / output (hereinafter referred to as "I / O") control unit that issues an interrupt notifies an interrupt to a processor that is uniquely set in advance corresponding to the interrupt factor. Was. In this case, depending on the setting, the interrupt load may be concentrated on a specific processor, which makes it difficult to uniformly distribute the load.

Therefore, a method has been adopted in which the load of interrupts is distributed by making individual judgments by each processor rather than setting the processors that accept interrupts in advance. For example, in Japanese Unexamined Patent Publication No. 2-82343, the processors monitor each other's load states through an interrupt-dedicated bus, and even if a heavily loaded processor receives an interrupt, the lightly loaded processor instead accepts the interrupt. A technique capable of achieving load balancing is described. Further, a technique is described in which a signal line indicating a life or death state of a processor is added to detect the presence of a faulty processor, and instead, another processor can accept an interrupt from an I / O device. There is.

[0003]

In the above-mentioned prior art,
When the number of I / O devices and the number of processors increase as the system becomes larger, the number of interrupt-dedicated buses increases in proportion to this. As a result, the arbitration control for interrupt acceptance between the processors becomes complicated, and there is a problem that the response becomes slow. In addition, there is a problem that if the fault tolerance is increased, the number of signal lines is further increased and the amount of hardware is increased.

An object of the present invention is to realize a multiprocessor interrupt control system which realizes uniform interrupt load distribution to each processor at high speed.

Another object of the present invention is to realize a multiprocessor interrupt control system which prevents an increase in the amount of hardware associated with an increase in system scale.

[0006]

In order to solve the above problems, a multiprocessor interrupt control system of the present invention comprises:
A multiprocessor interrupt control system for distributing interrupt requests from a plurality of I / O devices to a plurality of processors via interrupt lines, the processor control means being associated with each of the plurality of processors,
I / O device control means for receiving an interrupt from each of the plurality of I / O devices via the interrupt line, wherein the processor control means controls the interrupt load of the associated processor by the I / O device control. The I / O device control means includes means for notifying the means, and means for controlling the transmission of an interrupt request to the processor with the smallest interrupt load at present based on the contents of the transaction.

Further, in another multiprocessor interrupt control system of the present invention, the processor control means is an interrupt level register for storing an interrupt level associated with an interrupt factor, and pending during the interrupt level. And a counter that counts the number of interrupts from the I / O device control means and receives the interrupt request from the I / O device control means, and the counter corresponds to the counter from the interrupt level stored in the interrupt level register corresponding to the interrupt factor code included in the request. It includes interrupt reception control means for incrementing the level and interrupt completion issue control means for notifying the I / O device control means of the contents of the counter when the interrupt is completed. Further, in another multiprocessor interrupt control system of the present invention, the processor control means includes an interrupt pending register for storing an interrupt pending number associated with an interrupt factor, contents of the interrupt level register and the interrupt pending. An interrupt request issue control means for determining an interrupt to be sent to the processor based on the contents of the register and controlling the sending is included.

According to another multiprocessor interrupt control system of the present invention, the I / O device control means comprises:
A processor interrupt pending register that stores the number of pending states of each of a plurality of processors according to the interrupt level, and an interrupt completion notification reception control means that accepts the transaction and updates the content of the processor interrupt pending register based on the content of the transaction. Including and

According to another multiprocessor interrupt control system of the present invention, the I / O device control means comprises:
An interrupt priority notification register that stores the ID number of a processor that preferentially notifies an interrupt when the interrupt level obtained from the processor interrupt pending register is equal to all processors, the content of the interrupt priority notification register, and the processor An interrupt issue control means for controlling the transmission of an interrupt request to the processor with the lightest load at present based on the contents of the interrupt pending register.

According to another multiprocessor interrupt control system of the present invention, the I / O device control means comprises:
An interrupt level setting register for storing an interrupt level associated with each of the plurality of interrupt lines, and an interrupt to be accepted from the contents of the interrupt level setting register when accepting an interrupt from each of the plurality of interrupt lines And an interrupt acceptance control means for controlling the interrupt acceptance.

Further, another multiprocessor interrupt control system of the present invention is a multiprocessor interrupt control system which distributes interrupt requests from a plurality of I / O devices to a plurality of processors via interrupt lines. Of the processors of the above, and I / O device control means for accepting an interrupt from an I / O device via an interrupt line, the processor control means being associated with an interrupt factor. An interrupt pending register that stores the number of pending interrupts, an interrupt level register that stores the interrupt level associated with the interrupt factor, a counter that counts the number of pending interrupts according to the interrupt level, and I / O device control means Interrupt request control means for receiving a corresponding interrupt request, and incrementing the corresponding level of the counter from the interrupt factor code contained in the request and the contents of the interrupt level register; and the contents of the interrupt level register and the interrupt pending register. The interrupt request issuance control means for determining an interrupt factor to be sent to the processor based on the contents and the sending control, and the interrupt completion issue control means for issuing a completion transaction including the contents of the counter when the interrupt is completed, The O-device control means includes a processor interrupt pending register that stores the number of pending states of each of the plurality of processors according to the interrupt level, and an interrupt factor setting that stores an interrupt factor code associated with each of the plurality of interrupt lines. And register,
An interrupt level setting register that stores an interrupt level associated with each of a plurality of interrupt lines, and an interrupt priority notification that stores an ID number of a processor that preferentially notifies an interrupt when the interrupt levels of all processors are equal A register, an interrupt issue control means for controlling the transmission of an interrupt request to the currently lightest loaded processor from the contents of the processor interrupt pending register and the contents of the interrupt priority notification register,
Interrupt completion notification reception control means for receiving the end transaction and updating the contents of the processor interrupt pending register from the contents of the counter included in the transaction.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an embodiment of a multiprocessor interrupt control system of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a multiprocessor interrupt control system according to an embodiment of the present invention includes a processor control circuit 200-1, to which each of a plurality of processors 100-1, ..., 100-4 corresponds. ..., 200-
It is configured to be connected to the shared bus 700 via No. 4. I /
The O devices 500-1, 500-2, 500-3 are connected to the local bus 400-1, and the I / O devices 500-4, 5
00-5 and 500-6 are connected to the local bus 400-2, respectively. Local buses 400-1, 400-2
Are connected to the shared bus 700 via I / O control circuits 300-1 and 300-2, respectively.

I / O devices 500-1, 500-2,
500-3 is I / O via the interrupt line group 600-1.
It is directly connected to the control circuit 300-1. The I / O devices 500-4, 500-5, 500-6 are directly connected to the I / O control unit 300-2 via the interrupt line group 600-2.

Referring to FIG. 2, the processor controller 2 in the multiprocessor interrupt control system of the present invention.
0-1, via the processor input / output control circuit 210,
Data input / output control with the processor 100-1 and the shared bus 700 is performed. In addition, the processor control unit 200-1
Has a processor ID register 220 that stores the ID number of the corresponding processor, a register group 260, and an interrupt pending counter group 270.

The register group 260 stores a connect register 26 for storing an initialization test normal end flag indicating that the initialization test has been normally completed when the processor is started up.
1. An interrupt level register 262 that sets a level value indicating whether the interrupt corresponding to the interrupt factor is a high level or a low level, and an interrupt pending register 263 that indicates an interrupt factor code of interrupt processing during pending processing of the processor. It

Interrupt pending counter group 270
Counts the number of pending interrupt processes. Depending on the interrupt level, the number of high-level interrupt processes is in the high-level interrupt pending counter 271, and the number of low-level interrupt processes is in the low-level interrupt pending counter 272. Stored in each.

The processor control section 200-1 also has an interrupt reception control circuit 230, an interrupt request issue control circuit 240, and an interrupt completion issue control circuit 250. The interrupt receiving circuit 230 receives an interrupt from the shared bus. The interrupt request issuance control circuit 240
Issues an interrupt request to the corresponding processor. The interrupt completion issue control circuit 250 accepts an interrupt processing end notification from the corresponding processor, and issues a notification indicating that the interrupt has ended to the shared bus 700.

The I / O control circuit 300-1 transmits / receives data to / from the shared bus 700 and the local bus 400-1 via the I / O input / output control circuit 310.

The I / O control circuit 300-1 has a processor interrupt pending register group 340 for storing the number of pending interrupts of the processor on the system. The processor interrupt pending register group 340 includes a processor interrupt high-level pending register 341 and a processor interrupt low-level pending register 342, and the number of high-level interrupt pending corresponding to the interrupt level is the processor interrupt high-level pending register 341.
Further, the low-level interrupt pending number is stored in the processor interrupt low-level pending register 342, respectively.

Further, the I / O control circuit 300-1 has a register group 350. The register group 350 is a processor connection information register 3 that stores the ID number of a processor that was connected to the system and was normal at startup.
51, an interrupt factor code setting register 352 in which correspondence between each interrupt line group 600-1 and an interrupt factor code is set, and an ID of a processor to which an interrupt associated with each interrupt line group 600-1 is preferentially notified It is composed of an interrupt priority notification register 353 storing a number and an interrupt level setting register 354 storing a level value of an interrupt associated with each interrupt line.

Further, the I / O device control circuit 300-
1 is an I / O that controls an interrupt from the I / O device
Device interrupt acceptance control circuit 320, shared bus 7
An interrupt issuance control circuit 330 that issues an interrupt via 00 and an interrupt completion reception control unit 360 that receives an interrupt end notification from the shared bus. I /
The O-device interrupt acceptance control circuit 320 accepts an interrupt from the interrupt line group 600-1. The interrupt line group 600-1 includes interrupt lines INT # 1, INT # 2 and INT # 3.

Referring to FIG. 3, the interrupt level register 262 is set with a level value corresponding to the cause code of each interrupt. The level value consists of high and low, and a high level is set to the factor code that is desired to be processed early.

Referring to FIG. 4, in the interrupt pending register 263, 1 is set in the bit corresponding to the interrupt factor code which the processor is currently pending. The bit corresponding to the interrupt factor code that is not pending is set to 0.

Referring to FIG. 5, the processor interrupt high level pending register 341 holds the number of pending high level interrupts of each processor connected to the system. The number of low-level interrupts is similarly held in the processor interrupt low-level pending register 342.

Referring to FIGS. 6, 7 and 8, the interrupt factor code setting register 352 includes interrupt line groups 6
0-1, interrupt lines INT # 1, INT # 2 and I
An interrupt factor code is stored corresponding to each of NT # 3. The interrupt priority notification register 353 stores the ID number of the priority notification processor corresponding to each interrupt line. The interrupt level setting register 354 stores an interrupt level value corresponding to each interrupt line.

Next, the operation of the multiprocessor interrupt control system according to the embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIGS. 1 and 2, each processor which has normally completed the initialization test when the multiprocessor interrupt control system is started up is connected to the connect register 261 of its own processor control unit 200-1.
Set the initialization test normal end flag to. After a certain time from this processing, the master processor reads the connect register 261 of the processor control units 200-1 of all the processors via the shared bus, and becomes inoperable due to abnormal termination or failure in the initialization test. Degenerate operation processing is performed assuming that the processor is not connected to the shared bus, and processor connection information is generated. All the I / O control units 3 connected to the shared bus using this processor connection information
0-1 and 300-2 are notified, and the I / O control units 300-1 and 300-2 that have received the notification write the processor connection information in the processor connection information register 351.

Thereafter, the master processor firmware or the like sets in the interrupt level register 262 the correspondence between the interrupt factor code and the interrupt level when the interrupt is notified to the processor. In addition, I /
.., 500-3 are set in the interrupt factor code setting register 352 in association with each line of the interrupt line group 600-1. When the interrupt loads of the processors are equal in all the processors, the ID number of the processor which gives priority to the interrupt notification is set in the interrupt priority notification register in association with each line of the interrupt line group 600-1. Further, the correspondence between the interrupt line group 600-1 and the interrupt level values high and low is set in the interrupt level register 334.

The relative relationship between the interrupt levels of the interrupt factors is set in the interrupt level register 262 and the interrupt level setting register 354 so that they do not conflict with each other. That is, as shown in FIG. 8, in the interrupt level setting register 354, the interrupt line INT # 1 is set to high level, and INT # 2 and INT # 3 are set to low level. Each of these interrupt lines is set to IN from the contents of the interrupt factor code setting register 352 shown in FIG.
Since T # 1 is set as the interrupt factor code 12, INT # 2 is set as the interrupt factor code 13, and INT # 3 is set as the interrupt factor code 14, the interrupt factor code 12
Is a high level interrupt, and the interrupt factor codes 13 and 14 are low level interrupts. Thus, as shown in FIG. 3, in the interrupt level register 262, the interrupt factor code 12 is set to the high level and the interrupt factor codes 13 and 14 are set to the low level.

Next, the high level interrupt pending counter 271 and the low level interrupt pending counter 272 of all the connected processor control units 200-1, ..., 200-4 are set to the initial value 0. In addition, all connected I / O control units 3
The processor interrupt high level pending register 341 and the processor interrupt low level pending register 342 of 00-1 and 300-2 are initialized to 0.
Set to each.

Referring to FIGS. 1 and 2, the I / O control unit 300-1 includes an I / O device 500-1 ,.
A plurality of interrupt notifications are received from 500-3 via the interrupt line group 600-1. This interrupt notification is I /
It is accepted by the O-device interrupt acceptance control unit 320. The I / O device interrupt acceptance control unit 320 refers to the interrupt level setting register 354 and accepts an interrupt from an interrupt line having a high interrupt level in the notification of the interrupt. If the interrupt levels are the same, control such as round robin is performed to determine the interrupt to be accepted. The I / O device interrupt acceptance control unit 320 reads the interrupt factor code of the accepted interrupt from the interrupt factor setting register 362, and notifies the interrupt issue control unit 330 of this interrupt factor code and interrupt level.

Referring to FIGS. 2, 9 and 12, the interrupt issuance control unit 330 determines that the processor interrupt pending register group 3 corresponding to the received interrupt level.
The number of pending interrupts of each processor is read from 40 (step 92). That is, if the interrupt level is the high level, the processor interrupt high level pending register 341 is read, and if the interrupt level is the low level, the pending interrupt number of each processor is read from the processor interrupt low level pending register 342. It is determined whether or not the number of pending interrupts is equal for all processors (step 93). If they are not equal, it is the processor with the smallest number of pending interrupts, and the processor operation register 351 is operating normally. Determine the ID number of the processor to be verified (step 9)
4). If the number of pending interrupts of all processors is equal, the ID number of the priority processor to be preferentially notified is read from the interrupt priority notification register 353 (step 95). It is determined whether or not this priority processor has been subjected to the degeneration operation processing (step 96), and if it has not been subjected to the degeneration operation processing, this priority processor is determined as an interrupt processor (step 97). If the priority processor has been subjected to the degenerate operation process, 1 is added to the ID number of the priority processor and the process returns to step 96. When the processor of the interrupt notification destination is determined, the interrupt factor set transaction 10 is generated and sent to the shared bus 700 via the I / O input / output control circuit 310 (step 99).

Referring to FIGS. 2 and 10, in the processor control unit 200-1, the interrupt reception control unit 230 monitors the shared bus 700 and interrupts the processor 100-1 connected to the own processor unit 200-1. The factor set transaction 10 is received (step 101). The corresponding bit of the interrupt pending register 263 is set from the interrupt factor code 11 of this transaction (step 102). By referring to the interrupt level register 262, the level value corresponding to the interrupt request code 11 of this transaction 10 is read (step 103), and the interrupt pending counter group 270 of the corresponding level is incremented (step 104). That is, when the level value is the high level, the high level interrupt pending counter 271
Is low level, the low level interrupt pending counter 272 is incremented. Returning to step 101, interrupts are successively accepted, and the interrupt pending counter group 270 is incremented each time.

The interrupt request issuance control unit 240 monitors the interrupt pending register 263 and issues interrupt commands to the processor in order from the interrupt request having the highest interrupt level.

Referring to FIGS. 2 and 11, when the processor 100-1 finishes processing a certain interrupt factor,
A completion notice is sent to the processor control unit 200-1. The completion notification is received by the interrupt completion controller 250 of the processor controller 200-1 (step 11).
1). The bit of the interrupt pending register 263 corresponding to the interrupt factor code of this completed interrupt is set to 0 (step 112). Further, the level value corresponding to this interrupt factor code is read from the interrupt level register 262 (step 113), and the interrupt pending counter group 270 corresponding to this level value is decremented (step 114). That is, when the level value is high level, the high level interrupt pending counter 271 is set to low level, and when the level value is low level,
The low level interrupt pending counter 272 is decremented. Further, the interrupt factor clear transaction 20 is generated using the values of the interrupt pending counters 271 and 272 after decrement (step 115), and is sent to the shared bus 700 via the processor input / output control circuit 210 (step 116).

Referring to FIG. 2 and FIG. 12, in the I / O control units 300-1 and 300-2, each interrupt completion notification reception control unit 360 constantly monitors the interrupt factor clear transaction 20 on the shared bus 700, To receive. Based on the transaction issue source processor information 22, the high level pending number 24, and the low level pending number 25 of the received interrupt factor clear transaction 20, the processor of the corresponding level of the processor interrupt pending register group 340 in the own I / O control unit 300-1. Update the pending number corresponding to the ID number.
Further, it is determined whether the clear notification destination information 23 of the interrupt factor clear transaction indicates the own I / O control unit, and if the clear notification destination information 23 indicates the own I / O control unit 300-1, it is the issuer of the interrupt. Clears interrupt factors for I / O devices.

As described above, in the multiprocessor interrupt control system according to the embodiment of the present invention, the interrupt pending register 27 for storing the interrupt pending number in the processor control units 200-1, ..., 200-4.
1 and 272, and each processor control unit 200-
Each of the interrupt pending numbers from 1, ..., 200-4 is communicated to the I / O control units 300-1 and 300-2. Inside the I / O control units 300-1 and 300-2, a processor interrupt high level pending register 341 and a processor interrupt low level pending register 342 for storing the interrupt pending number of each processor are provided, and these values are constantly updated. I decided to do it. As a result, the I / O control unit 300-
1,300-2 can always grasp the number of pending interrupts of all processors. For this reason, an interrupt can be notified to the processor with the lightest interrupt load, and the interrupt load can be evenly distributed.

[0039]

As is apparent from the above description, according to the present invention, each of a plurality of processor control units is provided with an interrupt pending register for storing the number of interrupt pendings, and each processor control unit is provided with an interrupt pending number. Communication is made with the I / O control unit. Further, each of the plurality of I / O control units is provided with a processor interrupt high pending register and a processor interrupt low level pending register in which the interrupt pending number of each processor is stored, and these values are constantly updated. As a result, each I / O control unit can always grasp the number of pending interrupts of all processors. For this reason, an interrupt can be notified to the processor with the lightest interrupt load, and the interrupt load can be evenly distributed. Further, even in a large-scale system, interrupt load distribution can be realized at high speed and uniformly.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a multiprocessor interrupt control system of the present invention.

FIG. 2 is a block diagram showing a processor control circuit and an I / O device control circuit according to an embodiment of the present invention.

FIG. 3 is an interrupt level register 2 according to an embodiment of the present invention.
It is a figure which shows the content of 62.

FIG. 4 is a diagram showing the contents of an interrupt pending register 263 according to an embodiment of the present invention.

FIG. 5 is a diagram showing the contents of a processor interrupt pending register group 340 according to an embodiment of the present invention.

FIG. 6 is an interrupt factor code setting 3 according to an embodiment of the present invention.
It is a figure which shows the content of 52.

FIG. 7 is a diagram showing the contents of an interrupt priority notification register 353 according to an embodiment of the present invention.

FIG. 8 is a diagram showing the contents of an interrupt level setting register 354 according to an embodiment of the present invention.

FIG. 9 is an interrupt issuance control circuit 33 according to an embodiment of the present invention.
It is a figure which shows the flow of the operation | movement of 0.

FIG. 10 is a diagram showing an operation flow of an interrupt request issuance control circuit 240 according to an embodiment of the present invention.

FIG. 11 is a diagram showing an operation flow of an interrupt completion issue control circuit 250 according to an embodiment of the present invention.

FIG. 12 is a diagram showing an interrupt factor set transaction and an interrupt factor clear transaction according to an embodiment of the present invention.

[Explanation of symbols]

 100-1, ..., 100-4 Processor 200-1, ..., 200-4 Processor control circuit 300-1, 300-2 I / O control circuit 400-1, 400-2 Local bus 500-1 , 500-6 I / O device 600-1, 600-2 interrupt line 700 shared bus

Claims (6)

[Claims] 1. A multiprocessor interrupt control system for distributing interrupt requests from a plurality of I / O devices to a plurality of processors via interrupt lines, and processor control means associated with each of the plurality of processors, I / O device control means for accepting an interrupt from each of the plurality of I / O devices via the interrupt line, wherein the processor control means controls the weight of the interrupt load of the associated processor to the I / O. The I / O device control means includes means for notifying a device control means, and the I / O device control means includes means for controlling transmission of an interrupt request to a processor having the lightest interrupt load at present based on the contents of the transaction. Processor interrupt control system. 2. The processor control means, an interrupt level register for storing an interrupt level associated with an interrupt factor, a counter for counting the number of pending interrupts according to the interrupt level, Interrupt reception control means for receiving an interrupt request from the O-device control means and incrementing the corresponding level of the counter from the interrupt level stored in the interrupt level register corresponding to the interrupt factor code included in the request; The multiprocessor interrupt control system according to claim 1, further comprising an interrupt completion issue control means for notifying the I / O device control means of the contents of the counter. 3. The processor control means sends out to the processor from an interrupt pending register that stores an interrupt pending number associated with an interrupt factor, and the contents of the interrupt level register and the interrupt pending register. 3. The multiprocessor interrupt control system according to claim 2, further comprising interrupt request issue control means for determining an interrupt and controlling transmission. 4. The I / O device control means, a processor interrupt pending register that stores a pending number of each of a plurality of processors according to an interrupt level, accepts the transaction, and determines the processor interrupt from the content of the transaction. 2. The multiprocessor interrupt control system according to claim 1, further comprising interrupt completion notification reception control means for updating and controlling the contents of the pending register. 5. The I / O device control means stores an interrupt priority number in which an ID number of a processor that preferentially notifies an interrupt when the interrupt level obtained from the processor interrupt pending register is equal to all processors is stored. 7. A notification register, and an interrupt issuing control means for controlling, based on the contents of the interrupt priority notification register and the contents of the processor interrupt pending register, transmission of an interrupt request to the processor with the lightest load at present. 4. The multiprocessor interrupt control system described in 4 above. 6. The I / O device control means stores an interrupt level setting register in which an interrupt level associated with each of the plurality of interrupt lines is stored, and an interrupt level setting register when receiving an interrupt from each of the plurality of interrupt lines. 2. The multiprocessor interrupt control system according to claim 1, further comprising interrupt acceptance control means for determining an interrupt to be accepted from the contents of the interrupt level setting register.