JPH09153903A - Control signal transfer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transfer an in-equipment control signal without installation of a private line for the control signal when the control signal is transferred between packages in an ATM(asynchronous transfer mode) equipment. SOLUTION: When an ATM cell is terminated by an ATM cell termination section 31 in a transmission line interface package 3 and the cell is used for an ATM cell in the ATM equipment, a header error control(HEC) byte of a cell header part is set idle. Then an in-HEC byte signal insert section 32 inserts a control signal from a control signal generating circuit 33 to the idle HEC byte and the resulting cell is sent to a data multiplex/demultiplex package 4. Then an in-HEC byte signal detection section 41 extracts the control signal in the HEC byte and gives the control signal to a control signal detection circuit 42.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control signal transfer system, and more particularly to a transfer control system of an in-device control signal in an ATM (asynchronous transfer mode communication) device.

[0002]

2. Description of the Related Art A block diagram of FIG. 7 schematically shows an example of an ATM device. Referring to FIG. 7, in the ATM device 1, the ATM cells, which are optical signals from the transmission line 2, are respectively transmitted by a plurality of transmission line interface packages 3-1 to 3-4 (in this example, four packages are shown). Each of the transmission line interface packages 3-1 to 3-4 is an AT which is received and converted into an electric signal to generate an ATM cell in the device.
It has an M cell termination function.

ATM cells in these devices are multiplexed by a data demultiplexing package 4 and distributed by a SW (switch) package 5 in units of VP (virtual path). The distributed cells are separated into cells for each transmission line in the data demultiplexing package 6, and the ATM is used in the transmission line interface packages 7-1 to 7-4.
The transmission line 8 is converted into cells and converted from electrical signals to optical signals.
Sent to

In such an ATM device 1, the data demultiplexing package 4 is controlled by the in-device control signal generated by each of the transmission line interface packages 3-1 to 3-4. Therefore, it is necessary to transfer the control signal in the apparatus from each of the transmission line interface packages 3-1 to 3-4 to the data demultiplexing package 4. In the conventional case, as shown by the dotted line in FIG. The notification line 9 is provided to transfer the control signal.

[0005]

Since the data respectively supplied from the plurality of transmission line interface packages 3-1 to 3-4 are multiplexed by the data demultiplexing package 4, a dedicated notification for the in-device control signal is issued. When the line 9 is provided for each transmission line interface package, a physical connection (BWB; Back Wiring Boar) between the packages is provided.
d) The number increases and becomes impossible to deal with due to the BWB pin limitation.

Further, by providing a dedicated line for a control signal in the package, the wiring in the printed circuit board increases,
When the wiring density is high, it is extremely difficult to increase the wiring.

An object of the present invention is to provide a control signal transfer system capable of solving the above problems by allowing inter-package transfer of in-device control signals to be shared with data lines without providing a dedicated line.

[0008]

According to the present invention, a plurality of interface units for respectively receiving data cells from a plurality of transmission lines, and a multiplexing for multiplexing each data cell from these plurality of interface units. A control signal transfer system for transferring an in-device control signal between each of the interface units and the multiplexing unit in a communication device including a unit, the data cell being provided in each of the interface units. Control signal inserting means for inserting the in-device control signal into a predetermined part of the header part, and a control signal for extracting the in-device control signal provided in the multiplexing part in the predetermined part of the header part of the data cell A control signal transfer system is obtained which includes an extracting means.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The operation of the present invention will be described. When the ATM cell received from the transmission line is terminated at the ATM cell terminating portion in the transmission line interface package to be the in-apparatus ATM cell, a predetermined byte in the cell header portion is vacant. Therefore, the empty bytes in the header portion are used to insert and transmit the in-device control signal, and the data demultiplexing package extracts this.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. Referring to FIG. 1, the ATM cell from the transmission line is the ATM cell termination unit 3 of the transmission line interface package 3.
It is terminated with 1 and an intra-device header is added by 1 byte to be converted into an intra-device ATM cell. And HEC (Head
er Error Control) The in-byte signal insertion unit 32 inserts the control signal generated by the control signal generation circuit 33 into the HEC byte of the ATM cell and sends it to the data demultiplexing package 4.

In the data demultiplexing package 4, the HEC
The in-byte signal detection unit 41 detects and extracts the control signal in the HEC byte, and the control signal detection circuit 42 processes the control signal. This control signal has various kinds of control information. For example, the phase difference information of the cell between the active standby system for switching from the active system to the standby system, and the in-device A
There is control information for controlling the transmission of ATM cells in the device from the data demultiplexing package 4 in order to avoid overflow of the buffer for exchanging TM cells → ATM cells.

FIG. 2 is a format diagram of an ATM cell in the device. # 1 to # 54 represent the numbers of the constituent bytes of the cell. In the timing charts of FIGS.
It is shown using # 54. The format of this figure is NN
I (Network Node Interface)
In the case of UNI (User Network).
In the case of k Interface), the 5th to 8th bits of the first byte of the ATM header are GFC (Generic Fl).
ow Control). HEC byte is ATM
There is a 1-byte area at the 5th byte of the header.

This HEC byte is used for the ATM cell termination unit 31.
In the present invention, the above various control information in the apparatus is inserted into the HEC byte because it becomes empty at the time of the termination processing.

In FIG. 2, VPI is Virtua.
l Path Identifier, VCI is Vir
tual Channel Identifier, P
T is Payload Type, RS is Regener
ation Section, CLP is Cell Lo
It means ss Priority, respectively.

FIG. 3 shows the HEC in-byte signal insertion unit 3 of FIG.
It is a block diagram which shows the specific example of 2. In FIG. 3, 1
The data D-IN0 to 7 for each byte (8 bits) is latched by the latch circuit 321 by the system clock CLK, and these latch outputs are 2-input-1 output selector 322.
1 input A of The control signals 14 to 21 from the control signal generation circuit 33 are supplied to the other input B of the selector 322, respectively, and the timing generation circuit 3 for the HEC byte is supplied.
Signal 1 showing the timing of the HEC byte generated from
3 (S), the selector 322 controls the selection of the output Y, and the selection output Y outputs the data outputs D-OUT0 to D-OUT0.
It becomes 7.

HEC byte timing generation circuit 323
Is composed of a 54-ary counter 324 and a 6-54 decoder 325, and generates the timing signal 13 indicating the HEC byte position of the ATM cell in the device.

FIG. 4 shows a timing chart of the signals of the respective parts in FIG. 3, in which a pulse CP having a width of one clock CLK is output at the cell cycle of the ATM cell in the apparatus, and an inverted signal 11 of CP indicating the beginning of the cell is LD of the 54-ary counter 323
As a (load input), the counter is incremented by the clock CLK, and the 6-54 decoder 325 outputs H
The 6th byte which is the area of the EC byte is decoded, and by this decode signal 13, the control signals 14 to 21 generated by the control signal circuit 33 are inserted into the HEC byte in the data D-IN0 to 7 latched by the latch circuit 321. And output as data D-OUT0-7.

FIG. 5 shows the HEC in-byte signal detector 4 of FIG.
It is a block diagram which shows the specific example of 1. In FIG. 5, H
The ATM cells in the apparatus from the EC byte signal inserting section 32 are latched by the latch circuit 411 as DAIN0 to 7 for each byte, and the latch output 140 is 1 of the 2-input-1 output selector in the HEC byte detection circuit 412. It becomes the input B, and its selector output is taken into the latch F / F.
The output of the latch F / F is supplied to the control signal detection circuit 42 and also serves as the other input B of the selector.

The selection signal S of this selector is the timing signal 130 indicating the HEC byte position generated by the HEC byte timing generation circuit 413. This HEC
The byte timing generation circuit 413 is the HEC shown in FIG.
It has the same configuration as the byte timing generation circuit 323.

FIG. 6 is a timing chart showing the operation of the circuit of FIG. HEC byte timing generation circuit 32
By the timing signal 130 indicating the position of the HEC byte detected in 3, the 2-input-1 output selector inputs B
The control signal 150 of the HEC byte is supplied to the control signal detection circuit 42 by switching from A to A and continuously latching by the latch F / F.

[0022]

As described above, according to the present invention, the in-device control signal is inserted and transferred in the empty header byte portion of the in-device ATM cell, so that wiring on the printed circuit board in the package and There is an effect that a physical connection line between BWBs becomes unnecessary.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing a format example of an ATM cell in a device.

FIG. 3 is a block diagram showing a specific example of an HEC in-byte signal insertion unit 32.

FIG. 4 is a timing chart showing the operation of the blocks of FIG.

FIG. 5 is a diagram showing a specific example of an HEC in-byte signal detection unit.

FIG. 6 is a timing chart showing the operation of the block shown in FIG.

FIG. 7 is a schematic block diagram illustrating a conventional ATM device.

[Explanation of symbols]

1 ATM device 2, 8 transmission line 3-1 to 3-4, 7-1 to 7-4 transmission line interface package 4, 6 data demultiplexing package 5 SW package 31 ATM cell package 32 HEC in-byte signal insertion unit 33 control Signal generation circuit 41 HEC in-byte signal detection unit 42 Control signal detection circuit

Claims (3)

[Claims] 1. A communication device comprising: a plurality of interface units for respectively receiving data cells from a plurality of transmission lines; and a multiplexing unit for multiplexing each data cell from the plurality of interface units. A control signal transfer system for transferring an in-device control signal between each unit and the multiplexing unit, wherein the in-device control is provided in a predetermined part of a header part of the data cell provided in each of the interface parts. Control signal inserting means for inserting a signal, and control signal extracting means for extracting the in-device control signal provided in the multiplexing section and inserted in a predetermined portion of the header portion of the data cell. Control signal transfer system. 2. The communication device is an ATM (asynchronous transfer mode communication) device, each of the interface units has cell terminating means for terminating the data cell, and the control signal inserting means is the cell of the data cell. 2. The control signal transfer system according to claim 1, wherein the in-apparatus control signal is inserted into a vacant portion after termination by the terminating means. 3. The control signal transfer system according to claim 2, wherein the empty portion is the sixth byte of the header portion of the data cell.