JPH09153881A - Data transmitting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To permit an adder, A/D and D/A converters to be small in number of bits by multiplexing a frequency by the use of a Hadamard function in place of sine wave in a cable transmission path and the transmission of an infrared- ray, etc. SOLUTION: A transmitting device 1 converts input data into the synthetic waveform S16 of plural frequencies corresponding to input data through the use of an encoding circuit 10, the band of the frequency is limited in LPF circuit 11, executed FM modulation, for example, in a modulating circuit 12 and transmitted to a transmission line L12 . A receiving device 2 FM-demodulates, for example, a signal received from the transmission line L12 by a demodulating circuit 22, takes-out only the baseband signal S21 of a required frequency band by the LPF circuit 21, analizes a frequency component added in the signal S21 by the decoding circuit 20 and generates output data corresponding to the frequency. In the decoding, the received baseband signal S21 is subjected to Hadamard transformation from a one-frame time waveform by the use of a prescribed Hadamard matrix and the input data signal is generated per frame.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission device, and more particularly to an OFDM (Orthogon) used for a wired transmission line with no frequency band limitation or a modulation / demodulation device for infrared rays.
al FrequencyDivision Multiplexing (Orthogonal Frequency Division Multiplexing) The present invention relates to a data transmission apparatus including an encoding and decoding circuit.

[0002]

2. Description of the Related Art Conventionally, an example of a system configuration having a transmitter 3 and a receiver 4 as shown in FIG. 6 has been proposed as an OFDM data transmitter. The transmitter 3 includes an encoding circuit 30, an LPF circuit 31, and a modulation circuit 32. The output side (output signal S ₃₆ ) of the encoding circuit 30 is connected to the input side of the LPF circuit 31, and the output side of the LPF circuit 31 is connected to the input side of the modulation circuit 32. The output side of the modulation circuit 32 is connected to the transmission line L ₃₄ via the terminal P ₃ .

The receiver 4 includes a decoding circuit 40 and an LPF circuit 4
1. Demodulation circuit 42. The input side of the demodulation circuit 42 is connected to the transmission line L ₃₄ via the terminal P ₄ . Demodulation circuit 4
The output side of 2 is connected to the input side of the LPF circuit 41, and the output side (output signal S ₄₁ ) of the LPF circuit 41 is connected to the input side of the decoding circuit 40. FIG. 7 shows a configuration example of the encoding circuit 30. Eight data input terminals I ₃₁ , I ₃₂ , I ₃₃ , I ₃₄ , I ₃₅ , I ₃₆ ,
I ₃₇ and I ₃₈ are connected to the input port of the 8-bit data selector 301. The output side of the data selector 301 (output signal S ₃₁ (1 bit)) is connected to one input port of the 8-bit multiplier 303, and the output side of the 8-bit × 64 data memory 302 (output data signal S ₃₂ (8 bits)) is the multiplier 3
It is connected to the other input port of 03. The output side of the multiplier 303 (output data signal S ₃₃ (8 bits)) is connected to one input port of a 12-bit adder 304. Output side of adder 304 (output data signal S ₃₄ (12 bits))
Is connected to the input port of the 12-bit latch register 305, and the output side of the latch register 305 (the output data signal S
₃₅ (12 bits) is connected to the input port of the 12-bit D / A converter 306 and the other input port of the adder 304. Output side of D / A converter 306 (output signal S ₃₆ )
Is connected to the input side of the LPF circuit 31 (FIG. 6).

The output signals Φ ₃₁ , Φ ₃₂ , and Φ ₃₃ of the data processing timing generator 307 are input as column address signals of the data selector 301 and the 8-bit × 64 data memory 302. The output signals Φ ₃₄ , Φ ₃₅ , and Φ ₃₆ of the data processing timing generator 307 are input as row address signals of the data memory 302. Further, the output signals Φ ₃₇ and Φ ₃₈ of the data processing timing generator 307 are input as the rising latch signal and the L level active data clear signal of the latch register 305, and Φ ₃₉ is input as the input data rising latch signal of the D / A converter 306. To be done.

FIG. 8 shows a configuration example of the decoding circuit 40. Output side of the LPF circuit 41 of the receiver 4 (FIG. 6) (output signal S ₄₁ ).
Is connected to the analog signal input port of the 12-bit A / D converter 401, and the output side of the A / D converter 401 (data output signal S ₄₂ (12 bits)) stores one frame of sampling data. 12-bit x 8 FIFO 403 to do
Connected to the input port of. The output side of the FIFO 403 (output data signal S _{42 ′} (12 bits)) is connected to one input port of the 12-bit multiplier 404 and the output side of the 8-bit × 64 data memory 402 (output signal S ₄₃ (8 bits) )) Is the multiplier
Connected to the other input port of 404. The output side of the multiplier 404 (output data signal S ₄₄ (12 bits)) is connected to one input port of the 12-bit adder 405, and the adder 4
The output side of 05 (output data signal S ₄₅ (12 bits)) is 12
It is connected to the input port of the bit latch register 406. Output side of the latch register 406 (output data signal S ₄₆
(12 bits) is connected to the other input port of the adder 405 and one input port of the 12-bit comparator 407. A preset 12-bit threshold level data signal S ₄₈ is input to the other input port of the comparator 407, and the output side of the comparator 407 (output signal S ₄₇ (1 bit)) is 8-bit S. It is connected to the input port of the / P converter 408. Eight data output terminals O ₄₁ , O ₄₂ , O ₄₃ , and O are provided to the output port of the S / P converter 408.
₄₄ , O ₄₅ , O ₄₆ , O ₄₇ and O ₄₈ are connected.

Output signals Φ ₄₁ , Φ ₄₂ , Φ ₄₃ , Φ _{44 of} the data processing timing generator 409 synchronized with one frame
Φ ₄₅ and Φ ₄₆ are input as the address signal of the data memory 402, and Φ ₄₇ and Φ ₄₈ are input as the rising latch signal and the L level active data clear signal of the latch register 406. Data processing timing generator
The output signals Φ ₄₀ and Φ ₄₉ of 409 are input as the sampling clock signal of the A / D converter 401 and the rising shift clock signal of the S / P converter 408. Here, the description of the frame synchronization described above is omitted.

Table 1 shows the configurations of the data memory 302 of the encoding circuit 30 and the data memory 402 of the decoding circuit 40.

[0008]

[Table 1]

(A) shows the contents of the 8-bit × 64 data memory 302 of the encoding circuit 30. Column address offset is Φ
₃₁ , Φ ₃₂ , Φ ₃₃ , and row address offsets are Φ ₃₄ , Φ
It is specified by ₃₅ and Φ ₃₆ . (b) 8 bits of decoding circuit 40 ×
The contents of 64 data memories 402 are shown. The column address offsets are specified by Φ ₄₁ , Φ ₄₂ , and Φ ₄₃ , and the row address offsets are specified by Φ ₄₄ , Φ ₄₅ , and Φ ₄₆ . The Fourier coefficient ω in Table 1 is represented by the following formula.

Ω = EXP (-j2π / N) = COS (2π / N) -jSIN (2π / N) (where N varies depending on the number of elements in Table 1. In 8 × 8,
N = 8) Here, only the first term (real number term) of the Fourier coefficient ω 1 is used. The Fourier coefficient ω is a real number of 1 or less, but when the number of significant digits is 2 digits after the decimal point, it is necessary to have 8 or more digits in binary. Here, the case of 8 digits (8 bits) will be described.

In the data transmission device having such a configuration, the transmission device 3 uses the encoding circuit 30 to encode the input data, and the composite waveform S ₃₆ of a plurality of frequencies corresponding to the input data.
Then, the LPF circuit 31 limits the frequency band, the modulation circuit 32 performs FM modulation, for example, and sends the result to the transmission line L ₃₄ . This encoding is the inverse Fourier transform (8 × 8) of the input data signal (8 bits) to be transmitted using Table 1 (a),
The process of generating the temporal waveform of one frame is repeated. Details of data processing for one frame will be described below with reference to the operation of the encoding circuit 30 in FIG. Inverse Fourier transform, input data and table 1
It can be realized by performing the "convolution operation" of (a). For example, if the row address signal of the data memory 302 is Φ ₃₁ =
0, Φ ₃₂ = 1, when Φ _{3 3} = 0, selected in Table 1 sequentially read out signals from the beginning of the second line of the data memory 302 which records the Fourier coefficients of (a) S ₃₂ and the data selector 301 inputs The data signal S ₃₁ is multiplied by the multiplier 303 to output the output signal S _{33 of the} multiplier 303.
And the output data signal S ₃₅ of the latch register 305 is added to the adder 304.
Add with. The above operation is repeated eight times, and finally the output signal S ₃₅ of the latch register 305 is latched in the D / A converter 306 at the rising edge of Φ ₃₉ , and then Φ _{38 is set} to the L level to clear the contents of the latch register 305 to zero. The above operation is repeated eight times in each column of Table 1 (a) to generate the output signal S ₃₆ of one frame.

In the receiver 4, the demodulation circuit 42 demodulates the signal received from the transmission line by, for example, FM, the LPF circuit 41 extracts only the baseband signal S ₄₁ in the required frequency band, and the decoding circuit 40 outputs the signal S. _The frequency component contained in ₄₁ is analyzed, and the output data corresponding to the above-mentioned frequency is generated.
In this decoding, the received baseband signal S ₄₁ is Fourier transformed (8 × 8) from the time waveform of one frame using the Fourier coefficient of Table 1 (b), and the input data signal corresponding to each frequency component is obtained. Generate for each frame. The details of the data processing for one frame will be described below with reference to the operation of the decoding circuit 40 in FIG. The analog signal S ₄₁ input to the decoding circuit 40 is A /
The D converter 401 samples every rising edge of Φ ₄₀ , and eight data S ₄₂ are _recorded in one frame of the analog signal S _41.
Is recorded in the FIFO 403. The Fourier transform can be realized by performing “convolution operation” in Table 1 (b) with the input data, similarly to the encoding. For example, data memory 40
When the row address signals of 2 are Φ ₄₁ = 0, Φ ₄₂ = 1, Φ ₄₃ = 0, Table 1
The multiplier 404 multiplies the signal S ₄₃ sequentially read from the beginning of the second row of the data memory 402 recording the Fourier coefficient of (b) and the input data signal S _{42 ′} read from the FIFO 403 by the multiplier 404.
The adder 405 adds the output signal S ₄₄ of the multiplier 404 and the output data signal S ₄₆ of the latch register 406. The above operation is repeated 8 times, and finally the output signal S ₄₆ of the latch register 406 is compared with the threshold value data S ₄₈ preset by the comparator 407, and the output signal S ₄₇ (output signal S _{47
After 46} "1" if the above threshold data S _48, a "0") of less than and rising in one data shift input of [Phi ₄₉ to the S / P converter 408, the [Phi ₄₈ L level Then, the contents of the latch register 406 are cleared to zero. The above operation is repeated eight times in each column of Table 1 (b), and 8-bit data is output from the data output terminals O ₄₁ , O ₄₂ , O ₄₃ , O ₄₄ , O ₄₅ , O ₄₆ , O ₄₇ and O ₄₈ . The data processing timing generator 409 is
It shall operate taking an input signal S ₄ synchronization and one frame as shown in FIG. 10 but omitted the description of the frame synchronization method here.

[0013]

A conventional OFDM type data transmission apparatus has a severe band limitation of a frequency to be used like a radio wave for broadcasting, and a frequency multiplex sign is applied to make it resistant to noise and multipath. In order to use the wave as a carrier, it is necessary to perform Fourier transform and Fourier inverse transform, and the number of bits of the multiplier, adder, A / D, D / A converter becomes large. In addition, there are drawbacks such as an increase in the data memory capacity, a large circuit size that can be realized, and a high cost.

The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional OFDM type data transmission apparatus, and a wired transmission line with no limitation on the frequency band to be used,
In the transmission of infrared rays and the like, an adder, A /
The number of bits of the D, D / A converter can be reduced, the multiplier can be configured with a simple gate, and the data memory capacity can be reduced. It is intended to provide a data transmission device that is strong in a path.

[0015]

In order to achieve this object, a data transmission apparatus of the present invention has a transmission apparatus having an encoding circuit using inverse Hadamard transform and a decoding circuit using Hadamard transform. And a receiver.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of a data transmission device according to the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a system configuration example of a data transmission device according to the present invention. The data transmission device includes a transmission device 1 and a reception device 2.

The transmitter 1 includes an encoding circuit 10 and an LPF circuit 1.
1. Modulation circuit 12. The output side (output signal S ₁₆ ) of the encoding circuit 10 is connected to the input side of the LPF circuit 11, and the output side of the LPF circuit 11 is connected to the input side of the modulation circuit 12. The output side of the modulation circuit 12 is connected to the transmission line L ₁₂ via the terminal P ₁ . The receiving device 2 includes a decoding circuit 20, an LPF circuit 21,
It is composed of a demodulation circuit 22. The input side of the demodulation circuit 22 is connected to the transmission line L ₁₂ via the terminal P ₂ . The output side of the demodulation circuit 22 is connected to the input side of the LPF circuit 21, and the output side (output signal S ₂₁ ) of the LPF circuit 21 is connected to the input side of the decoding circuit 20.

FIG. 2 shows a configuration example of the encoding circuit 10. Eight data input terminals I ₁₁ , I ₁₂ , I ₁₃ , I ₁₄ , I ₁₅ , I ₁₆ ,
I ₁₇ and I ₁₈ are connected to the input port of the 8-bit data selector 101. The output side of the data selector 101 (output signal S ₁₁ (1 bit)) is connected to one input port of the 1-bit multiplier 103, and the output side of the 64-bit data memory 102 (output data signal S ₁₂ (1 bit)). Bit)) is connected to the other input port of the multiplier 103. The output side of the multiplier 103 (output data signal S ₁₃ (1 bit)) is connected to one input port of a 4-bit adder 104. The output side (output data signal S ₁₄ (4 bits)) of the adder 104 is connected to the input port of the 4-bit latch register 105, and the output side (output data signal S ₁₅ (4 bits)) of the latch register 105 is , 4-bit D / A converter 106 and the other input port of adder 104. D
The output side (output signal S ₁₆ ) of the / A converter 106 is connected to the input side of the LPF circuit 11 (FIG. 1).

Output signals Φ ₁₁ , Φ ₁₂ , and Φ ₁₃ of the data processing timing generator 107 are input as column address signals of the data selector 101 and the data memory 102. Further, the output signal Φ _{14 of} the data processing timing generator 107,
Φ ₁₅ and Φ ₁₆ are input as row address signals of the data memory 102. Further, the output signals Φ ₁₇ and Φ ₁₈ of the data processing timing generator 107 are input as the rising latch signal and the L level active data clear signal of the latch register 105, and Φ ₁₉ is input as the input data rising latch signal of the D / A converter 106. To be done.

FIG. 3 shows a configuration example of the decoding circuit 20. Receiving apparatus 2 output side of the LPF circuit 21 (FIG. 1) (the output signal S ₂₁₎
Is connected to the analog signal input port of the 4-bit A / D converter 201, and the output side of the A / D converter 201 (data output signal S ₂₂ (4 bits)) stores 1 frame of sampling data. Is connected to the input port of the 4-bit × 8 FIFO 203. The output side of the FIFO 203 (output data signal S _{22 ′} (4 bits)) is connected to one input port of the 4-bit multiplier 204 and the output side of the 64-bit data memory 202 (output signal S ₂₃ (1 bit)). Is connected to the other input port of multiplier 204. The output side of the multiplier 204 (output data signal S ₂₅ (4 bits)) is connected to one input port of the 4-bit adder 205, and the output side of the adder 205 (output data signal S ₂₅ (4 bits)) ) Is connected to the input port of the 4-bit latch register 206. Output side of latch register 206 (output data signal S ₂₆ (4 bits))
Is the other input port of adder 205 and 1/8 divider 2
Connected to 07 input port. The output side (output signal S ₂₇ (1 bit)) of the frequency divider 207 is an 8-bit S / P converter 20.
Connected to 8 input ports. S / P converter data output terminal O ₂₁ 8 pieces of the output port of _{208, O 22, O 23,} O 24,
O ₂₅ , O ₂₆ , O ₂₇ and O ₂₈ are connected.

Output signals Φ ₂₁ , Φ ₂₂ , Φ ₂₃ , Φ _{24 of} the data processing timing generator 209 synchronized with one frame
Φ ₂₅ and Φ ₂₆ are input as the address signal of the data memory 202, and Φ ₂₇ and Φ ₂₈ are input as the rising latch signal and the L level active data clear signal of the latch register 206. Data processing timing generator
The output signals Φ ₂₀ and Φ ₂₉ of 209 are input as the sampling clock signal of the A / D converter 201 and the rising shift clock signal of the 8-bit S / P converter 208. Here, the description of the frame synchronization described above is omitted.

Table 2 shows the configurations of the data memory 102 of the encoding circuit 10 and the data memory 202 of the decoding circuit 20.

[0023]

[Table 2]

The contents of the 64-bit data memories 102 and 202 of the encoding circuit 10 and the decoding circuit 20 have the row address offsets of Φ ₁₁ , Φ ₁₂ , and Φ ₁₃ (Φ ₂₁ , Φ ₂₂ , and Φ ₂₃ ). Address offsets are Φ ₁₄ , Φ ₁₅ , Φ ₁₆ (Φ ₂₄ , Φ ₂₅ ,
Φ ₂₆ ). The contents of the data memory in Table 2 are the 8 × 8 Hadamard matrix (Hadamad matrix) for use in the Hadamard transform or inverse Hadamard transform.
rd matrix).

In the thus configured data transmission apparatus, the transmission apparatus 1 (FIG. 1) uses the input circuit to encode the input data.
Was used to convert the composite waveform S1 ₆ of a plurality of frequencies corresponding to the input data, to limit the band of frequencies in the LPF circuit 11, the modulation circuit 12, for example, subjected to FM modulation, the transmission line L ₁₂
To send to. In this encoding, the input data signal (8 bits) to be transmitted is converted into an inverse Hadamard transform (8 × 8) using Table 2.
8) and repeat the process of generating the time waveform of one frame. Details of data processing for one frame will be described below with reference to the operation of the encoding circuit 10 in FIG.

The inverse Hadamard transform can be realized by performing "convolution operation" in Table 2 with the input data. For example, if the row address signal of the data memory 102 is Φ ₁₁ = 0, Φ
_{When 12} = 1 and Φ ₁₃ = 0, the signal S sequentially read from the beginning of the second row of the data memory 102 in which the Hadamard matrix of Table 2 is recorded.
₁₂ and the input data signal S _{1 1} selected by the data selector 101
Is multiplied by the multiplier 103, and the output signal S ₁₃ of the multiplier 103 and the output data signal S ₁₅ of the latch register 105 are added by the adder 104. More repeated 8 times, after the last output signal S ₁₅ of the latch register 105 is latched at the rise of the [Phi ₁₉ to the D / A converter 106, and the .phi.1 ₈ to L level, the latch register
Clear the contents of 105 to zero. The above procedure is repeated eight times in each column of Table 2 to generate the output signal S ₁₆ of one frame.

In the receiver 2, the signal received from the transmission line is demodulated by the demodulation circuit 22, for example FM demodulation, the LPF circuit 21 extracts only the baseband signal S ₂₁ of the required frequency band, and the decoding circuit 20 outputs the signal S. _The frequency component contained in ₂₁ is analyzed, and the output data corresponding to the above-mentioned frequency is generated.
In this decoding, the received baseband signal S ₂₁ is subjected to Hadamard transform (8 × 8) from the time waveform of one frame using the Hadamard matrix of Table 2, and the input data signal corresponding to each frequency component is frame by frame. To generate. Details of data processing for one frame will be described below with reference to the operation of the decoding circuit 20 in FIG.

The analog signal S input to the decoding circuit 20
₂₁ is sampled by the A / D converter 201 at each rise of Φ ₂₀ , and eight pieces of data S ₂₂ are recorded in the FIFO 203 in one frame of the analog signal S ₂₁ . The Hadamard transform can be realized by performing “convolution operation” in Table 2 with input data and then dividing by 8 as in the case of encoding. For example, if the row address signal of the data memory 202 is Φ ₂₁ =
When 0, Φ ₂₂ = 1 and Φ ₂₃ = 0, the signal S ₂₃ read sequentially from the beginning of the second row of the data memory 202 storing the Hadamard matrix of Table 2 and the input data signal S read from the FIFO 203
_{22 ′} is multiplied by the multiplier 204, and the output signal S ₂₄ of the multiplier 204 and the output data signal S ₂₆ of the latch register 206 are added by the adder 205. Repeat the above 8 times, and finally latch register 2
The signal S obtained by dividing the output signal S _{26 of} 06 by the 1/8 frequency divider 207 by 1/8
_{After 27} is shifted into the S / P converter 208 by one data at the rising edge of Φ ₂₉ , Φ _{28 is set} to L level and the contents of the latch register 206 are cleared to zero. 8 in the order of each column in Table 2
Repeats 8 times and outputs 8-bit data as data output terminals O ₂₁ , O
_It outputs from ₂₂ , O ₂₃ , O ₂₄ , O ₂₅ , O ₂₆ , O ₂₇ , and O ₂₈ . The data processing timing generator 209 is assumed to operate by taking frames and synchronization of the input signal S ₂₁ as in FIG. 5, description thereof is omitted for a frame synchronization method here.

The above-described embodiment can be implemented in the same manner even if it is modified as follows. It can also be applied to the case where an integrated circuit such as a gate array having the above-described circuit function is used for realizing the circuit. The number of elements of the Hadamard transform matrix is 8 × 8 or more, and a power of 2 can be similarly applied.

A / D, D / A, a multiplier, and an adder as the number of bits of the encoding circuit and the decoding circuit can be similarly applied if they have 4 bits or more. Since the input of the multiplier is 1 bit, it can be configured by a combination of simple gates (AND, OR, NOT). The number of bits of input data and output data other than 8 bits can be similarly applied (however, the same as the number of rows or columns of the Hadamard transform matrix).

Modulation (AM or PM) or non-modulation (baseband) other than FM as the modulation circuit and demodulation circuit
However, the same can be applied. The same applies to transmission lines (wireless or infrared) other than wired transmission lines. In addition, the above-described exemplary embodiments include a remote controller and a PCM.
It can be diverted to voice transmission equipment.

[0032]

According to the data transmission apparatus of the present invention, in a wired transmission line with no limitation on the frequency band to be used, infrared rays or the like, frequency multiplexing is performed by using a Hadamard function instead of a sine wave. Adder, A / D, D / A
The number of bits of the converter can be reduced, and the multiplier can be composed of a simple gate. In addition, the circuit scale that can be realized is small, such as the data memory capacity is small, it can be realized at low cost, and data transmission that is resistant to noise and multipath is possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a system configuration example of a data transmission device according to the present invention.

FIG. 2 is a block diagram showing an encoding circuit in a data transmission device according to the present invention.

FIG. 3 is a block diagram showing a decoding circuit in a data transmission device according to the present invention.

FIG. 4 is an explanatory diagram showing the operation of the encoding circuit in the data transmission device according to the present invention.

FIG. 5 is an explanatory diagram showing the operation of the decoding circuit in the data transmission device according to the present invention.

FIG. 6 is a block diagram showing a system configuration example of a conventional data transmission device.

FIG. 7 is a block diagram showing an encoding circuit of a conventional data transmission device.

FIG. 8 is a block diagram showing a decoding circuit of a conventional data transmission device.

FIG. 9 is an explanatory diagram showing an operation of an encoding circuit in a conventional data transmission device.

FIG. 10 is an explanatory diagram showing the operation of a decoding circuit in a conventional data transmission device.

[Explanation of symbols]

 1 ・ ・ Transmission device 2 ・ ・ Reception device 10 ・ ・ ・ ・ ・ Encoding circuit 20 ・ ・ ・ ・ ・ Decoding circuit

Claims (1)

[Claims] 1. A coding circuit using inverse Hadamard transform (1
A data transmission device comprising: a transmission device (1) having 0) and a reception device (2) having a decoding circuit (20) using Hadamard transform.