JP3183791B2 - Digital signal processor and digital signal modulator using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processor and a digital signal modulator using the same, and more particularly, to a digital signal processor for performing a fast Fourier transform or an inverse fast Fourier transform of a digital signal, and a digital signal processor using the same. Obtain orthogonal frequency multiplexed signal by using as modulator
It relates to a digital signal modulation system.

[0002]

2. Description of the Related Art Discrete Fourier transform of digital signal processing
(DFT: Discrete Fourier Transform) and Inverse Discrete Fourier Transform (IDFT) are used in various places.

For example, orthogonal frequency division multiplexing (OFDM: O
In a digital transmission system using the rthogonal Frequency Division Multiplex (multiplex) system, a main process in a modulation unit on a transmission side is an inverse discrete Fourier transform, and a main process in a demodulation unit on a reception side is a discrete Fourier transform. This OFDM
Regarding the method, for example, “VIEW” Vol. 12 No. 3
pp. 1-6 (1993), "Mobile Digital Audio Broadcasting Using OFDM" and "EBU Review-technica".
l "No.224, pp.47-69 August (1987)" P.
rinciples of Modulation and Channel Coding for
Digital Broadcasting for Mobile Receiver "and the like.

Normally, the number of operations such as the sum of products required for the discrete Fourier transform increases exponentially according to the number N of samples in one cycle, and the time required for the operation becomes enormous. Several algorithms have been proposed in which the number of operations required for this operation is greatly reduced. In general, a fast Fourier transform (FFT: FFT) has been proposed.
ast Fourier Transform), inverse fast Fourier transform (IF
FT: Inverse Fast Fourier Transform.

[0005] However, even if such a fast Fourier transform algorithm is used, an extremely high-speed operation clock is required to complete all calculations in a short time. For example, in order to perform Fourier transform with 1024 sample points N within about 100 μsec, it depends on the number of bits of the signal expression.
MHz or higher is required.

One reason for this is that, generally, a digital signal processing device that executes a fast Fourier transform or an inverse fast Fourier transform in real time has an N corresponding to one cycle.
One point is that the complex signals (samples) at points are sequentially input one by one, and the complex signals at N points corresponding to this one cycle are sequentially output one by one.

[0007]

Since the above-mentioned OFDM system is suitable for mobile reception, it is considered to be used for transmission to mobiles such as television broadcasts. In this case, video information, audio information, data, and the like are transmitted collectively, and a high transmission rate of at least several tens of Mbps must be realized. For example,
The number of OFDM carriers is 2048, and one symbol is 1
When transmission is performed at 00 μsec and 4-bit transmission is performed for each carrier, transmission at about 80 Mbps can be performed.

However, such a technique has the following problems.

First, in order to modulate and demodulate a digital signal of a high transmission rate as shown in the above example by the OFDM method, the number of sample points N = 2048.
, The inverse fast Fourier transform or the fast Fourier transform must be performed within 100 μsec.

In order to cope with the OFDM format signal corresponding to such a high transmission bit rate, an inverse fast Fourier transform unit or a fast Fourier transform unit, an external memory necessary for generating the OFDM signal, and an external memory necessary for generating the OFDM signal are provided. Of course, a high operating frequency is also required for a control unit for controlling an address of a memory and the like.

In particular, in the case of such a high operating frequency, if there is a factor such as a long connection length of each processing unit, the timing shift is caused, the operation becomes unstable, and the obtained signal is distorted. This causes a problem that a required signal cannot be obtained.

By the way, one of the features of the OFDM transmission signal is as follows.
One is that one transmission symbol consists of an effective symbol period and a period called a guard interval. The guard interval can be regarded as a signal period provided to reduce the influence of multipath in terms of a transmission system, and is physically a cyclically repeated signal waveform in an effective symbol period. . The guard interval signal is transmitted prior to the effective symbol.

The signal of the effective symbol can be generated using an inverse discrete Fourier transform or an inverse fast Fourier transform. That is, the input signal on the modulation side is G (n) (where n =
.., N−1), the modulated output signal g (k) (where k = 0, 1,..., N−1) is represented by the following equation.

[0014]

(Equation 1)

A signal corresponding to the guard interval is a signal g (NM), g (NM + 1), g (NM + 1) of the last M samples of the output signal g (k) given by the above equation (1).
.., G (N−1). Therefore, OFD
As shown in FIG. 3, the M transmission signal is a signal having a format in which a signal corresponding to the guard interval is circulated.

Therefore, as a second problem, the signal of the guard interval must be transmitted prior to the effective symbol as described above. To realize this, the conventional inverse fast Fourier transform is performed. In such a digital signal processing apparatus, the output signal for one cycle must be temporarily stored in an external memory. This is because the output signals of the inverse fast Fourier transform are obtained in the order of g (0), g (1),.

That is, the guard interval signal g (N-
In order to obtain signals from M), g (N−M + 1),..., A signal for one cycle subjected to the inverse fast Fourier transform is temporarily stored in an external memory, and a part to be used as a signal of the guard interval is firstly obtained. Reading, and when this reading is completed, a signal corresponding to an effective symbol is subsequently read and transmitted.

For this reason, there is a problem that a certain time delay occurs in order to obtain one transmission symbol as a modulation signal of the OFDM system.

A first object of the present invention is to solve the above-mentioned problems, to eliminate a timing deviation of each signal even at a high operating frequency, and to obtain a required signal in a stable operation. And modulation equipment using this
To provide a location .

A second object of the present invention is to provide a digital signal processing device capable of obtaining a signal of the OFDM system with a reduced time delay, and a modulation device using the same.

[0021]

In order to achieve the first object, the present invention provides an inverse fast Fourier transform unit or a fast Fourier transform unit to which an input signal is supplied, and an inverse fast Fourier transform unit or a fast Fourier transform unit. A first memory for temporarily storing an output signal of the conversion unit and a control unit for controlling an address of the first memory are integrated in one IC circuit.

In order to achieve the second object, the present invention multiplies an input signal by a complex sine wave stored in a second memory in advance, and performs an inverse fast Fourier transform or a fast Fourier transform on the result. At the same time as outputting the output signal directly, the output signal is also stored in the first memory as necessary, and the output of the inverse fast Fourier transform unit or the fast Fourier transform unit is stored in the first memory. Output immediately after the process is completed.

In order to achieve the second object,
According to the present invention, when an input signal is input to an inverse fast Fourier transform unit or a fast Fourier transform unit in the bit reverse order, the complex is obtained by rearranging the input signal in the bit reverse order stored in the second memory in advance. The sine wave is multiplied, and then the inverse fast Fourier transform or the fast Fourier transform is performed. The output signal is directly output, and at the same time, stored in the first memory, if necessary, and stored in the first memory. The signal is output immediately after the output of the inverse fast Fourier transform or the fast Fourier transform is completed.

[0024]

At least an inverse fast Fourier transform unit or a fast Fourier transform unit, a first memory for temporarily storing an output signal of the inverse fast Fourier transform unit or the fast Fourier transform unit, and a first memory By integrating the control unit for controlling the address and the like into one IC circuit, it is possible to prevent the connection length between them from becoming unnecessarily long, and it is difficult for clock timing deviation to occur even in high-speed operation. Become. Therefore, a stable operation can be obtained, and a required signal can be obtained.

After multiplying by an appropriate complex sine wave in advance,
By performing the inverse fast Fourier transform or the fast Fourier transform, this output signal can be made one cycle from the head signal of the required guard interval. As a result, the time delay that occurs to obtain one transmission symbol as an OFDM modulated signal can be reduced.

Incidentally, the input signal to the inverse fast Fourier transform unit or the fast Fourier transform unit may be in the bit reverse order in order to make the output signal the correct order. In this case, a correct result can be obtained by setting the order corresponding to the complex sine wave to be multiplied.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. First, referring to FIG. 1, a digital signal processor according to the present invention will be described.
The basic configuration of the processing device will be described. In addition, 10 is FF
T (fast Fourier transform) units, 11a and 11b are complex conjugate units, 12 is a memory, 13 is a control unit, 14 is an information signal input terminal, 15 is an output terminal, 16 is a control signal input terminal,
17 is a clock input terminal, 18a, 18b, 19a,
19b is a changeover switch.

In the figure, an input signal G (n) for one symbol (ie, one cycle) to be modulated (where n =
.., N−1, and N is a positive integer.
(Several tens or more) is input from the signal input terminal 14. Further, a control signal is supplied from the input terminal 16 to the control unit 13, whereby the control unit 13
a, 18b, 19a, 19b switching control and FFT unit 1
Control such as the operation start time of fast Fourier transform by 0 is performed.

The digital signal processing device 1 operates based on a clock signal input from the input terminal 17.

The input signal G (n) is obtained by the inverse Fourier transform.
When the modulation is performed, the control unit 13 switches the changeover switches 18a, 18b, 19a, and 19b to the A side. As a result, the input signal G (n) is supplied to the complex conjugate unit 11a via the changeover switch 18a to generate the complex conjugate signal G * (n), and this complex conjugate signal G *
(n) is supplied to the FFT unit 10 via the changeover switch 18b. In the FFT unit 10, this complex conjugate signal G *
(n) is fast Fourier transformed. The output signal of the FFT unit 10 is supplied to a conjugate complex unit 11 via a changeover switch 19a.
b, and its complex conjugate signal is generated.

Such a series of processing operations is performed by the input signal G (n).
Can be regarded as being subjected to the inverse fast Fourier transform. As a result, the conjugate complex part 11b outputs the inverse fast Fourier transformed signal g (k) (where k = 0, 1,..., N−1).

The output signal g (k) of the conjugate complex unit 11b is g
(0), g (1), g (2),... Are temporarily stored in the memory 12 via the changeover switch 19b under the control of the control unit 13.

Now, assuming that the samples corresponding to the guard interval are M samples of g (N−M), g (N−M),..., G (N−1). G (N−M), g (N−M + 1),..., G (N
After the samples are read out in the order of -1) and the reading of the guard interval signal is completed, subsequently, the samples g (0) to g (N-1) are output as one effective symbol signal.
Are read out and output from the output terminal 15.

In this way, the input signal G (n) is subjected to inverse fast Fourier transform as shown in the above equation 1, and the resulting signal g (k) is used to generate an OFDM signal having the form shown in FIG.
One transmission symbol of the scheme is obtained.

The values of N and M can be arbitrarily set by the control unit 13 in accordance with a control signal input from the input terminal 16.

Here, the symbol rate of the OFDM system is 10k symbols / sec, and the number of samples in one cycle N =
Assuming that 4096, even if independent parallel data buses are used for the real part and the imaginary part, respectively, the transmission rate of the FFT unit 10 and the complex conjugate unit 11b and the transmission of data from the complex conjugate unit 11b to the memory 12 will be described. The rate is over 40 Mbps. In the case where the real part and the imaginary part are serially transmitted alternately, the transmission speed is twice as high as 80 Mbps or more.

At such a high transmission rate, if the wiring length between the complex conjugate part 11b and the memory 12 is unnecessarily long, data transmission becomes unstable. That is, the FFT unit 10
When the memory and the memory 12 are realized by independent integrated circuits, such a problem occurs.

However, here, at least all the components shown in FIG. 1 are integrated and integrated into one IC (integrated circuit). As a result, the wiring length between the components becomes sufficiently short, and high-speed data transmission is performed stably.

The number of samples in one cycle N = 4096,
In order to represent both the real part and the imaginary part with 32 bits, the capacity required for the memory 12 is 256 kbits.

In FIG. 1, when the modulation of the OFDM system is defined by the fast Fourier transform instead of the inverse fast Fourier transform, the changeover switches 18a, 18b and 19 are used.
What is necessary is just to switch a and 19b to B side, respectively.

FIG. 2 is a block diagram showing an embodiment of a digital signal processing apparatus according to the present invention. Reference numeral 21 denotes a complex multiplier, 22 denotes a memory, and portions corresponding to those in FIG. A duplicate description will be omitted.

In the figure, an input signal G (n) for one symbol to be modulated, which is input from an input terminal 14, is supplied to a complex multiplier 21. On the other hand, the memory 22 has N
Complex sine waves exp (−j2πMn / N) (where M (<
N) stores the number of samples at the guard interval (FIG. 3)), and the complex multiplier 21 stores each input sample G (0), G (1),..., G (N-1). Each time it is supplied, the complex sine wave exp
(0), exp (−j2πM / N),..., Exp (−j2πMn
/ N) is read out and the product of the corresponding input sample G (i) and the complex sine wave exp (−j2πMi / N) (where i =
0, 1,..., N-1).

Here, G (n) and g (k) represent the input signal and the output signal, respectively, and G (i) and g (i) represent the respective samples of the input signal and the output signal, respectively. Shall be.

In this embodiment as well, when the signal is modulated by the inverse fast Fourier transform shown in the above equation (1), the changeover switch 1 is provided in the same manner as in the embodiment shown in FIG.
8a, 18b, 19a, and 19b close to the A side.

Also in this embodiment, at least all the components shown in FIG. 2 are integrated and integrated into one IC (integrated circuit). As a result, the wiring length between the components becomes sufficiently short, and high-speed data transmission is performed stably.

By a series of operations of the complex conjugate unit 11a, the FFT unit 10, and the complex conjugate unit 11b, the output signal of the complex multiplier 21 is subjected to inverse fast Fourier transform. An output signal h (k) is obtained.

[0047]

(Equation 2)

Here, from the periodicity of g (k), k−M <
If 0,

[0049]

(Equation 3)

Is as follows. Therefore, the first M signals h (0), h (1),..., H (M−1) of h (k) are
The previous sample g (NM), g (NM + 1), ..., g
(N-1). Accordingly, a guard interval signal required in the OFDM system can be obtained from the beginning as the output h (k).

FIG. 4 shows the signal g (k) and the signal h
It shows the correspondence of the sample with (k).

The control section 13 performs the following control on the output signal h (k) of the complex conjugate section 11b expressed by the above equation (2).

The M samples h (0), h (1),..., H (M−1) from the beginning of the output signal h (k) are output to the output terminal 1.
5 and is also stored in the memory 12 at the same time. The remaining (N−M) samples h (M), h (M + 1),.
.., H (N-1) are subsequently output from the output terminal 15, but need not be stored in the memory 12 (of course, if there is a memory capacity, the storage has no effect). A series of N samples h (0), h (1),..., H (N-1)
, All the samples h (0), h (1),..., H (M-1) are read from the memory 12 and output from the output terminal 15.

By the above operation, one transmission symbol of a required OFDM signal as shown in FIG. 3 can be obtained.

In this embodiment, since the signal corresponding to the guard interval is obtained from the beginning, there is no time delay caused by temporarily storing the signal in the memory 12 and then reading it out again. Be shortened.

As the memory 12, a FIFO (Fi
A rst In First Out) N-step delay unit may be used.

In some cases, the input signals from the input terminal 14 may be in the bit reverse order. In such a case, it is needless to say that the read contents of the memory 22 are set in advance so as to correspond to the bit reverse order.

FIG. 5 is a block diagram showing one embodiment of a digital signal modulation apparatus according to the present invention using the embodiment shown in FIG. 2. Reference numeral 50 denotes an OFDM modulator, and 52a and 52.
b and 52c are information source coding units, 53 is a multiplexer,
54 is a communication channel coding unit, 55 is a time base, 56 is a transmission system controller, 57 is a D / A conversion unit, 58 is an LPF (low-pass filter), 59 is a frequency conversion unit, 6
0 is a high-frequency amplifier, 61 is an antenna.

This embodiment uses the OFDM system as its modulation system.

In the figure, input video information, audio information and data are input to information source coding sections 52a, 52b, 52b, respectively.
53c, and is subjected to appropriate information source coding such as MPEG. These source-coded signals are supplied to a multiplexer 53 and multiplexed into one signal sequence. The multiplexed signal is converted into a channel coded signal to which redundancy is added by a channel coder 54 using a block code or a convolutional code so as not to be affected by noise or the like generated on a transmission line.

The channel coded signal is subjected to required modulation by the OFDM modulator 50 of the embodiment shown in FIG. 2, and is converted to an analog signal by the D / A converter 57. This analog signal is processed by a frequency converter 59 and a high-frequency amplifier 60 after unnecessary harmonics and the like are suppressed by the LPF 58, and transmitted as an OFDM modulated signal from the antenna 61.

The multiplexer 53 and the OFDM modulator 50 operate on the basis of a clock signal from the time base 55 and a control signal from the transmission system controller 56.

In this embodiment, OFD which is a main component
Since the digital signal processing apparatus shown in FIG. 2 is used as the M modulator 50, the inverse fast Fourier transform can be performed stably even at a high bit rate, and the distortion-free OF is performed.
A DM modulation signal can be obtained.

Since no extra time is required to generate a guard interval, the information source coding unit 52
a, 52b, and 52c after each information is input.
The time required to obtain a modulated signal is also reduced.

FIG. 6 shows the digital signal processing device shown in FIG.
FIG. 7 is a block diagram showing an example of a digital signal demodulation device using a device , where 70 is an OFDM demodulation unit, 71 is an antenna,
72 is a channel selector, 73 is an intermediate frequency amplifier, 74
Is a frequency converter, 77 is an LPF, 78 is an A / D converter,
82 is a communication path decoding unit, 83 is a demultiplexer, 84
Reference numerals a, 84b, and 84c denote an information source decoding unit, 75 denotes a carrier reproduction unit, 76 denotes a timing control unit, 80 denotes a clock generation unit, and 81 denotes a reception system controller.

This digital signal demodulator also has an OFDM
The modulation method is used as the modulation method.

In the figure, a channel selection section 72 selects a modulation signal of a required channel from a modulation signal received by the antenna 71 and converts it to an intermediate frequency signal. This intermediate frequency signal is amplified by the intermediate frequency amplifier 73, and is converted into a low band signal by the carrier from the carrier reproducing unit 75 by the frequency converting unit 74. This low-frequency signal, after unnecessary harmonics and noise are suppressed by the LPF 77,
The digital signal is converted by the A / D converter 78. The sampling timing at this time is determined by the timing control unit 7.
6.

This digital signal is demodulated by the OFDM demodulation unit 70 and further decoded by the communication channel decoding unit 82.
The output signal of the channel decoding unit 82 is supplied to a demultiplexer 83, where it is separated into video components, audio components, data components, and the like. Then, each component is used as an information source decoding unit 8.
At 4a, 84b and 84c, required video information, audio information and data are decoded.

Here, the digital signal processor 1 shown in FIG. 1 is used as the OFDM demodulator 70.
In this case, in FIG. 1, the changeover switches 18a, 18
b, 19a, and 19b are each switched to the B side, and the complex conjugate units 11a and 11b are not used. Thus, the fast Fourier transform in the forward direction is performed by the OFDM demodulation unit 70.

The OFDM demodulation section 70, carrier reproduction section 75, timing control section 76, and the like are controlled by a control signal from the reception system controller 81 and a clock signal from the clock generation section 80.

In this digital signal demodulator ,
Since the digital signal processing device shown in FIG. 1 is used as the OFDM demodulation unit 70 constituting the main configuration, a fast Fourier transform is performed stably even at a high bit rate, and an OFDM demodulated signal without distortion can be obtained. .

[0072]

As described above, according to the digital signal processing apparatus of the present invention, in order to perform high bit rate transmission, IFFT or fast Fourier transform required for OFDM modulation or demodulation is performed. It is possible to stabilize high-speed operation and obtain a desired signal without distortion.

Further, according to the digital signal processing apparatus of the present invention, no extra time is required to generate an OFDM guard interval, and a signal necessary to obtain one transmission symbol as an OFDM modulated signal is not required. Delay time can be reduced.

Further, according to the digital signal modulation apparatus of the present invention, the inverse fast Fourier transform is performed stably even at a high bit rate, and an OFDM modulated signal without distortion can be obtained. , The delay time required to obtain can be reduced.

[0075]

[Brief description of the drawings]

FIG. 1 shows the basic structure of a digital signal processing device according to the present invention.
It is a block diagram showing composition .

One embodiment of the digital signal processing apparatus according to the invention, FIG
It is a block diagram showing an example .

FIG. 3 is an explanatory diagram of a configuration of a transmission symbol of the OFDM scheme.

FIG. 4 is an operation explanatory diagram of the embodiment shown in FIG. 2;

FIG. 5 is a block diagram showing an embodiment of a digital signal modulation device according to the present invention.

FIG. 6 shows a digital signal processing apparatus shown in FIG .
FIG. 2 is a block diagram illustrating a configuration of a digital signal demodulation device .

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 FFT part 11a, 11b Complex conjugate part 12 Memory 13 Control part 14 Information signal input terminal 15 Information signal output terminal 16 Control signal input terminal 17 Clock input terminal 18a, 18b, 19a, 19b Changeover switch 21 Complex multiplier Reference Signs List 22 memory 50 OFDM modulator 52a, 52b, 52c information source encoder 53 multiplexer 54 communication path encoder 55 time base 56 transmission system controller 57 D / A converter 58 low-pass filter 59 frequency converter 60 High frequency amplifier 61 Antenna 70 OFDM demodulation unit 71 Antenna 72 Channel selection unit 73 Intermediate frequency amplifier 74 Frequency conversion unit 75 Carrier regeneration unit 76 Timing control unit 77 Low-pass filter 78 A / D conversion unit 80 Clock generation unit 81 Receiving system control 82 channel decoding section 83 a demultiplexer 84a, 84b, 84c information source decoding unit

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takashi Okubo 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Video Media Research Laboratory, Hitachi, Ltd. (56) References JP-A-6-51795 (JP, A) JP-A-6-224869 (JP, A) JP-A-5-83218 (JP, A) JP-A-6-261019 (JP, A) JP-T-62-502932 (JP, A) (58) Int.Cl. ⁷ , DB name) H04J 11/00

Claims (4)

(57) [Claims] 1. N, M (where N>M>)
0), N complex sine waves exp (−j2πMi)
/ N) (where i = 0, 1,..., N-1), or
A first memory that outputs coefficients obtained by rearranging them in the bit reverse order, a multiplier that multiplies each sample of the input signal by a coefficient output from the first memory, and at least one of output signals of the multiplier An inverse fast Fourier transform unit or a fast Fourier transform unit for performing an inverse fast Fourier transform or a fast Fourier transform of N (> 0) samples, and one of the outputs of the inverse fast Fourier transform unit or the fast Fourier transform unit Second for temporarily storing part or all
, The inverse fast Fourier transform unit or the fast Fourier transform unit, the first memory, the second memory, and a control unit for controlling the multiplier. Digital signal processor. 2. The integrated circuit according to claim 1, wherein at least the inverse fast Fourier transform unit or the fast Fourier transform unit, the first and second memories, the multiplier, and the control unit are integrated into one integrated circuit. A digital signal processing device characterized in that: 3. The method according to claim 1, wherein, under the control of the control unit, N (> 0) samples of the input signal are multiplied by a coefficient output from the first memory by the multiplier. An inverse fast Fourier transform or a fast Fourier transform of the N-point samples is performed on the multiplication result by the inverse fast Fourier transform unit or the fast Fourier transform unit. At least the first M (N>M> 0) samples of the output result from the inverse fast Fourier transform unit or the fast Fourier transform unit are stored in the second memory, and the inverse fast Fourier transform unit or the fast Fourier transform unit The conversion unit outputs the output results of the (N−M) points subsequent to the sample of the M points, outputs the output results of all the N points, and subsequently stores the output results at least in the second memory. Digital signal processing apparatus and outputting read the value of M points were. 4. A digital signal using orthogonal frequency multiplexing.
4. A signal modulation device according to claim 1 , wherein at least a modulation unit is provided.
Using any one of the digital signal processors
Digital signal modulator characterized by the above-mentioned.