JPH09153299A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To embody the detection of the marginal defect of a semiconductor memory device in a short period of time. SOLUTION: A static random access memory has an address transition detection circuit 9 which detects the change in an address signal and generates a pulse A of a prescribed width and a pulse generating circuit which generates a pulse B for determining the activation period of memory cells by receiving this pulse A. The memory described above has a switching means for disconnecting the capacitance constituting an autopower down signal generating circuit 11 at the time of a test mode, thereby making the pulse width of the pulse B shorter by tc than the pulse width at the time of an ordinary mode. The setting of the severer timing condition is thereby made possible. Then, the detection of the marginal defect in the short period of time is made possible without using a test pattern.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, particularly a static random access memory (hereinafter referred to as SRA).
Regarding M), the present invention relates to a test method and a test circuit for shortening the test time for detecting defects.

[0002]

2. Description of the Related Art As a conventional technique for testing a semiconductor memory device, a technique disclosed in Japanese Patent Laid-Open No. 3-154288 has been proposed. This conventional technique will be described with reference to FIGS. 1 and 2. The aforementioned public patent information (A)
Although a DRAM is described as an example in Japanese Patent Laid-Open No. 3-154288, a static RAM (hereinafter referred to as SRAM) will be described as an example here. FIG. 1 is a simplified diagram of a circuit diagram around a memory cell of a conventional SRAM. Memory cell A0
37-40 are N-channel MOSFETs (hereinafter referred to as N-channel MOSFETs).
MOS), and 41 and 42 are high resistance loads. 43
Is a word line. Reference numerals 44 and 45 are bit lines b and / b for reading data from the memory cell, and the NMOS 39 and
40 sources, respectively. A bit line load circuit 46 is connected to the bit lines b and / b. N
The MOSs 47 and 48 are column gates, the sources and drains of which are connected to the bit line 44, the data bus 50 and the bit line 45, and the data bus 49, respectively, and the gates are controlled by the column selection signal Φ1. Reference numeral 51 denotes a sense amplifier, which is connected to the data buses 49 and 50. 52
Is a control signal output means for receiving the signal Φ and generating the signal Φ1. The configuration of the SRAM in FIG. 1 has been described above.

Next, the operation will be described with reference to FIG.

First, in the operation in the normal mode, the word line 43 rises to "H", and data is read from the memory cell A0 to the bit lines 44 and 45 precharged and equalized by the bit line load circuit and the equalize circuit 46. A potential difference is generated between the bit lines 44 and 45. At the same time, by inputting the external input signal Φ to the control signal output means 52, the control signal Φ1 rises to the VDD level and the column selection gates NMOS 47 and 48 are turned on at the same time. At this time, since Φ1 is at the “H” level, the NMO
S47 and S48 are completely turned on. After that, the data is read to the data buses 49 and 50 from the bit lines 44 and 45 through the column selection gates 47 and 48, and the potential difference ΔVdb from the data buses 49 and 50 is obtained. Then, it is amplified by the sense amplifier 51 and output.

Next, in the test mode, the word line 4
3 rises to "H", precharges from the memory cell A0 by the bit line load circuit and the equalize circuit 46,
Data is read to the equalized bit lines 44 and 45, and a potential difference is generated on the bit lines 44 and 45. At the same time, by inputting the external input signal Φ to the control signal output means 52, the control signal Φ1 rises to the intermediate level ½ VDD and the column selection gates NMOS 47 and 48 are turned on at the same time. At this time, since Φ1 is at the intermediate level, V
As compared with the DD level, the NMOS 47 and 48 are not completely turned on, so that the transmission capability is deteriorated. Therefore, the potential difference between the data buses 49 and 50 is smaller than the potential difference between the bit lines 44 and 45 and is ΔVdb ′. If the potential difference ΔVdb ′ between the data buses 49 and 50 is equal to or lower than the detection sensitivity of the sense amplifier, the sense amplifier 51 does not normally amplify the signal and malfunctions. In this way, the test is performed by determining the quality of the output data. That is, it is possible to detect a memory cell that does not have a sufficient operation margin.

[0006]

In recent years, 1M, 4M, 1
Since the capacity of 6 Mbits and static random access memory has been increased, the test time has been increased to 4 times and 16 times accordingly, which is a very big problem from the viewpoint of cost. In the conventional static random access memory, the unbalance of the transistors in the memory cell due to mask shift or the like, the storage node potential of the memory cell becomes worse than the normal memory cell due to parasitic resistance, etc., and the potential difference of the bit line cannot be obtained sufficiently. In order to detect an access delay due to such a marginal cell defect, an increase in the resistance of the word line, a defect in the sense amplifier characteristic, etc.
N ^3/2 series, N ² series patterns, etc. are used. For example, 1
MSRAM (128K × 8, 17 addresses, N =
2 ¹⁷ ) and 4 MSRAM (512K × 8, address 19
7 and N = 2 < ¹⁹ >), data is written in one set of memory cells, and a read test requires 100 ns for one condition. A comparison is shown in FIG. As can be seen from this table, it can be seen that as the storage capacity increases and the pattern having the higher detection capability is used, the test time becomes extremely long.

Therefore, although the proposal shown in the prior art has been made, in the case of the prior art, the control signal output for setting the control signal Φ1 to the intermediate level (the intermediate between Vth of the NMOS 47 and 48 and the power supply potential VDD). At the same time that the means 25 is required, a very delicate adjustment is required when conducting a test at low voltage operation, which makes the circuit design complicated.

Therefore, an object of the present invention is to provide a semiconductor memory device capable of detecting marginal cells easily and in a short time.

[0009]

An address transition detection circuit having a plurality of static memory cells arranged in a matrix and detecting a change in an address signal and generating a pulse A having a predetermined width is provided. A static random access memory having a pulse generation circuit that receives the pulse A and generates a pulse B that determines a memory cell activation period. In a test mode, the pulse width of the pulse B is made shorter than that in the normal mode. Is characterized by.

And a switch means for disconnecting the capacitor constituting the timer circuit for determining the pulse width of the pulse B in the test mode.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described with reference to FIGS. 3, 4, 5, and 6. FIG. 3 is a block diagram of the static random access memory in this embodiment. 1 is a memory cell group, 2 is a bit line load circuit and an equalize circuit. Reference numeral 3 is a row selection decoder, and 4 and 8 are column selection gates and column selection decoders. 5 is a sense amplifier, 6
Is a data latch circuit, and 7 is an input / output buffer. Reference numeral 9 is an address transition detection circuit and 10 a control circuit. 11, 1
Reference numeral 2 denotes an auto power down signal generation circuit (hereinafter referred to as an APD signal generation circuit) and a control circuit. Ax0 to Axi are X address signals, and Ay0 to Ayj are Y address signals. FIG. 2 shows an embodiment of an automatic power down signal (hereinafter referred to as APD signal) generation circuit. Reference numerals 13 to 17 are delay inverters, and 20 to 22 are P channel type MOs.
SFET (hereinafter PMOS) and 23 to 25 are N-channel MOSFETs (hereinafter NMOS). 26-28 is P
MOS, 19 and 30 are NMOSs, and their gates are used as capacitors. Reference numerals 18 and 33 are inverters. The signal tst is a test mode / normal mode switching signal. FIG. 4 is an example of the APD signal generation circuit of the present embodiment, and FIG. 5 is a timing chart of the present embodiment. The solid line shows the one in the normal mode and the dotted line shows the present embodiment.

It is assumed that the signal tst is in the logic "H" state, that is, in the normal mode. Address signal Ax0
When any one of Axi and Ay0 to Ayj or a plurality of them change, a pulse is generated by the address transition detection circuit 9 (hereinafter referred to as an ATD pulse). The ATD pulse “H” is input to the timer circuit IN. At this time, the potential of the node 1 rises from the logic "L" to the logic "H" in response to the ATD pulse. At the same time, PMOS
In order to charge and discharge the node between the delay inverters at high speed by 20, 21, 22 and NMOSs 23, 24, 25,
The level of node 2 rises to logic "H". At this time, the output of NOR31 becomes logic "L". Eventually, the ATD pulse falls to logic "L" after time t.
At the same time, the PMOS 20, 21, 22, NMOS 23,
24 and 25 are turned off, and charging / discharging of the node between the delay inverters is stopped. As mentioned above, the PMOS
The gates of 26 to 28 and the NMOSs 19 and 30 are gate capacitors connected to the nodes between the delay inverters.
The delay time between the delay inverters depends on the gate capacitance connected to this delay inverter and the NMO forming the next stage delay inverter.
It is determined by the gate capacitance of S, PMOS, wiring capacitance and wiring resistance. Here, the delay time from the input IN to the node 2 is td. The node 2 changes to the logic "L" after the delay of the time td after the time t. The NOR 31 further outputs the logic "L" for the time td at the logic "L" of the node 1 and the logic "H" of the node 2. In other words, this A
The output of the PD signal generating circuit is the pulse width t + t of logic "L".
The APD signal of d is generated. APD signal is control circuit 1
It is input to the row selection decoder 3, the column selection decoder 8, the bit line equalize and precharge circuit 2, the sense amplifier 5, and the data latch circuit 6 via 2.

Address signals Ax0-Axi and Ay0-Ay
When j is input to the row selection decoder 3 and the column selection decoder 8 and the APD signal is logic "L", the word line and the column selection gate corresponding to the address signal are selected (however, the APD signal is logic "L"). It is assumed that precharge and equalization of the bit line have been completed at the time of "H").

After the word line is selected, data is read from the corresponding memory cell via the bit lines BL and / BL and the column selection gate. At the same time, the sense amplifier activation signal SAON becomes logic "H", the sense amplifier is activated, and the data is amplified. LON which activates the data latch circuit becomes logical "H" as SAON becomes logical "H" and data is latched. Here, even if the address signal does not change in the word line, the APD pulse width t +
It is turned off after td. After this, the sense amplifier is also SA
ON turns to logic "L" and turns off, but before the sense amplifier turns off, LAON turns to logic "L" and turns off. As a result, the latched data is transmitted to the output buffer 7 without being inverted due to erroneous data.

Here, the signal tst changes to logic "L",
It is assumed that the state has changed to the test mode. The gate capacitors 28 and 30 and the delay inverters 16 and 17 connected to the automatic power-down signal generating circuit are separated by turning off the transmission gates 35 and 36. At the same time, the transmission gate 37 turns on. As a result, the APD pulse width t + td in the normal mode is determined by the separated gate capacitance and resistance, the delay inverter 1
It is shortened by the time tc determined by the gate capacitances of 6 and 17. That is, t + td-tc. The APD signal is input to the row selection decoder 3, the column selection decoder 8, the bit line equalize and precharge circuit 2, the sense amplifier 5, and the data latch circuit 6 via the control circuit 12. When the address signals Ax0 to Axi and Ay0 to Ayj are input to the row selection decoder 3 and the column selection decoder 8 and the APD signal is logic "L", the word line and the column selection gate corresponding to the address signal are selected. (However, it is assumed that the bit line precharge and equalization have been completed when the APD signal is logic "H").

Here, some failure modes will be described as examples. In FIG. 6, the solid line is the waveform of a good product,
The dotted line is the waveform of the defective product.

1. When the word line WL becomes higher in resistance due to process-related narrowing than the design value or when leak occurs due to stains or dust, the word line WL rises as shown in FIG. 6-1. I'm very addicted to V
It may not reach the DD level. In the past (in the normal mode), the time during which the word line WL is activated is t + td, which is a sufficient time for reading the data, and the test result becomes a pass and the defect cannot be detected. In this case, since the activation time is shortened to t + td-tc, the word line WL becomes inactive before the data is read to a level having a sufficient amplitude, so that the sense amplifier cannot fully amplify it and the test result becomes a failure.

2. In the case of a memory cell having an imbalance due to mask shift or the like and a marginal characteristic due to parasitic resistance on the store node, the bit lines BL and / BL have a sufficient data amplitude as shown in FIG. 6-2. It may not be possible to read it above. However, conventionally (in the normal mode), the activation time of the word line and the activation time of the sense amplifier are long, so that the test result may pass. However, in this embodiment, since the activation period of the word line and the sense amplifier is shortened by tc, the word line is deactivated before the data is accurately read onto the bit line, and the sense amplifier is deactivated in a short time. , The data cannot be accurately amplified and latched, and the test result becomes fail.

3. In the above cases 1 and 2, or even when amplification is not possible with a sufficient gain due to the characteristic imbalance of the sense amplifier (differential amplifier) due to mask shift or the like, if there is a timing margin, it passes the test. There was a case. However, in this embodiment, by shortening the active period of the sense amplifier and the data latch period in the test mode, the test result can be failed as shown in FIG. 6C.

Next, again in the normal mode, that is, the signal t
When st becomes logic "L", the gate capacitors 28 and 30 and the delay inverters 16 and 17 of the auto power-down signal generating circuit which were disconnected in the test mode are connected, and the width of the APD pulse returns to t + td.

The above is one embodiment of the present invention, and it goes without saying that it can be changed without departing from the spirit of the present invention.

[0022]

According to the present invention, it is possible to shorten the activation time of the word line, the sense amplifier, and the data latch circuit by shortening the APD pulse only at the time of testing without requiring a complicated circuit configuration as in the prior art. Therefore, it becomes possible to detect a defect having marginal characteristics with a strict data read timing by using a simple test pattern. As a result, it is possible to significantly reduce the test time and cost, and it is possible to ship highly reliable samples. Also, since the switching means is used to disconnect the capacitance in the auto power-down signal generation circuit, it is not necessary to newly provide another auto-power-down signal generation circuit, and it is possible to minimize the increase in layout area. Becomes

[Brief description of the drawings]

FIG. 1 is a test circuit diagram of an SRAM showing a conventional example.

FIG. 2 is a timing chart of a conventional example.

FIG. 3 is a block diagram of an SRAM showing an embodiment of the present invention.

FIG. 4 is a diagram showing an auto power-down signal generation circuit according to an embodiment of the present invention.

FIG. 5 is a timing chart showing an example of the present invention.

FIG. 6 is a waveform chart showing an example of a failure mode.

FIG. 7 is a test time comparison diagram based on a test pattern and a storage capacity.

[Explanation of symbols]

1 ... Memory cell array 2, 46 ... Bit line equalize circuit and precharge circuit 3 ... Row selection decoder 4 ... Column selection gate 5 ... Sense amplifier 6 ... Data latch circuit 7 ... Input / output buffer 8 ... Column selection decoder 9 ... Address transition detection circuit 10, 12 ... Control circuit 11 ... Auto power down signal generation circuit 13-17 ... Delay inverter 18, 33, 34 ... Inverter 23-25, 37-40, 47, 48 ... NMOS 20-20 ... PMOS 35, 36, 37 ... Transmission gate 29, 30 ... NMOS (capacitance) 26-28. ..PMOS (capacitance) 31 ... NOR gate 16 ... Control signal output means 49, 50 ... Data bus 43 ... Word line ADD ...・ Address signal ATD ・ ・ ・ Address transition detection signal APD ・ ・ ・ Auto power down signal WL ・ ・ ・ Word line BL, / BL ・ ・ ・ Bit line SAON ・ ・ ・ Sense amplifier activation signal SAout ・ ・ ・ Sense amplifier output LON ... Data latch circuit activation signal Lout ... Data latch circuit output tst ... Normal mode / test mode switching signal Ax0 to Axi ... Row address signal Ay0 to Ayj ... Column address signal

Claims (2)

[Claims] 1. An address transition detection circuit having a plurality of static memory cells arranged in a matrix and detecting a change in an address signal and generating a pulse A having a predetermined width. In response to this, a static random access memory having a pulse generation circuit for generating a pulse B for determining a memory cell activation period is characterized in that the pulse width of the pulse B in the test mode is shorter than that in the normal mode. Semiconductor memory device. 2. The static random access memory according to claim 1, wherein a capacitor forming a timer circuit (hereinafter referred to as an auto power down signal generating circuit) for determining the pulse width of the pulse B is disconnected in a test mode. A semiconductor memory device having switch means.