JPH0915294A - Specifying method for failure mode - Google Patents

Abstract

PURPOSE: To provide a specifying method for a failure mode, capable of specifying the failure mode in nondestruction easily and speedily. CONSTITUTION: When a logical motion test pattern (FTP) is inputted to a CMOS logical circuit, a leak current Iddq in a static state of logical motion extracts this FTP at a time when abnormality of this leak current Iddq flowing beyond a specified value is produced. A relationship of supply voltage vs. supply current known called a 'V-I characteristic' in the FTP at the time when this Iddq abnormality is produced, is examined. Next, the distinctive feature of this examined V-I characteristic curve is extracted. When a failure mode is not narrowed down at stationary environment, the power source impression of a large scale integrated circuit LSI is contrived or the physical environment of this LSI to be measured in varied to some extent, and by emphasizing the feature of this V-I characteristic curve, the failure mode is clearly actualized. Then, the failure mode is specified on the basis of the examined V-I characteristic.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for specifying a failure mode, and more particularly to a method for specifying a failure mode when a certain logic test pattern is
The present invention relates to a method for specifying a failure mode that has occurred in a CMOS logic circuit in which a leakage current abnormality occurs in a quiescent state of logic called ddq.

[0002]

2. Description of the Related Art Heretofore, it has not been possible to specify the cause of a failure that has occurred inside a CMOS logic circuit from electrical characteristics except for a short between power supplies (short between Vdd and GND). Therefore, a failure occurrence location is narrowed down using a logical test pattern, and then a physical analysis of the narrowed failure location is performed to investigate and detect a failure cause.

[0003] First, a fault location is narrowed down by a method called an EB tester, in which electrons are irradiated onto wiring of a large-scale integrated circuit (LSI), and secondary electrons generated are detected to generate a potential map or a logical waveform at an irradiation point. The extraction technique was typical.

[0004] In addition, the detection of a failure point is performed by a microscope (SEM,
Using an optical microscope, etc., the external appearance is observed, and further, a desired layer is etched by a laser or the like to expose a failed portion, or a cross section of a limited portion is focused by a focused ion beam called FIB. The failure mode was detected by observation.

Conventional methods for estimating a failure mode include:
A method using an emission microscope (EMS) is known, and the REAJ 4th Reliability Symposium (Vol. 1)
3 / No. 3 / November 1991). 71-P. 76
It is proposed by “Study of LSI failure analysis method using emission wavelength distribution”. This method is an analysis method that estimates the failure mode of the LSI by analyzing the spectrum of light emitted from the failure location of the LSI with an emission microscope.

FIG. 18 is an explanatory diagram for analyzing the LSI by the above emission microscope. In FIG.
The optical microscope 43 placed above the LSI 42 mounted on the UT board 41 observes the light emission emitted from the faulty part of the LSI 42. The light emission observed by the optical microscope 43 is amplified by a font amplification tube 45 called an image intensifier through a filter 44 called a bandpass filter that transmits only an arbitrary light wavelength band, and an image is picked up by a CCD camera 46. It is then sent to the image processing device 47. Emission microscope is LSI4
The light emission observation path is placed in the dark room 48 in order to detect the minute light emission from 2. Further, an image obtained by processing by the image processing device 47 is displayed by a cathode ray tube (CRT) 49.

In this conventional failure mode identification method, light emission for each wavelength band is combined by combining a function of integrating the amount of light detected by an emission microscope and a filter 44 for transmitting only an arbitrary light wavelength band by a band-pass filter. The failure mode is estimated by measuring the quantity and observing the spectrum caused by each failure mode.

[0008]

However, in the above-mentioned conventional failure mode identification method, the failure mode detected by the emission microscope is limited to the optical wavelength band of the bandpass filter 44 from 400 nm to 1000 nm. Therefore, the failure mode detected in that band is CMOS
Failure modes to be detected are limited due to open failure of a gate electrode on a logic circuit, leak failure due to destruction of a gate oxide film, and short-circuit between wires due to a high-resistance conductor.

Further, the detected failure modes are plotted in a graph called "emission spectrum" in which the amount of light emission on an arbitrary scale is plotted on the Y axis and the wavelength is plotted on the X axis. There was variation and it was not definite. For example, FIG. 19 is an emission spectrum showing the relationship between the amount of emitted light with respect to each wavelength of the gate oxide film breakdown (A in the figure) and the open defect of the gate electrode (B in the figure). As can be seen from FIG. 19, the emission amount for each wavelength of the gate oxide film breakdown and the gate electrode open defect is almost the same shape. Therefore, when considering the variation of the spectrum shape, the failure mode can be accurately estimated. Disappear.

Further, since the failure analysis by the emission microscope must first be performed by detecting the failure occurrence point,
It takes a lot of time to specify (or estimate) the failure mode. Furthermore, the emission microscope has a drawback that it limits the narrowing down of failures because it makes it impossible to detect light emission under wiring in an LSI having a multilayer wiring structure. Further, when the leak current is large, the light amount becomes enormous, and there is a disadvantage that the emission microscope cannot be used.

The present invention has been made in view of the above points,
It is an object of the present invention to provide a method for specifying a failure mode in which a failure mode can be easily specified in a nondestructive manner by using a power supply voltage vs. power supply current characteristic in a test pattern in which a leakage current abnormality has occurred in a static state of logic called Iddq. And

Another object of the present invention is to provide a failure mode specifying method capable of quickly specifying a failure mode.

[0013]

In order to achieve the above-mentioned object, the present invention sequentially inputs an arbitrary logic operation test pattern from an input terminal of a CMOS logic circuit so that the logic operation of the CMOS logic circuit is in a static state. Measure the power supply currents respectively, extract the logic operation test pattern in which the power supply current in the quiescent state of the logic operation exceeds the specified value, and extract the logic operation test pattern, and then apply the extracted logic operation test pattern to change the power supply voltage The failure mode is specified from the change characteristic curve of the power supply current that changes in accordance with.

Further, the change characteristic curve of the power supply current, which changes according to the change of the power supply voltage in the state where the extracted logic operation test pattern of the present invention is applied, changes by changing the power supply application environment of the CMOS logic circuit. It is characterized in that it is a curve of power supply voltage vs. power supply current characteristics.

Here, the power supply environment of the CMOS logic circuit may be changed by changing the power supply voltage-current characteristic at arbitrary time intervals with a constant power supply voltage applied or by changing a constant abnormal stationary power supply current. Change of the power supply voltage-current characteristic at any time in the flowing state, or change the power supply voltage-current characteristic by applying a pulse voltage to the power supply voltage;
Alternatively, the present invention is characterized in that the polarity of the applied power supply voltage is reversed to change the power supply voltage-current characteristics.

A power supply current change characteristic curve which changes in accordance with a change in the power supply voltage when the extracted logic operation test pattern of the present invention is applied is a power supply current which changes by changing the physical environment of the CMOS logic circuit. It is characterized by a curve of a voltage vs. power supply current characteristic.

Here, the change of the physical environment of the CMOS logic circuit may be caused by changing the external temperature of the large-scale integrated circuit having the CMOS logic circuit, or by the light on the chip surface of the large-scale integrated circuit having the CMOS logic circuit. Alternatively, it is characterized by the presence or absence of ion or electron irradiation.

Further, according to the present invention, in order to specify a failure mode from a change characteristic curve of a power supply current which changes in accordance with a change in a power supply voltage in a state where a logic operation test pattern in which an abnormality occurs is applied, In the current characteristic, a failure mode is detected using a power supply voltage value at which the power supply current starts to flow rapidly, a gradient of the power supply current, and a characteristic singularity.

[0019]

When a CMOS logic circuit has a physical defect inside the circuit, a general tendency is "Iddq (Quiesent Vdd Sup
An abnormal value appears in the quiescent power supply current called “ply Current”. This description is described in the literature (M. Sanada “New Application
of Laser Beam to Failure analysis of LSI with Mult
i-metal layers '' Micro Electronics and Reliability, Vo
l.33, No. 7, pp. 993-1009, 1993 and M. Sanada `` Evaluation a
nd Detection of CMOS-LSI with Abnormal Iddq '' MicroEl
ectronics and Reliability, Vol. 35, No. 3, pp. 619-629,
1995).

The present invention utilizes the state of occurrence of this Iddq value abnormality. That is, “FTP (Function
When a logical operation test pattern called “Test Pattern” is input to the input terminal of the CMOS logic circuit, FTP that flows beyond a predetermined value and causes an Iddq abnormality is input to the input terminal, and the “VI characteristic” obtained at that time is input. A failure mode is specified by investigating a relationship of a power supply current that changes when a power supply voltage is changed, and a test pattern in which an Iddq abnormality that causes a physical failure in a circuit to appear is input. A failure mode can be specified from a VI characteristic curve obtained by inputting the voltage to a terminal. In the present invention, as a method of changing the power application environment of the LSI to be measured, a method in which a constant power supply voltage is applied to the LSI is arbitrary. The shape of the characteristic changed by measuring the VI characteristic in FTP at the Iddq abnormality flowing over a predetermined value for each time of The shape of the characteristic changed by measuring the above-mentioned VI characteristic at an arbitrary time with the Iddq abnormal current flowing, and the change by applying a pulse voltage so as to be superimposed on the applied power supply voltage. VI
Because the shape of the characteristics and the VI characteristics detected by reversing the polarity of the applied power supply voltage are used,
The failure mode can be specified with the I-characteristic curve emphasized.

Further, in the present invention, as a method of changing the physical environment of the LSI to be measured, by changing the external temperature of the LSI, a change in VI characteristics before and after the temperature change can be inspected, or the chip surface of the LSI can be inspected. Whether to irradiate the light,
Since the change of the VI characteristic which changes depending on the presence / absence of the electron beam irradiation and the ion irradiation is inspected, the failure mode can be specified with the curve of the VI characteristic emphasized.

Further, according to the present invention, in order to detect the peculiarity of the VI characteristic, the failure of the VI characteristic which is changed by combining the above-described power supply contrivance and the physical environment of the LSI is performed. The mode is specified.

In the method of the present invention, the parameter used to specify the failure mode based on the above-mentioned VI characteristic
This is a method of specifying a failure mode from the characteristics of the entire shape of the I characteristic curve, or a parameter used for detecting the failure mode from the VI characteristic is that the current on the VI characteristic curve is abruptly increased. The voltage value that starts to flow, the current gradient (ΔI / ΔV value), and the singular point (V, I
Value).

[0024]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a flow chart of an embodiment of the method of the present invention, which is a flow chart for specifying a failure mode of a defect occurring inside a CMOS logic circuit. As shown in the figure, first, when a plurality of known logic operation test patterns (FTP) are sequentially input from the input terminal of the CMOS logic circuit, a leakage current (static power supply current) Iddq in a quiescent state of the logic operation. FT when an Iddq abnormality that flows exceeding a predetermined value occurs
Extract P (step 11).

FIG. 2 is a graph showing the relationship between the FTP and the Iddq value at this time. The x-axis indicates the FTP number, and the y-axis indicates the Iddq value.
The ddq value is shown. In this graph, FTP (P
In 1) and (P2), an Iddq abnormality has occurred.
The FTP (P1) and (P2) are used to specify the failure mode.

Next, in step 11 of FIG.
The FTP extracted as the occurrence of the q abnormality is inputted to the input terminal, and the relation of the power supply current, which changes when the power supply voltage called “VI characteristic” obtained at that time is changed, is examined (step 12). FIG. 3 shows the FTP vs. Id in FIG.
FT with Iddq value abnormality detected from dq value measurement
It is a VI characteristic in P (P1) or FTP (P2).

In a normal state, the power supply current of a CMOS logic circuit (large-scale integrated circuit: LSI) in which a through current does not occur in a circuit is 1 μA or less, but there is a physical defect inside the LSI, and the defect is found in the circuit. In general, Iddq abnormalities of several hundred times to several thousand times or more of the upper limit of the standard occur in defective products having an influence (see the above-mentioned literature).

Next, in step 12 of FIG. 1, the characteristics of the investigated VI characteristic curve are extracted (step 1).
3). However, when the failure mode cannot be narrowed down in a steady environment, the failure mode can be reduced by devising the power supply to the LSI or changing the physical environment of the LSI to be measured to emphasize the characteristics of the VI characteristic curve. It is clearly evident (step 14).

As the above-described method of accelerating the environment, the former method of applying power is to measure the VI characteristic at an arbitrary time interval with a constant power supply voltage applied, and to determine the V-I characteristic from the changing characteristic shape. A method of enhancing the characteristics of the I characteristic curve, and measuring the VI characteristics at arbitrary time intervals while a constant Iddq abnormal current is flowing, thereby enhancing the characteristics of the VI characteristic curve from the shape of the changing characteristics. how to,
A method of emphasizing the characteristics of the VI characteristic curve when a pulse voltage is applied so as to be superimposed on the applied power supply voltage, and by reversing the polarity of the applied power supply voltage,
-I There is a method of enhancing the characteristics of the characteristic curve.

The latter method for changing the physical environment of the LSI includes, for example, a change in the external temperature of the entire LSI,
There is a method of emphasizing the characteristics of the VI characteristic curve by irradiating the LSI chip surface with light, irradiating the LSI chip surface with ions, and irradiating the LSI chip surface with an electron beam. In addition, the characteristics of the VI characteristic curve can be emphasized by a combination of the above-described irregular power supply use method and the physical environment of the LSI.

Then, as described above, in step 14, the LSI
The failure mode is clearly clarified by devising the power supply of the device or changing the physical environment of the LSI to be measured to emphasize the characteristics of the VI characteristic curve. After extracting the characteristics of the VI characteristics extracted in step 13, the failure mode is specified in step 15.

Next, the environmental acceleration method in step 14 will be described in detail. First, the constant voltage is set to L
There is a method in which a failure mode is specified from the shape of the changed characteristic by measuring the VI characteristic at an arbitrary time in a state where the voltage is applied to the SI.

FIG. 4 shows VI with a constant voltage applied.
It is a figure showing a change of a characteristic. In the figure, a solid line I is a VI curve obtained when an Iddq abnormality was detected, and a broken line II.
Is the VI whose impedance decreases with time.
It is a curve. This method is effective in preventing a reverse bias electric field higher than the breakdown voltage from being applied to the PN junction. In this method, a singular point of the VI characteristic (described later) may tend to change, but the change is not directly related to the failure mode.

This will be described with reference to the equivalent circuit diagram of FIG. This equivalent circuit has impedances Z1 and Z2
Is connected at one end to the power supply voltage Vdd and the other end is connected to the ground via an element having an impedance Z, and a failure occurs at a common connection point P of the elements having impedances Z1, Z2 and Z. 1 shows a circuit. In this case, the leak current path is initially Vdd → Z1 → P → Z → GND.
Pass through the current path in order of Vdd → Z2 → P → Z → GND, the impedance of which decreases with the passage of time.

As described above, the leakage current path changes in the direction in which the impedance decreases from the failure occurrence point P as a starting point or center, so that the fluctuation is not directly related to the failure mode. Therefore, by paying attention to the change point based on the fluctuation of the VI characteristic curve, an equivalent circuit that accelerates the deterioration of the failure location becomes clear, and therefore, the leak at the failure location is emphasized, and the failure mode can be easily specified.

Next, a description will be given of a method of measuring a VI characteristic at an arbitrary time in a state where the above-mentioned constant Iddq abnormal current is flowing, and specifying a failure mode from the shape of the changed characteristic. FIG. 6 is a diagram showing a change in the VI characteristic with the leak current kept constant. In the figure, solid line II
I is a VI curve acquired when the Iddq abnormality is detected, and broken line IV is a VI curve in which the impedance decreases with time.

This method is effective for preventing disconnection due to electromigration generated in a particularly thin wiring due to an increase in current, and inducing another failure mode due to a change in an upper layer due to heat generated by a high-resistance body. In this method, the same tendency as described above becomes apparent, and the leak at the failure location is emphasized, and therefore, the failure mode can be easily specified.

Next, as a method of devising the power supply voltage of the LSI, V-V
A method for observing a change in the I characteristic will be described. FIG. 7 shows a system configuration diagram in this case. In FIG. 1, a constant voltage power supply and a test pattern (FTP) generated by a test pattern generator 21 are supplied to an LSI 23 mounted on a board 22. Also, VI
A voltmeter 24 and an ammeter 25 for measuring the characteristics are installed between the respective Vdd and the GND terminal and in the GND wiring connected to the GND terminal of the LSI 23, and the signals are transmitted through a cable 26 to a personal computer ( (Hereinafter abbreviated as a personal computer) 27 and a curve tracer 28. Further, a pulse voltage source 29 is provided on a path between the constant voltage power supply 21 and the board 22, and applies a power supply voltage on which a pulse voltage is superimposed to the LSI 23.

The amplitude of the output pulse voltage of the pulse voltage source 29 is suppressed to 0.5 V or less. The reason for this is to prevent the PN junction from being forward biased and starting to flow current. Generally, the voltage that starts to flow due to forward bias is about 0.65 V to 0.7 V, which is derived from the following equation.

V ≒ (kT / q) · ln (Is / I) where I = 1 μA.

(K: Boltzmann constant, T: absolute temperature,
(q: charge amount of electrons, Is: saturation current value) In this method, it is possible to determine whether a PN junction is present in a passage where a through current is generated.

FIG. 8 is a diagram for explaining an example of a failure mode which is detected when the pulse voltage is superimposed on the power supply voltage. In the figure, a solid line V is a VI characteristic in which the pulse voltage is not superimposed, and a VI is a VI characteristic in which the pulse voltage is superimposed. The difference between the characteristics of V and VI is that the characteristic VI has peaks (a and b in the figure) at about 0.2 V and 1.8 V. This phenomenon indicates that the PN junction is in the forward direction step by step at the points a and b.

The presence of the PN junction on the passage of the through current is due to the fact that a physical defect exists in the semiconductor substrate or
A short circuit between the wiring and the well due to dielectric breakdown is considered.

FIG. 9 shows V- when the polarity of the applied voltage is reversed.
This is an example of the I characteristic. In the figure, the solid line VII is the VI inverse characteristic of the normal LSI, and the broken line VIII is the VI inverse characteristic of the LSI having a physical defect in the internal circuit. This kind of curve
VIII is a short circuit between power supplies and a mode of PN junction breakdown, and this test identifies a certain failure mode.

Next, as a method of changing the physical environment of the LSI, a method of emphasizing the characteristic of the VI characteristic curve by changing the external temperature of the entire LSI will be described. Fig. 10 shows that the LSI is put in a thermostatic chamber with the FTP that causes the Iddq anomaly being input, and V is applied while accelerating the temperature.
1 shows a system configuration diagram for observing a change in -I characteristics.

In the figure, the constant voltage and test pattern (FTP) generated by the constant voltage power supply and test pattern generator 21 are used for an LSI mounted on a board 22.
23. Further, a voltmeter 24 and an ammeter 25 for measuring the VI characteristic are respectively provided with Vdd and G.
G connected between the ND terminals and to the GND terminal of the LSI 23
It is installed in the ND wiring, and its signal is
Are connected to a personal computer 27 and a curve tracer 28 via the.

Further, the entire LSI 23 is placed in the constant temperature bath 30. The constant temperature bath 30 has a structure in which the internal temperature can be changed to a desired temperature by some method. The change in the VI characteristic of the CMOS logic circuit of the LSI 23 when the temperature of the entire LSI 23 is changed in this way is effective mainly for detecting leaks caused by open gate electrodes and PN junction defects. For example, the opening of the gate electrode will be described with reference to FIGS.

FIG. 11 shows an example of a failure mode which is detected when the temperature of the entire LSI is accelerated. In the figure, the solid line IX is the case where the temperature is not accelerated, and the broken line X is the case where the temperature is accelerated.
-I characteristic. What is discriminated from the difference between the characteristics IX and X is that the channel resistance and the threshold voltage are related. That is, the channel resistance shifts in the direction in which the impedance increases according to the temperature coefficient, and the threshold voltage has a temperature characteristic (several mV).
/ Deg). This change becomes remarkable when one gate electrode of the inverter circuit is opened.

For example, FIG. 12 is an example for explaining the above-mentioned phenomenon. A pair of P-channel transistors (hereinafter, P-
This is an inverter circuit composed of a QTr) Q1 and an N-channel transistor (hereinafter N-chTr) Q2. When a high-level (H) signal is applied to the input when the gate electrode of the P-ch Tr Q1 of the inverter circuit is open (indicated by ★ in the figure), the signal is supplied from Vdd via the normally-on P-ch Tr Q1. Then, a through current flows to GND via the N-ch Tr Q2 in the ON state.

When this inverter circuit is accelerated in temperature, the channel resistance of the normally-on P-chTrQ1 shifts in the direction of increasing impedance in accordance with the temperature coefficient, and the threshold voltage of N-chTrQ2 changes with temperature. It decreases according to the characteristic (several mV / deg), and the change of the VI characteristic shown in FIG. 11 becomes apparent.

Next, as a method of changing the physical environment of the LSI, a method of emphasizing the characteristics of the VI characteristic curve by the presence or absence of light irradiation on the surface of the LSI chip will be described. FIG. 13 is a system configuration diagram of a system for inspecting a change in the VI characteristic by irradiating or not irradiating light on the LSI chip surface in the state where the FTP causing the Iddq abnormality is input.

In the same figure, a constant voltage and a test pattern (FTP) generated by a constant voltage power supply and test pattern generator 21 are mounted on an LSI mounted on a board 22.
23. Further, a voltmeter 24 and an ammeter 25 for measuring the VI characteristic are respectively provided with Vdd and G.
G connected between the ND terminals and to the GND terminal of the LSI 23
It is installed in the ND wiring, and its signal is
Are connected to a personal computer 27 and a curve tracer 28 via the.

Further, the package of the LSI 23 is opened and the chip surface is exposed. A light source is installed above the chip surface, and the light 31 from the light source may or may not be irradiated on the chip surface. A characteristic feature of the presence or absence of light irradiation is that the leak greatly varies. This phenomenon is particularly observed in defects caused by the diffusion layer. For example, since electrons are activated at the PN junction by light irradiation, the observed VI characteristic moves in a direction in which the impedance decreases, and the threshold voltage of the junction shifts in a decreasing direction. The presence of the joint is detected.

Next, as a method of changing the physical environment of the LSI, a method of emphasizing the characteristics of the VI characteristic curve by the presence or absence of ion irradiation on the LSI chip surface will be described. FIG. 14 is a system configuration diagram of a system for inspecting fluctuations of VI characteristics by inputting or not inputting ions to the chip surface of an LSI in a state where an FTP causing an Iddq abnormality is input.

In the figure, the constant voltage and test pattern (FTP) generated by the constant voltage power supply and test pattern generator 21 are mounted on an LSI mounted on a board 22.
23. Further, a voltmeter 24 and an ammeter 25 for measuring the VI characteristic are respectively provided with Vdd and G.
G connected between the ND terminals and to the GND terminal of the LSI 23
It is installed in the ND wiring, and its signal is
Are connected to a personal computer 27 and a curve tracer 28 via the.

Further, the package of the LSI 23 is opened to irradiate ions, and the chip surface is exposed.
An ion source 32 is provided above the chip surface.
Further, the ion source 32 is installed in a vacuum lens barrel 34 including the LS 23 and the board 22.

Ion irradiation is effective in determining a defect in which the gate electrode of the CMOS logic circuit is opened. For example, in the inverter circuit shown in FIG.
-When considering the state where the gate electrode of chTrQ1 is open, the ions are accumulated in the gate electrode of P-chTrQ1 by ion irradiation, and the transistor becomes an operating state as if "H" level was input, and the leak is reduced. Therefore, it is possible to detect the failure mode in which the gate electrode of P-chTrQ1 is open.

Next, as a method of changing the physical environment of the LSI, a method of emphasizing the characteristics of the VI characteristic curve by the presence or absence of electron irradiation on the surface of the LSI chip will be described. FIG. 15 shows that the chip surface of the LSI is irradiated with electrons while the FTP that causes the Iddq abnormality is input,
The system block diagram of the system which inspects the fluctuation | variation of VI characteristic by not irradiating is shown.

In the figure, a constant voltage and a test pattern (FTP) generated by a constant voltage power supply and test pattern generator 21 are mounted on an LSI mounted on a board 22.
23. Further, a voltmeter 24 and an ammeter 25 for measuring the VI characteristic are respectively provided with Vdd and G.
G connected between the ND terminals and to the GND terminal of the LSI 23
It is installed in the ND wiring, and its signal is
Are connected to a personal computer 27 and a curve tracer 28 via the.

Further, the package of the LSI 23 is opened to irradiate electrons, and the chip surface is exposed. An electron gun 36 is provided above the chip surface. Further, the electron gun 36 is installed in a vacuum lens barrel 37 including the LSI 23 and the board 22.

Electron irradiation is also CM similar to ion irradiation.
This is effective in determining a defect in which the gate electrode of the OS logic circuit is open. For example, considering the state in which the gate electrode of P-chTrQ1 is opened in the inverter circuit shown in FIG.
Electrons are accumulated in the gate electrode of the chTrQ1 and the transistor enters an operating state as if the "L" level was input, and the leak current shifts to a further increase. Therefore, the gate electrode of the P-chTrQ1 is said to be open. The failure mode can be detected.

Conversely, when the gate electrode of the N-ch Tr Q2 is open, the N-ch Tr
The accumulation of electrons in the gate electrode of Q2 causes the transistor to enter an operating state in which an "L" level is input, and the transistor shifts to a direction in which the leakage current is reduced.
It is possible to detect a failure mode in which the gate electrode of chTrQ2 is open.

As described above, the failure mode can be detected in more detail by changing the VI environment of a CMOS LSI having a physical defect inside the circuit by changing the external environment.

Further, the above-described device of the applied voltage, LS
From the combination of changes in the external environment of I, it is possible to reveal a unique mode of a physical failure inside the CMOS LSI.

The VI characteristic curve detected by the above operation has two methods in which a failure mode can be detected by grasping its characteristics. This is a method of extracting the overall shape of the VI characteristic curve and the singular point of the VI characteristic curve.

FIG. 16 shows the overall shape of the VI characteristic curve for explaining the first method. This draws a characteristic curve for each failure mode, so that rough detection is possible.

FIG. 17 shows another method, in which the singular point of the VI characteristic curve and the leak gradient are detected as parameters. That is, those parameters indicate the voltage value (a in the figure) at which the leak current starts flowing, the voltage at which the slope of the leak current curve changes, and the current position (b, c, d in the figure). (Vb, Ib) , (Vc, I
c), (Vd, Id) value and the value of each gradient (α, β,
γ). Here, the values α, β, and γ of the respective gradients are expressed by the following equations.

Α = Ib / (Vb−Va) β = (Ic−Ib) / (Vc−Vb) γ = (Id−Ic) / (Vd−Vc) These parameters determine the characteristics of the VI characteristics. Therefore, the equivalent circuit of the leak path can be clearly determined, and therefore, the failure mode can be reliably specified.

As described above, when a physical fault exists inside the CMOS logic circuit, the detected VI characteristic can obtain a characteristic peculiar to each physical fault. The failure mode can be detected from the curve determination.

Next, a method of specifying the failure mode from the detected characteristic of the VI characteristic will be described. A correlation between a failure mode and a voltage-current characteristic generated due to the failure is collected in advance as a database. There are two known schemes for this. One is a method of setting a fault in a basic logic circuit and calculating a VI characteristic generated by circuit simulation. The simulation is determined based on the equivalent circuit based on the device structure of the LSI incorporating the failure mode. The current value flowing on the equivalent circuit is calculated by increasing or decreasing the voltage, and the VI characteristic is output. be able to. A second method is to collect a failure mode and VI characteristics generated due to the failure from failure analysis of the failed LSI.

The collected VI characteristics are stored in a database as the overall shape of the above-described VI characteristic curve or the singular point parameter value of the VI characteristic curve.

Next, the failure mode is specified by comparing the similarity between the shape of the detected VI characteristic and the characteristic of the VI characteristic in the database. The comparison method is performed using a personal computer or an engineering workstation. As described above, according to the present embodiment, the CM is nondestructively and efficiently
A failure mode generated inside the OS logic circuit can be specified.

The present invention is not limited to the above-mentioned embodiment, and for example, if the circuit has a small Iddq value in the steady state, it can be used in a memory, an analog circuit, and a circuit such as a microcomputer.

In a circuit in which a large Iddq value is generated in a steady state, if the VI characteristic in a steady state is known, Id
From the VI characteristics at the occurrence of the dq abnormality,
By subtracting the characteristic component, the failure mode can be easily specified as in the above.

[0075]

As described above, according to the present invention,
It is possible to efficiently specify a failure mode generated inside the CMOS logic circuit without destruction. That is, according to the present invention, a test pattern in which an Iddq abnormality that causes a physical failure inside a circuit to become apparent is input to an input terminal, and a failure mode can be specified from a VI characteristic curve obtained at that time. The enormous number of steps and time required to narrow down the location of occurrence and detect a failure mode can be reduced.

Further, according to the present invention, it is possible to specify a failure mode while emphasizing a VI characteristic curve by devising a power supply and an external environment for specifying various failure modes. Therefore, it is possible to reliably estimate a mode unique to each failure mode.

Further, according to the present invention, the VI characteristic measured by the Iddq abnormality test pattern is displayed as the VI characteristic depending on the type of the failure mode generated on the electric circuit. The failure mode can be easily specified by detecting the VI characteristic.

[Brief description of the drawings]

FIG. 1 is a flowchart of an embodiment of the method of the present invention.

FIG. 2 shows FTP and Idd in the flowchart of FIG.
It is a graph which shows an example of the relationship of q value.

3 is an example of a power supply voltage vs. power supply current (VI) characteristic of an FTP having an Iddq value abnormality detected from the graph of FIG. 2;

FIG. 4 is a VI characteristic when a constant voltage is applied.

FIG. 5 is an equivalent circuit diagram showing a state where a leak path changes in a direction in which impedance decreases with a failure occurrence point as a starting point or center.

FIG. 6 is a diagram showing a change in VI characteristics in a state where a leak current is kept constant.

FIG. 7 is a system configuration diagram of an example when a pulse voltage is superimposed on a power supply voltage.

FIG. 8 is a diagram showing changes in VI characteristics when a pulse voltage is superimposed on a power supply voltage and when it is not superimposed.

FIG. 9 is a diagram showing an example of the VI characteristic when the polarity of the applied voltage is reversed.

FIG. 10 is a configuration diagram showing an example of an apparatus for measuring a change in VI characteristic while accelerating temperature.

FIG. 11 is a diagram showing a change in VI characteristic when the temperature of the entire LSI is accelerated and when it is not accelerated.

FIG. 12 is an inverter circuit diagram illustrating a change in VI characteristic due to temperature acceleration.

FIG. 13 shows V depending on whether light is incident on the LSI chip surface.
It is a block diagram which shows an example of the apparatus which inspects the fluctuation | variation of -I characteristic.

FIG. 14 is a configuration diagram showing an example of an apparatus for inspecting the fluctuation of the VI characteristic depending on the presence or absence of ion irradiation on the LSI chip surface.

FIG. 15 is a configuration diagram showing an example of an apparatus for inspecting a change in VI characteristic depending on the presence or absence of electron irradiation on the LSI chip surface.

FIG. 16 is an overall shape of a VI characteristic curve used for estimating a failure mode.

FIG. 17 is a diagram showing an example of a singular point of a VI characteristic curve and a gradient of leakage used as parameters for estimating a failure mode.

FIG. 18 is an explanatory diagram for analyzing an LSI with an emission microscope.

FIG. 19 is an emission spectrum showing the relationship between the amount of light emission with respect to each wavelength of open defects of the gate oxide film and the gate electrode.

[Explanation of symbols]

 11 to 15 Steps of one embodiment of the method of the present invention 21 Constant voltage power supply and test pattern generator 22 Board 23 Large scale integrated circuit (LSI) 24 Voltmeter 25 Ammeter 26 Cable 27 Personal computer (PC) 28 Curve tracer 29 Pulse voltage source 30 constant temperature bath 31 light 32 ion source 34, 37 lens barrel 36 electron gun

Claims (12)

[Claims] An arbitrary logic operation test pattern is sequentially input from an input terminal of a CMOS logic circuit, and the CMOS
The power supply current in the static operation of the logic operation of the logic circuit is measured, and a logic operation test pattern in which an abnormality occurs in which the power supply current in the static operation of the logic operation exceeds a predetermined value is extracted, and the extracted logic operation test A method for identifying a failure mode, which comprises identifying a failure mode from a change characteristic curve of a power supply current that changes according to a change in a power supply voltage in a state where a pattern is applied. 2. A power supply current change characteristic curve that changes according to a change in a power supply voltage in a state in which the extracted logic operation test pattern is applied, a power supply that changes by changing a power supply application environment of the CMOS logic circuit. The method for identifying a failure mode according to claim 1, wherein the method is a curve of voltage-source current characteristics. 3. The power supply environment of the CMOS logic circuit according to claim 2, wherein the change of the power supply environment is a change of the power supply voltage-current characteristic at an arbitrary time with a constant power supply voltage applied. How to identify the failure mode. 4. The change in the power supply environment of the CMOS logic circuit is a change in the power supply voltage-current characteristic at arbitrary time intervals in a state where a constant abnormal quiescent power supply current is flowing. Item 2. The method for specifying a failure mode according to Item 2. 5. The failure mode according to claim 2, wherein the change in the power supply environment of the CMOS logic circuit is to change the power supply voltage-current characteristic by applying a pulse voltage to the power supply voltage. How to identify. 6. The fault according to claim 2, wherein the change in the power supply environment of the CMOS logic circuit is to change the power supply voltage-current characteristic by reversing the polarity of the power supply voltage to be applied. How to identify the mode. 7. A change characteristic curve of a power supply current that changes in accordance with a change in a power supply voltage in a state where the extracted logic operation test pattern is applied, the power supply voltage changing by changing a physical environment of the CMOS logic circuit. The method for specifying a failure mode according to claim 1, wherein the method is a curve of a power supply current characteristic. 8. The method according to claim 7, wherein the change in the physical environment of the CMOS logic circuit changes an external temperature of a large-scale integrated circuit having the CMOS logic circuit.
How to identify the failure mode described. 9. The failure mode according to claim 7, wherein the change in the physical environment of the CMOS logic circuit is the presence or absence of light irradiation on the chip surface of a large-scale integrated circuit having the CMOS logic circuit. How to identify. 10. The failure mode according to claim 7, wherein the change in the physical environment of the CMOS logic circuit is the presence or absence of ion irradiation on the chip surface of a large-scale integrated circuit having the CMOS logic circuit. How to identify. 11. The failure mode according to claim 7, wherein the change in the physical environment of the CMOS logic circuit is the presence or absence of irradiation of electrons on a chip surface of a large-scale integrated circuit having the CMOS logic circuit. How to identify. 12. A power supply voltage vs. power supply current characteristic in order to specify a failure mode from a power supply current change characteristic curve that changes in accordance with a power supply voltage change with a logic operation test pattern in which the abnormality occurs applied. The failure mode according to any one of claims 1 to 11, wherein the failure mode is detected using a power supply voltage value at which the power supply current starts to flow rapidly, a gradient of the power supply current, and a characteristic singularity. How to identify.