JPH09152853A - Video signal conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively reduce a flicker while holding the resolution of a vertical direction satisfactorily without enlarging and complexing the circuit constitution of a scanning line transform filter, etc., by providing a flicker preventing circuit. SOLUTION: The high-pass filter 151 of a flicker preventing circuit 15 has a characteristic of passing the high frequency component relatively largely and a non-linear circuit 152 has a characteristic β of suppressing the component having a large amplitude among the high frequency components through a filter 151 releatively largely to output it. That is, the non-linear circuit 152 has the characteristic β in which in the case the amplitude of an input signal is small, a gain is 1 but as the amplitude of the signal becomes larger, the gain decreases non-linearly. Consequently, the circuit 152 can be operated as a low-pass filter only to the high frequency component having the large amplitude in which a flicker is apt to be conspicuous at the time of a non-interlace- interlace transformation and, as a result, even though the characteristic of a scanning line transform filter 14 is not made steep, the flicker of the video signal to be outputted from this video signal transform device is sufficiently suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for converting a non-interlaced video signal into an interlaced video signal. In particular, the present invention relates to a device that reduces flicker with a relatively simple hardware configuration.

[0002]

2. Description of the Related Art There is provided a device called a scan converter for converting an output video signal of a personal computer into a standard television signal (NTSC system television signal or the like). In the scan converter, the number of scanning lines of the video signal output from the personal computer is converted by the scanning line conversion filter so that it matches the number of scanning lines of the standard television signal, and then controlled by the clock on the personal computer side. Written to image memory. At that time, each odd line and each even line in the same frame are alternately written at a speed twice the frame period. As a result, the non-interlaced method is converted into the interlaced method.
The video signal written in the image memory is read by being controlled by the clock of the television device on the output side. As a result, the number of samples (number of horizontal pixels) in the horizontal scanning period becomes
It is converted to fit the image size of the television device on the output side.

Japanese Laid-Open Patent Publication No. 6-292154 discloses a scanning line compression unit for compressing the number of scanning lines so as to match the image size of the television device on the output side, and the number of horizontal pixels for the image size of the television device on the output side. There is disclosed an apparatus in which a flickerless processing unit for suppressing flicker is provided between an image memory for conversion so as to comply with the above. The flicker-less processing unit of the apparatus reduces flicker by adding adjacent scanning lines and then halving them to output.

[0004]

When a non-interlaced video signal is converted into an interlaced video signal, so-called flicker, which is flicker between adjacent scanning lines, tends to occur in the converted video signal. In order to reduce this flicker, it is effective to give the scanning line conversion filter the characteristics of a low-pass filter.
In that case, there is a problem that the resolution in the vertical direction is reduced. Further, in order to reduce flicker without lowering the resolution in the vertical direction, it is necessary to provide the scanning line conversion filter with a high-order tap number, which increases the size and complexity of the hardware configuration.

In the above-mentioned Japanese Patent Laid-Open No. 6-292154, the average value of adjacent scanning lines is output,
Although flicker can be suppressed, there is a problem that the vertical resolution is reduced.

An object of the present invention is to provide a video signal conversion device capable of effectively reducing flicker without increasing the size and complexity of the circuit configuration of the device and while maintaining good resolution in the vertical direction. To aim.

[0007]

According to the present invention, a non-interlaced video signal is input and the number of scanning lines is converted, and the number of horizontal pixels is converted by writing / reading to / from an image memory. A video signal conversion device for performing conversion processing and outputting as an interlaced video signal, comprising a flicker suppressing means for suppressing high frequency components of the video signal before writing to the image memory. Is.

Further, in the above, means for being provided between the scanning line number converting means and the image memory to relatively greatly suppress a signal component having a relatively large amplitude among the high frequency components. Therefore, the flicker suppressing unit is configured as described above. Further, in the above, the high frequency component of the signal sent from the scanning line number converting means is reduced to a high frequency cut signal, and the relatively high amplitude component of the high frequency component is suppressed. The flicker suppressing means is configured by using means for adding the large-amplitude suppressed high-frequency signal to the high-frequency cut signal as a large-amplitude suppressed high-frequency signal and outputting it. Thus, the high frequency components of the video signal, especially,
By adding a relatively simple configuration of a circuit that largely suppresses a large amplitude component of the high frequency component, it is possible to configure a device that sufficiently reduces flicker.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1A shows an example of a circuit configuration of a main part of a video signal conversion apparatus embodying the present invention, and FIG. 1B shows a flicker prevention circuit 15 in FIG. An example is shown.

The circuit shown in the figure is an A / D converter 11 for digitizing analog video signals (R, G, B signals) sent from a personal computer (not shown), and a digitized R signal.
・ Matrix circuit 12 for converting G / B data into video signals of luminance / color difference, and horizontal low-pass filter (LPF) 13
And a scanning line conversion filter that converts the number of scanning lines of the video signal sent from the horizontal LPF 13 so as to match the number of scanning lines of the standard television device on the output side (here, the NTSC system television device). 14, a flicker prevention circuit 15 that suppresses flicker of the video signal after conversion of the number of scanning lines, and a writing system (device on the personal computer side) that writes and reads the video signal after suppression of flicker (on the television side). Image device 20 / writing system timing generation circuit that converts the number of samples (horizontal pixel number) in the horizontal scanning period to match the number of horizontal pixels of the standard TV device on the output side by reading by controlling the timing signal of 10. A read system timing generation circuit 30 and a D / A converter 31 for converting the video data read from the image memory 20 into an analog signal. The output signal of the D / A converter 31 is sent to an NTSC encoder (not shown) and converted into an NTSC television signal.

An example of the scanning line conversion filter 14 is shown in FIG. The filter 14 of FIG. 3 has three line memories 141 and 14
2,143, four multipliers 144,145,146,147, and one adder 148, which is a filter with four taps, and positive or negative coefficients K0 to four scanning lines sequentially input from the horizontal LPF13. By appropriately multiplying K3 and then adding them, one scanning line is generated from four scanning lines.

The operation of the scanning line conversion filter 14 is shown in FIG. 4 (a), and the characteristics required of the scanning line conversion filter 14 are shown in FIG. 4 (b). As shown in the figure, the scanning line conversion filter 14 converts seven scanning lines into six scanning lines. Also, at that time, it is possible to
Book scan lines are generated.

That is, as the output side scanning lines shown in the right column of FIG. 4A, four input side scanning lines shown in the left column of FIG. 4 are used, and the four scanning lines are multiplied by the above-mentioned multiplication. It is generated by appropriately multiplying any one of twelve kinds of positive or negative coefficients α _{0 to} α _{11 in} the units 144, 145, 146 and 147 and adding them by the adder 148. In the figure, the scan lines on the output side shown in the right column are the scan lines with circles and crosses alternately arranged. This is from one non-interlaced frame to two interlaced fields (= 1 frame). In order to generate, the same non-interlaced frame is generated at the speed of twice the frame frequency for each of the ○ marks and × marks.
Indicates to write to. By processing in this way, one field is formed on each of the screens marked with a circle and a cross.

Ideally, such a filter for performing conversion processing from 7 to 6 filters is required to have the characteristics shown in FIG. 4 (b). That is, the sampling scan line frequency fsmax
On the other hand, a cutoff characteristic of π / 7 is required, and the closer to this characteristic, it is possible to maintain the resolution in the vertical direction and reduce the flicker, but for that purpose, a high-order tap number is required. . When performing the non-interlace / interlace conversion described above, a cutoff characteristic of π / 14 is required as indicated by a broken line in the figure.

Next, an example of the flicker prevention circuit 15 will be described.
This will be described with reference to FIG. The illustrated flicker prevention circuit 15 includes a high-pass filter 151 and a non-linear circuit 15
This is a circuit composed of 2, a subtractor 153, and an adder 154. That is, the high-pass filter 151 and the subtractor 153 remove high-frequency components from the signals sequentially sent from the scanning line conversion filter 14 to obtain a high-frequency cut signal, and among the removed high-frequency components, By suppressing a component having a large amplitude by the non-linear circuit 152 having the characteristic β to form a large-amplitude suppressed high-frequency signal, and adding the large-amplitude suppressed high-frequency signal to the high-frequency cut signal by the adder 154, This is a circuit that prevents flicker.

Here, the high-pass filter 151 is constructed so as to have a characteristic of relatively high-passing the high frequency component in the input signal, as shown in FIG. Further, the non-linear circuit 152 is a high-pass filter as shown in FIG.
Of the high frequency components that have passed through 151, it is configured to have a characteristic β that relatively largely suppresses a component with a large amplitude and outputs. That is, when the amplitude of the input signal is small, the gain is 1, but the characteristic is such that the gain decreases non-linearly as the amplitude of the input signal increases. With this configuration, it is possible to act as a low-pass filter only on high-amplitude high-frequency components where flicker tends to stand out during non-interlaced / interlaced conversion, and as a result, the characteristics of the scanning line conversion filter 14 are made sharp. Even without it, it is possible to sufficiently suppress the flicker of the video signal output from the present video signal conversion device.

[0017]

According to the present invention, since the flicker prevention circuit for suppressing the high frequency component of the video signal, especially the large amplitude component in the high frequency component is provided in the preceding stage of the image memory, non-interlace / interlace is performed. It is possible to sufficiently suppress high-amplitude high-frequency components where flicker tends to be noticeable during conversion, and as a result, it is possible to maintain good resolution in the vertical direction without increasing the size and complexity of the circuit configuration such as the scanning line conversion filter. The flicker can be effectively reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram (a) showing a circuit configuration of a main part of an example of a video signal converter embodying the present invention, and a block diagram (b) showing an example of a flicker prevention circuit 15 in the block diagram (a). ).

2 is a characteristic diagram (a) showing a characteristic of a high-pass filter 151 in a flicker prevention circuit 15 of FIG. 1 (b) and a characteristic diagram (b) showing a characteristic β of a non-linear circuit 152.

FIG. 3 is a block diagram showing an example of the scanning line conversion filter 14 of FIG.

FIG. 4 is an operation explanatory diagram (a) of a scanning line conversion filter that converts the number of scanning lines from seven to six, and a characteristic diagram (b) showing ideal characteristics required for the scanning line conversion filter.

Claims (3)

[Claims] 1. A non-interlaced video signal is input, and conversion processing of the number of scanning lines, conversion processing of the number of horizontal pixels by writing / reading control to an image memory, and conversion processing to the interlaced method are performed, A video signal conversion device for outputting as an interlaced video signal, comprising a flicker suppressing means for suppressing a high frequency component of the video signal before writing to the image memory. 2. The flicker suppressing means according to claim 1, wherein the flicker suppressing means is provided between the scanning line number converting means and the image memory and has a relatively large amplitude among the high frequency components. A video signal conversion device that is a means for relatively significantly suppressing noise. 3. The flicker suppressing means according to claim 2, wherein the high frequency component of the signal sent from the scanning line number converting means is reduced to a high frequency cut signal, and the high frequency component of the high frequency component is reduced. A video signal conversion device, which suppresses a component having a relatively large amplitude to obtain a large-amplitude suppressed high-frequency signal, adds the large-amplitude suppressed high-frequency signal to the high-frequency cut signal, and outputs the signal.