JPH09152629A - Array substrate of liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately specify the position of a defect without making the structure extremely complicated. SOLUTION: The array substrate of the liquid crystal display device is equipped with plural pixel electrodes, plural scanning lines 3, plural signal lines 4, plural switching elements 5 which supply video signals from corresponding signal lines 4 to corresponding pixel electrodes in response to scanning signals from corrsponding scanning lines 3, and an inspection support circuit 30 which senses the potentials of the scanning lines 3. Specially, the circuit 30 consists of plural thin film transistors 35 for inspection which have their gates connected to the scanning lines 3 and an inspection wiring part 34 which is connected to the source-drain paths of those transistors 35, and the wiring part 34 includes a monitor pad 32 and a ground pad GND where the source- drain paths of the transistors 35 are connected to each other in parallel, an inspection potential pad 31 which is applied with an inspection voltage, and a resistor element 33 which is connected between the pads 31 and 32 and divides the inspection voltage in cooperation with the electric resistance of the transistor 35.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to an array substrate of a liquid crystal display device, and more particularly to an array substrate in which a plurality of pixel electrodes are integrated with a driving circuit for driving these pixel electrodes.

[0002]

2. Description of the Related Art In recent years, liquid crystal display technology has been applied to video equipment such as video projectors and viewfinders. For example, when three liquid crystal display devices (or liquid crystal display panels) are provided to display a color image, these liquid crystal display devices obtain red, green, and blue light obtained by dispersing white light with a dichroic mirror or the like. To selectively transmit the respective lights. The light transmittance distribution of each liquid crystal display device is controlled by a liquid crystal drive circuit connected through a plurality of connection pads provided in the liquid crystal display device. The transmitted light from these liquid crystal display devices is condensed by a lens so as to synthesize a color image at the display position.

Conventional video equipment is expensive because it generally has a large optical system such as a lens and a dichroic mirror, and occupies a lot of space. In order to make the optical system compact, it is necessary to maintain the resolution and reduce the size of the liquid crystal display device. For this reason, the pixel density of the liquid crystal display device has been maximized, and the area and spacing of the connection pads have been reduced accordingly.
However, since there is a limit to reducing the area and interval of the connection pads without impairing the connection reliability, a method has been proposed in which the liquid crystal drive circuit is incorporated in the liquid crystal display device to eliminate the connection pads.

Here, the structure of the above-mentioned liquid crystal display device will be schematically described. This liquid crystal display device generally includes an array substrate in which a plurality of pixel electrodes are arranged in a matrix,
The counter electrode includes a counter substrate formed corresponding to the matrix array of the pixel electrodes, and a liquid crystal layer held between the array substrate and the counter substrate. The array substrate has a plurality of scanning lines formed along rows of a plurality of pixel electrodes, a plurality of signal lines formed along columns of these pixel electrodes, and positions where corresponding scanning lines and corresponding signal lines intersect. And a plurality of thin film transistors (TFTs) that are formed adjacent to each other and form a switching element. Each TFT
Has a gate connected to one scanning line, a source connected to one pixel electrode, and a drain connected to one signal line. The liquid crystal drive circuit is composed of a scanning line driver, a signal line driver, and the like which are formed in an area outside the matrix array of pixel electrodes on the array substrate. The plurality of scanning lines are connected to the scanning line driver, and the plurality of signal lines are connected to the signal line driver. The scanning line driver sequentially supplies a scanning signal to a plurality of scanning lines, and the signal line driver supplies a video signal to a plurality of signal lines each time the TFTs in each row are simultaneously turned on by the scanning signal. As a result, each pixel electrode is
The pixel potential is set according to the video signal supplied via the. The light transmittance distribution of the liquid crystal display device is set according to the distribution of the voltage applied to the liquid crystal layer between the counter electrode set to the reference potential and these pixel electrodes.

Such a liquid crystal display device is usually manufactured through a process of forming an array substrate, a process of forming a counter substrate, and a bonding process of integrating the array substrate and the counter substrate with a liquid crystal layer. In the manufacturing process of the array substrate, the liquid crystal driving circuit is integrated with the display circuit including the pixel electrode, the scanning line, the signal line, and the TFT. In this case, the array substrate is formed in a state where the plurality of scanning lines and the plurality of signal lines are directly connected to the liquid crystal drive circuit. In this state, the display circuit and the liquid crystal drive circuit cannot be inspected except to operate the display circuit via the liquid crystal drive circuit. That is, since the display circuit and the liquid crystal drive circuit cannot operate individually, it is not always possible to detect all defects existing in wiring such as signal lines and scanning lines. Even if the presence of a defect can be detected, it is difficult to specify where the defect exists in the wiring. Therefore, an operation test is performed to confirm that the completed liquid crystal panel is a good product. When the operation of the liquid crystal display device is not normal, the liquid crystal display device is discarded as a defective product. Even though it is clear that defects are present in the array substrate, the counter substrate and the liquid crystal layer are also discarded together with the array substrate because the array substrate cannot be properly separated from the counter substrate and the liquid crystal layer.

[0006]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention For example, JP-A-63-5
No. 2121 and "S14-2 3.7-i" of JAPAN DISPLAY '92 .561
n.HDTV Poly-Si TFT-LCD Light Valve with Fully Int
egrated Peripheral Drivers "provides multiple inspection transistors at the ends of wiring such as scan lines and signal lines.
A technique for inspecting an array substrate using these inspection transistors is disclosed.

In Japanese Patent Laid-Open No. 63-52121, the source / drain paths of a plurality of inspection transistors are connected to corresponding wirings, and the gate of each inspection transistor is connected to the source / drain path of an adjacent inspection transistor. It has a circuit structure. Assuming that defects occur in all even-numbered wirings, it may be observed that defects occur not only in these wirings but also in all odd-numbered wirings. Therefore, accurate inspection is difficult.

JAPAN DISPLAY '92 .561 "S14-2 3.7-in. H
DTV Poly-Si TFT-LCD Light Valvewith Fully Integrat
The ed Peripheral Drivers "has a circuit structure in which the source / drain paths of a plurality of inspection transistors are respectively connected to corresponding wirings, and the gates of these inspection transistors are commonly connected in each group. When it occurs in the inspection transistor itself, it makes accurate inspection difficult, that is, when the gate insulation of one inspection transistor is broken, the gate of this inspection transistor is electrically short-circuited to the corresponding wiring. It may be observed that a defect has occurred in the inspection transistors belonging to the same group as this inspection transistor, and further that a defect has occurred in all the wirings connected to these transistors.

In the techniques of these documents, the addition of the inspection transistor tends to rather reduce the yield and reliability of the array substrate. Further, the circuit structures of these technologies cannot make it possible to inspect the display circuit including the scanning line, the signal line, and the TFT without the liquid crystal drive circuit.
Particularly, in Japanese Patent Laid-Open No. 63-52121, the wiring structure of the array substrate is complicated by the wiring added for switching the inspection transistors in groups. It is an object of the present invention to provide an array substrate of a liquid crystal display device that enables an inspection to accurately identify a defect site without significantly complicating the structure.

[0010]

The object of the present invention is to provide an insulating substrate, a plurality of pixel electrodes arranged in a matrix on the insulating substrate, and a row of the plurality of pixel electrodes on the insulating substrate. A set of first pixel wirings, a set of second pixel wirings formed on the insulating substrate along a plurality of pixel electrode columns, and an intersection of the first and second pixel wirings. A plurality of switching elements which are formed adjacent to each other on the insulating substrate and which supply the video signal from the corresponding second pixel wiring to the corresponding pixel electrode in response to the scanning signal from the corresponding first pixel wiring, respectively. An inspection auxiliary circuit that senses the potentials of a set of first and second pixel wirings, and the inspection auxiliary circuit has a gate of 1
A plurality of inspection thin film transistors respectively connected to the set pixel wirings, and an inspection wiring portion connected to the source / drain paths of these inspection thin film transistors for detecting an operating state according to the gate potential 1
The inspection wiring part has a first and second inspection pad in which source / drain paths of a plurality of inspection thin film transistors are connected in parallel with each other, and an inspection voltage is based on the first inspection pad. Achieved by an array substrate of a liquid crystal display device including a third inspection pad to be applied and a resistance element connected between the second and third inspection pads to divide an inspection voltage in cooperation with electric resistances of a plurality of inspection thin film transistors. To be done.

In the array substrate of the present invention, the gates of the inspection thin film transistors are connected to a set of pixel wirings, respectively, and the inspection wiring portion detects the operating state according to the gate potential. Connected to the path. During inspection of the array substrate, a voltage such as a scanning signal or a video signal is supplied to the switching element via each pixel wiring. For example, disconnection, short circuit,
When a defect such as element destruction exists in this pixel wiring or the switching element connected to this pixel wiring, the potential of this pixel wiring changes depending on the type of this defect.
Therefore, the inspection thin film transistor operates so as to sense the potential of this pixel wiring. Specifically, the conductivity of the inspection thin film transistor, that is, the electric resistance is controlled by the potential of the pixel wiring, and is set to a value that reflects the type of defect. Therefore, the defect information as described above can be obtained by passing a current through the inspection thin film transistor using the inspection wiring portion and measuring the voltage drop in these inspection thin film transistors. Further, by sequentially collecting defect information for one set of all pixel wirings, it is possible to specify in which of these pixel wirings a defect exists.

Further, the inspection wiring portion is electrically insulated from the pixel wiring by the gate insulating film of the inspection thin film transistor. In this structure, a gate wiring and a source / drain path of one inspection thin film transistor are electrically connected to each other due to a defect such as a defective gate insulating film. The conventional problem of short circuit can be avoided.

Further, if the source / drain paths of a plurality of thin film transistors for inspection are connected in parallel using a common line, it is possible to prevent the wiring structure of the array substrate from becoming extremely complicated to enable reliable inspection. . Further, when the switching element is composed of a thin film transistor, these can be formed simultaneously with the inspection thin film transistor in the same manufacturing process. This means that no separate process is required to form the test thin film transistor.

As described above, according to the present invention, there is no need for a drastic change in circuit components or a complicated wiring structure.
It is possible to reliably detect a defect existing in the pixel wiring or the switching element. Since these defect inspections can be performed almost independently, it is easy to specify the location of the defect.
Further, with respect to the defect of the inspection thin film transistor included in the inspection auxiliary circuit, the defect can be removed to prevent the decrease in the yield of the array substrate.

Further, after the array substrate is manufactured or after the main circuit components of the array substrate are formed, the defect inspection can be performed by using the inspection auxiliary circuit. This defect inspection can be performed regardless of the manufacturing process of the counter substrate and the bonding process of integrating the array substrate and the counter substrate with the liquid crystal layer. Of course, it is not necessary to perform a defect inspection after the liquid crystal display device is completed. Therefore, it is not necessary to discard the defect-free counter substrate and the liquid crystal layer due to the defects generated in the array substrate, and it is possible to improve the yield of the entire liquid crystal display device.

As described above, it is possible to detect electrical circuit defects early in the manufacturing process of the liquid crystal display device.
This is preferable not only for reducing the manufacturing cost due to the improvement in yield but also for maintaining the reliability of the liquid crystal display device.

[0017]

DETAILED DESCRIPTION OF THE INVENTION A liquid crystal display device according to a first embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 schematically shows the planar structure of this liquid crystal display device, and FIG. 2 schematically shows the cross-sectional structure of this liquid crystal display device. This liquid crystal display device includes an array substrate 100 in which m × n pixel electrodes 1 are arranged in a matrix, and a counter substrate 200 in which a single counter electrode 2 is provided corresponding to a matrix array of these pixel electrodes 1. A liquid crystal layer 300 held between the array substrate 100 and the counter substrate 200, and a polarizing plate 101 attached to the array substrate 100 and the counter substrate 200 on the opposite side of the liquid crystal layer 300.
And 201.

In the array substrate 100, m × n pixel electrodes 1 are formed on a transparent glass substrate 102. The array substrate 100 further includes n scanning lines 3 (Y1 to Yn) formed along the rows of the pixel electrodes 1, and m signal lines 4 formed along the columns of the pixel electrodes 1.
(X1 to Xm), and m × n thin film transistors (TF) that are formed adjacent to the intersections of the corresponding scanning lines 3 and the corresponding signal lines 4 to form switching elements.
T) 5. Each TFT 5 has a gate 5G connected to one scanning line 3, a source electrode 5S connected to one pixel electrode 1, and a drain electrode 5D connected to one signal line 4. The gate electrode 5G is an electrode formed as a part of the scanning line 3. The TFT 5 is a polysilicon semiconductor layer 5T formed on the glass substrate 102.
And a gate insulating film 5I formed between the semiconductor layer 5T and the gate electrode 5G. The source electrode 5S and the drain electrode 5D are the source and drain regions 5 formed in the semiconductor layer 5T on both sides of the gate electrode 5G.
Electrodes in contact with SC and 5DC. The drain electrode 5D is formed as a part of the signal line 4. The pixel electrode 1 is formed in contact with the source electrode 5S. The array substrate 100 further has a storage capacitance line 1A formed on the insulating glass substrate 102 substantially parallel to the scanning lines 3.
Having. A part of the storage capacitance line 1A overlaps with the pixel electrode 1, capacitively couples with the pixel electrode 1 through the protective film 103 to form a storage capacitance CS, and is electrically connected to the counter electrode 2 of the counter substrate 200. The above-described pixel electrode 1, scanning line 3, signal line 4, and TFT 5 form a display circuit 6 on the array substrate 100. The array substrate 100 further has a liquid crystal drive circuit 7 formed for driving the display circuit 6 at a peripheral portion of the pixel electrode 1 located outside the matrix array. This liquid crystal drive circuit 7 is provided with n scanning lines 3
A scanning line driver 8 connected to the signal lines, a signal line driver 9 connected to the m signal lines 4, and a liquid crystal controller 10 for controlling the scanning line driver 8 and the signal line driver 9. The scanning line driver 8 and the signal line driver 9 are configured using shift registers or the like as conventionally known. The scanning line driver 8 uses these n scanning lines 3
To the T line of each row.
A video signal is supplied to the m signal lines 4 each time the FT 5 is simultaneously turned on by a scanning signal. As a result, each pixel electrode 1 is set to a pixel potential according to the video signal supplied via the corresponding TFT 5. The display circuit 6 and the liquid crystal drive circuit 7 are covered with a protective film 103, and the protective film 103 and the pixel electrode 1 are covered with an alignment film 104.

The counter substrate 200 is a light shielding layer 203 formed on a transparent glass substrate 202 for shielding unnecessary light.
The color stripe portion 20 is formed on the glass substrate 202 and is surrounded by the light shielding layer 203 to filter the light transmitted through the pixel electrode 1 provided on the array substrate 100.
And 4. The counter electrode 2 is formed so as to cover the light shielding layer 203 and the color stripe portion 204, and the alignment film 206 is formed so as to cover the counter electrode 2.

The liquid crystal layer 300 is composed of a liquid crystal composition sealed in the gap between the alignment film 104 of the array substrate 100 and the alignment film 206 of the counter substrate 200. The counter electrode 2 constitutes a liquid crystal capacitance CLC by capacitively coupling with each pixel electrode 1, and also a ground pad G set to a reference potential of 0V, for example.
Connected to ND. The light transmittance distribution of the liquid crystal display device has a liquid crystal layer 300 between the counter electrode 2 and these pixel electrodes 1.
It is set according to the distribution of the voltage applied to. 1 and 3, the counter electrode 2 and the liquid crystal layer 300 are shown as equivalent circuit elements.

FIG. 3 shows in detail the circuit formed on the array substrate 100. The matrix array of the pixel electrodes 1 is formed in the display region SR corresponding to the region of the counter substrate 200 where the counter electrode 2 is formed. This array substrate 10
Reference numeral 0 includes an inspection auxiliary circuit 20 formed outside the display area SR. This inspection auxiliary circuit 20 has n scanning lines 3
(Y1-Yn) and TF connected to these scanning lines 3
Scan line inspection unit 3 used for inspecting defects of T5
0, m signal lines 4 (X1 to Xm) and a signal line inspection unit 50 used to inspect for defects in the TFTs 5 connected to these signal lines 4.

The scanning line inspection section 30 includes an inspection potential pad 31.
, Monitor pad 32, and these pads 31 and 32
A resistance element 33 connected between them, an inspection wiring 34 connected in parallel with the signal line 4 and connected to the monitor pad 32, source / drain paths connected between the inspection wiring 34 and the ground pad GND, and corresponding N inspection thin film transistors (gates for inspection T having a gate connected to the scanning line 3)
FT) 35. At the time of inspection, the inspection voltage Vh is supplied between the inspection potential pad 31 and the ground pad GND. (The inspection voltage Vh is determined in accordance with the threshold voltage of the inspection TFT 35 so that the inspection TFT 35 conducts under the scanning signal.) The signal line inspection unit 50 includes the inspection potential pad 51, the monitor pad 52, and these. A resistance element 53 connected between the pads 51 and 52, an inspection wiring 54 set in parallel with the scanning line 3 and connected to the monitor pad 52, and a source / source connected between the inspection wiring 54 and the ground pad GND, respectively. M having a drain path and a gate connected to the corresponding signal line 4
It has a thin film transistor for inspection (inspection TFT) 55. During the inspection, the inspection voltage Vh is the inspection potential pad 5
1 and the ground pad GND. (The inspection voltage Vh is determined in accordance with the threshold voltage of the inspection TFT 55 so that the inspection TFT 55 conducts under a video signal of a specific level.) In the above-mentioned liquid crystal display device, the array substrate 100 is usually manufactured in the opposite process. A manufacturing process of the substrate 200,
Then, the array substrate 100 and the counter substrate 200 are integrated with the liquid crystal layer 300 through a bonding process to complete the process. In the manufacturing process of the array substrate 100, the inspection TFTs 35 and 55 are formed by the same process as the TFT 5. Therefore, these TFTs 5, 35, and 55 are
Are composed of the same material and the same layer structure. However, TF
T5 has an element size capable of obtaining an operation performance suitable for the switching operation, and each of the inspection TFTs 35 and 55 has an element size capable of obtaining an operation performance suitable for the potential sensing operation of the scanning line 3 and the signal line 4, respectively. Since these device dimensions can be defined, for example, by the photomask pattern used in the patterning process for TFTs 5, 35, and 55, no separate processing is required due to these device size differences.

Next, a defect inspection carried out after the array substrate 100 of the above-mentioned liquid crystal display device is manufactured or after the main circuit components of the array substrate 100 are formed will be described. First, the defect inspection using the scanning line inspection unit 30 will be described. In this defect inspection, the scanning line driver 8 is controlled to select n scanning lines 3 one by one and supply a scanning signal to the selected scanning line 3. The potentials of the scanning lines 3 depend on types of defects such as short circuit and disconnection of the scanning lines 3, element destruction of the TFT 5 connected to these scanning lines 3, and malfunction of the scanning line driver 8 connected to these scanning lines 3. Change depending on. Therefore, the potentials of the n scanning lines 3 are respectively sensed by the n inspection TFTs 35. The conductivity or electric resistance of these inspection TFTs 35 depends on the sense potential. Briefly, each inspection TFT 35 is made conductive by the potential of the corresponding scanning line 3 when the scanning signal is supplied, and is kept non-conductive by the potential of the corresponding scanning line 3 when the scanning signal is not supplied. The inspection voltage Vh is divided by the voltage divider composed of the parallel inspection TFT 35 and the resistance element 33, and the monitor output voltage corresponding to the voltage drop in the parallel circuit of the inspection TFT 35 is output to the monitor pad 32. . The monitor output voltage is measured for each scanning line 3 sequentially selected by the scanning line driver 8, and the location and type of the defect are specified based on the measurement result. (Scan line inspection unit 3
In the defect inspection using 0, the signal line driver 9 has m signal lines 4 in order to eliminate adverse effects due to variations in inspection conditions.
Are controlled to perform the operation of supplying the same video signal to all of them or supplying no video signal at all. ) When the scanning signal is supplied from the scanning line driver 8 to the selected scanning line 3, the monitor output voltage becomes the voltage level Von. This voltage level Von is Von = Vh / [Rx {Roff + Ron
(N-1)} / (Ron.Roff)} + 1].
(Here, Ron is the ON resistance of the inspection TFT 35, Roff
Is an OFF resistance of the inspection TFT 35, and Rx is a resistance element 33.
Is the electrical resistance value of. By the way, when Ron is a value sufficiently lower than Roff, the voltage level Von is Von =
It can be approximated by the formula Vh / (Rx / Ron + 1).

When the scan signal is not supplied from the scan line driver 8 to the selected scan line 3, the monitor voltage is the voltage level Vof.
becomes f. This voltage level Voff is Voff = Vh / (n
-Represented by Rx / Roff + 1).

Therefore, if the operation of the scanning line driver 8 is normal, the monitor output voltage substantially matches the voltage level Von regardless of the selected scanning line 3. If the monitor output voltage substantially matches the voltage level Voff when the particular scan line 3 is selected by the scan line driver 8, then the scan line driver 8 is considered defective. By the way, since the source / drain path of the TFT 5 is electrically separated from the current path from the inspection potential pad 31 to the ground pad GND through the source / drain path of the inspection TFT 35, the monitor output voltage is in the ON state of the TFT 5. And does not depend on the off state.

Further, when the adjacent k scanning lines 3 such as the first scanning line Y1 and the second scanning line Y2 are short-circuited to each other, the scanning signal is transmitted from the scanning line driver 8 to the first scanning line Y1. To the first scanning line Y1
To the second scanning line Y2. Therefore, the two inspection thin film transistors 35 connected to the first scanning line Y1 and the second scanning line Y2 are electrically connected together. The monitor output voltage becomes the voltage level Vonk when the scanning signal is supplied to the k scanning lines 3 as described above. This voltage level V
onk is Vonk = Vh / [Rx {k.Roff + Ron
(N−k)} / (Ron · Roff) +1]. Here, k is an integer larger than 1 and smaller than n. Ron
Is sufficiently lower than Roff, the voltage level Vonk is Vonk
= Vh / (k.Rx / Ron + 1).

A short circuit is detected because the monitor output voltage is at the voltage level Vonk when each of these k scan lines 3 is selected by the scan line driver 8. (Also, for example, when a single scanning line 3 such as the first scanning line Y1 is disconnected, the parasitic capacitance of this scanning line Y1 decreases. In this case, the potential of the first scanning line Y1 is the scanning signal. Changes faster than usual after being supplied from the scan line driver 8. Therefore, the above-mentioned disconnection is detected from the transition of the monitor output voltage to the voltage level Von in a shorter time than usual. The parasitic capacitance also changes due to element breakdown of the TFT 5 connected to the scanning line 3. Therefore, when a difference in transition time of the monitor output voltage occurs, disconnection of the scanning line 3 or element breakdown of the TFT 5 occurs. Then, the defect inspection using the signal line inspection unit 50 will be described.
In this defect inspection, the signal line driver 9 uses the m signal lines 4
Are selected one by one, and the inspection TFT 5 is connected to the selection signal line 4.
5 is controlled so as to supply a video signal of a specific level for conduction. The potentials of these signal lines 4 are the types of defects such as short circuit and disconnection of these signal lines 4, element destruction of the TFT 5 connected to these signal lines 4, and malfunction of the signal line driver 9 connected to these signal lines 4. Change depending on. Therefore, the potentials of the m signal lines 4 are respectively sensed by the m inspection TFTs 55. The conductivity or electric resistance of these inspection TFTs 55 depends on the sense potential. Simply put, each inspection TFT5
5 is made conductive by the potential of the corresponding signal line 4 when the video signal is supplied, and is kept non-conductive by the potential of the corresponding signal line 4 when the video signal is not supplied. Inspection voltage Vh
Is divided by a voltage divider composed of these parallel inspection TFT 55 and resistance element 53.
The monitor output voltage corresponding to the voltage drop in the parallel circuit is output to the monitor pad 52. The monitor output voltage is measured for each of the signal lines 4 sequentially selected by the signal line driver 9, and the location and type of the defect are specified based on the measurement result. The location and type of these defects are
Since it is specified in the same format as the case of the scanning line inspection unit 30, duplicate description will be omitted. (In the defect inspection using the signal line inspection unit 50, in order to eliminate the adverse effect due to the variation of the inspection conditions, the scanning line driver 8 supplies the scanning signal to one scanning line 3 or does not supply the scanning signal at all. In the array substrate of the liquid crystal display device according to the first embodiment, the scan line driver 8 malfunctions, the scan line 3 connected to the scan line driver 8 is short-circuited and disconnected, and the scan line 3 is connected. Defects such as element destruction of the connected TFT 5 can be found by measuring the monitor output voltage supplied to the monitor pad 32. In addition, the signal line driver 9 malfunctions, the signal line 4 connected to this signal line driver 9 is short-circuited and disconnected, and the TF connected to these signal lines 4 is short-circuited.
Defects such as element destruction at T5 can be found by measuring the monitor output voltage supplied to the monitor pad 52.

Further, each scanning line 3 has a corresponding inspection T.
It is connected to the gate of FT35, and this gate is the inspection wiring 3
The gate insulating film electrically insulates the source / drain path of the inspection TFT 35, which is connected to the inspection TFT 4. If a defect such as poor insulation of the gate insulating film is present in the TF for inspection,
If present in T35, this is this inspection TFT3.
This causes a scanning signal to be supplied to the inspection wiring 34 from the scanning line 3 connected to the gate of No. 5. On the other hand, each signal line 4 is connected to the gate of the corresponding inspection TFT 55, and the gate is electrically insulated from the source / drain path of the inspection TFT 55 connected to the inspection wiring 54 by the gate insulating film. If a defect such as a defective insulation of the gate insulating film exists in the inspection TFT 55, the image signal supplied to the signal line 4 connected to the gate of the inspection TFT 55 is supplied to the inspection wiring 54. Cause.

However, such an obstacle can be eliminated by disconnecting the gate of the defective inspection TFT 35 or 55 from the scanning line 3 or the signal line 4 by using, for example, a laser repair device. In this case, the defect inspection of the array substrate 100 becomes substantially infeasible, but the array substrate can be used for manufacturing the liquid crystal display device, assuming that other components are not defective. If you confirm that the display performance of the manufactured liquid crystal display device is satisfactory,
This liquid crystal display device can be certified as a defect-free product.

Further, the inspection TFTs 35 and 55 are T
Since it can be formed by the same manufacturing process as FT5, an independent manufacturing process is not required. In addition, the TFT 35
The element size difference between the TFTs 5 and 55 and the TFT 5 can be defined by the photomask pattern used in the patterning process for forming them. That is, the TFT 35
And 55 are T without adding a complicated manufacturing process.
It can be formed on the array substrate 100 together with the FT5.

In this embodiment, the voltage drop in the parallel circuit of the inspection TFT 35 (or 55) is measured by the monitor pad 32 (or 52) as the monitor output voltage, but the parameter other than the voltage should be measured. You can also For example, under the inspection voltage Vh, the inspection TFT 35 (or 5
It is also possible to change the wiring structure of the array substrate 100 so as to measure the value of the current flowing through the parallel circuit of 5) and find the above-mentioned defect from the measured current value. Also,
It is also possible to measure the electric resistance of the parallel circuit of the inspection TFT 35 (or 55) using the ground pad GND and the monitor pad 32. In the measurement of this electric resistance, the inspection voltage Vh does not need to be applied between the inspection potential pad 31 (or 51) and the ground pad GND.

The liquid crystal display device according to the second embodiment of the present invention will be described below. FIG. 4 shows a circuit formed on the array substrate of this liquid crystal display device. This liquid crystal display device is shown in FIG.
-It is similar to the liquid crystal display device of the first embodiment described with reference to FIG. Therefore, in FIG. 4, the same parts are designated by the same reference numerals, and the duplicate description will be omitted.

In the array substrate of this liquid crystal display device, the driver inspection section 60 is provided in the scanning line driver 8 in order to detect the malfunction of the scanning line driver 8 more reliably. In the present embodiment, in order to facilitate understanding of the defect inspection by the driver inspection unit 60, the scanning line inspection unit 30 and the signal line inspection unit 50 shown in FIG. 4 are not provided. The scanning line driver 8 generally has n output buffers 8A in order to sequentially supply scanning signals having a voltage amplitude suitable for turning on the TFT 5 to the n scanning lines 3 (Y1-Yn). . Each output buffer 8A is a CM as conventionally known.
It is composed of an OS transistor and converts a scanning signal into a voltage amplitude applied between the power supply terminals VDD and VSS shown in FIG.

The driver inspection section 60 includes the inspection potential pad 31.
D, a monitor pad 32D, a resistance element 33D connected between these pads 31D and 32D, an inspection wiring 34D set in parallel with the signal line 4 and connected to the monitor pad 32D, and each inspection wiring 34D and ground. Pad GN
It has a source / drain path connected between D and n inspection thin film transistors (inspection TFTs) 35D having a gate connected to the input terminal of the corresponding output buffer 8A. During the inspection, the inspection voltage Vh is the inspection potential pad 31.
It is supplied between D and the ground pad GND. (The inspection voltage Vh is determined in accordance with the threshold voltage of the inspection TFT 35D so that the inspection TFT 35D conducts under the scanning signal input to the output buffer 8A.) That is, the driver inspection unit 60 of the inspection TFT 60 operates. ) 35D has substantially the same configuration as the scanning line inspection unit 30 shown in FIG. 3 except that 35D senses the potential of the input terminal of the output buffer 8A.

According to the second embodiment, the scanning line driver 8
N scanning lines 3 (Y1-Y selectively driven by
n) are electrically separated from the inspection TFT 35D by the output buffer 8A of the scanning line driver 8. The potential of each scanning line 3 is the TF connected to this scanning line 3.
The defect generated at T5 changes like the first embodiment. For example, if the electric resistance between the gate and the source of the TFT 5 is extremely lowered due to a defective gate insulating film, the potential of the scanning line 3 is significantly lowered from the level of the scanning signal supplied to the scanning line 3. Therefore, if the potential of the scanning line 3 is sensed for the inspection of the scanning line driver 8 as in the first embodiment, the scanning line driver 8 will not operate even if the scanning signal is supplied to this scanning line 3. May be considered bad. However, in the second embodiment, the inspection driver 8 is inspected by using the inspection TFT 35D that senses the potential of the input end of the output buffer 8A that is electrically separated from the scanning line 3. That is, the potential at the input end of the output buffer 8A is mainly the display circuit 6 such as disconnection, short circuit of the scanning line 3 and defective gate insulation of the TFT 5.
Since it is not affected by the defect occurring inside, the malfunction of the scanning line driver 8 can be reliably distinguished from the defect of the display circuit 6 in the inspection procedure of the first embodiment.

In order to detect the malfunction of the signal line driver 9 with certainty, a driver inspection unit configured to sense the potential at the input end of the output buffer of the signal line driver 9 is provided in the signal line driver 9. It may be provided.

The liquid crystal display device according to the third embodiment of the present invention will be described below. FIG. 5 shows a circuit formed on the array substrate of this liquid crystal display device. This liquid crystal display device is shown in FIG.
-Similar to the liquid crystal display device of the first and second embodiments described with reference to FIG. Therefore, in FIG. 5, the same parts are denoted by the same reference numerals, and duplicated description will be omitted.

The array substrate of this liquid crystal display device is shown in FIG.
The scanning line inspection unit 30 shown in FIG. 4 and the driver inspection unit 60 shown in FIG. 4 are provided. In the present embodiment, the scanning line inspection unit 3
In order to facilitate understanding of the defect inspection by the combination of 0 and the driver inspection unit 60, the signal line inspection unit 50 shown in FIG.
Is not provided.

The scanning line inspection section 30 includes an inspection potential pad 31.
, Monitor pad 32, and these pads 31 and 32
A resistance element 33 connected between them, an inspection wiring 34 connected in parallel with the signal line 4 and connected to the monitor pad 32, source / drain paths connected between the inspection wiring 34 and the ground pad GND, and corresponding It has n thin film transistors for inspection (inspection TFTs) 35 having a gate connected to the output terminal of the output buffer 8A. At the time of inspection,
The inspection voltage Vh is the inspection potential pad 31 and the ground pad G.
It is supplied between ND.

The driver inspection section 60 includes the inspection potential pad 31.
D, a monitor pad 32D, a resistance element 33D connected between these pads 31D and 32D, an inspection wiring 34D set in parallel with the signal line 4 and connected to the monitor pad 32D, and each inspection wiring 34D and ground. Pad GN
It has a source / drain path connected between D and n inspection thin film transistors (inspection TFTs) 35D having a gate connected to the input terminal of the corresponding output buffer 8A. During the inspection, the inspection voltage Vh is the inspection potential pad 31.
It is supplied between D and the ground pad GND.

In the above configuration, first, the monitor pad 32D
Is monitored for inspection of the scan line driver 8,
After that, the potential of the monitor pad 32 is monitored mainly for the inspection of defects generated in the display circuit 6.

According to the third embodiment, the scanning line driver 8
N scanning lines 3 (Y1-Y selectively driven by
n) are electrically separated from the inspection TFT 35D by the output buffer 8A of the scanning line driver 8. The potential of each scanning line 3 is the TF connected to this scanning line 3.
The defect generated at T5 changes similarly to the second embodiment. As described in the second embodiment, for example, this TF
When the electric resistance between the gate and the source of T5 is extremely lowered due to the defective gate insulating film, the potential of the scanning line 3 is significantly reduced from the level of the scanning signal supplied to the scanning line 3. Therefore, if the potential of the scanning line 3 is sensed by the inspection TFT 35 for the inspection of the scanning line driver 8, the operation of the scanning line driver 8 is defective even though the scanning signal is supplied to the scanning line 3. May be considered to be Therefore, the inspection TFT 3
Output buffer 8 in which 5D is electrically separated from scan line 3
It is used to detect the potential at the input end of A. That is, the potential at the input end of the output buffer 8A is not affected by defects mainly occurring in the display circuit 6, such as disconnection of the scanning line 3, short circuit, and defective gate insulation of the TFT 5. Therefore, the malfunction of the scanning line driver 8 can be reliably distinguished from the defect of the display circuit 6 by the inspection procedure of the first embodiment. On the other hand, the inspection TFT 35 has the potential of the scanning line 3 which mainly depends on the type of defects such as disconnection, short circuit of the scanning line 3 and defective gate insulation of the TFT 5 as in the first embodiment. Used to detect.

That is, since the scanning line driver 8 and the display circuit 6 can be inspected substantially independently of each other, the location of the defect can be identified more easily than in the first and second embodiments.

The liquid crystal display device according to the fourth embodiment of the present invention will be described below. FIG. 6 shows a circuit formed on the array substrate of this liquid crystal display device. This liquid crystal display device is shown in FIG.
-It is similar to the liquid crystal display device of the first embodiment described with reference to FIG. Therefore, in FIG. 6, the same parts are designated by the same reference numerals, and the overlapping description will be omitted.

In the array substrate of this liquid crystal display device, the scanning line inspection unit 70 is further provided in order to more accurately detect defects mainly in the display circuit 6 such as disconnection of the scanning line 3, short circuit and defective gate insulation of the TFT 5. To be The scanning line inspection unit 70 is arranged on the opposite side of the scanning line inspection unit 30 outside the display region SR. In the present embodiment, the scanning line inspection unit 3
In order to facilitate understanding of the defect inspection by 0 and 70, the signal line inspection unit 50 shown in FIG. 3 is not provided.

The scanning line inspection section 30 includes an inspection potential pad 31.
, Monitor pad 32, and these pads 31 and 32
A resistance element 33 connected between them, an inspection wiring 34 that is set in parallel with the signal line 4 and connected to the monitor pad 32, a source / drain path connected between the inspection wiring 34 and the ground pad GND, and scanning. The line driver 8 and n inspection thin film transistors (inspection TFTs) 35 each having a gate connected to the corresponding scanning line 3 located between the display regions SR. At the time of inspection, the inspection voltage Vh is supplied between the inspection potential pad 31 and the ground pad GND. (The inspection voltage Vh is determined in accordance with the threshold voltage of the inspection TFT 35 so that the inspection TFT 35 conducts under the scanning signal.) The scanning line inspection unit 70 includes the inspection potential pad 31E, the monitor pad 32E, and these. A resistance element 33E connected between the pads 31E and 32E, an inspection wiring 34E connected in parallel with the signal line 4 and connected to the monitor pad 32E, and a source connected between the inspection wiring 34E and the ground pad GND. There are n inspection thin film transistors (inspection TFTs) 35E having gates connected to the drain path and the end of the corresponding scanning line 3 far from the inspection TFT 35. During the inspection, the inspection voltage Vh is the inspection potential pad 31.
It is supplied between E and the ground pad GND. (The inspection voltage Vh is determined corresponding to the threshold voltage of the inspection TFT 35E so that the inspection TFT 35E conducts under the scanning signal.) In the present embodiment, the two inspection TFTs 35 and 35E.
Are provided for each scanning line 3. In this case, the potentials of the monitor pads 32 and 32E may cause malfunction of the scanning line driver 8,
The scanning line 3 connected to the scanning line driver 8 is monitored to detect defects such as short circuit and disconnection of the scanning line 3 and destruction of the TFT 5 connected to the scanning line 3. That is, first, it can be confirmed by the inspection method of the first embodiment that the scanning line driver 8 operates normally and that none of the scanning lines 3 is short-circuited with the other scanning lines 3. After this confirmation, the potential of the monitor pad 32 and the potential of the monitor pad 32E are measured for each scanning line 3, and the disconnection of the scanning line 3 can be found by comparing the measurement results. If the wire is broken, the monitor pad 32 becomes the voltage level Von described in the first embodiment, and the monitor pad 32E becomes the voltage level Von.
It will be off. In addition, these measurement results show that the voltage level Vof
If neither f nor Von is present, it can be considered that the gate insulation failure has occurred in any of the TFTs 5 connected to the scanning line 3. According to the fourth embodiment, it is possible to more reliably distinguish the disconnection of the scanning line 3 and the element destruction of the TFT 5 from the above-mentioned defects in the display circuit 6.

A liquid crystal display device according to the fifth embodiment of the present invention will be described below. FIG. 7 shows a circuit formed on the array substrate of this liquid crystal display device. This liquid crystal display device is shown in FIG.
-It is similar to the liquid crystal display device of the first to fourth embodiments described with reference to FIG. 6. Therefore, in FIG. 7, the same parts are designated by the same reference numerals, and the duplicated description will be omitted.

The array substrate of this liquid crystal display device has a characteristic structure of the scanning line inspection unit 30, the signal line inspection unit 50, the driver inspection unit 60, and the scanning line inspection unit 70 used in the first to fourth embodiments. Including all. Further, in this array substrate, the driver inspection section 80 is provided in the scanning line driver 9 in order to detect the malfunction of the signal line driver 9 more surely, and the signal line inspection section 90 is connected to the signal line 4 for disconnection, short circuit and TFT 5. It is further provided mainly for more accurately detecting a defect of the display circuit 6 such as the destruction failure of the display circuit 6.

The scanning line inspection section 30 includes an inspection potential pad 31.
, Monitor pad 32, and these pads 31 and 32
A resistance element 33 connected between them, an inspection wiring 34 that is set in parallel with the signal line 4 and connected to the monitor pad 32, a source / drain path connected between the inspection wiring 34 and the ground pad GND, and scanning. The line driver 8 and n inspection thin film transistors (inspection TFTs) 35 each having a gate connected to the corresponding scanning line 3 located between the display regions SR. At the time of inspection, the inspection voltage Vh is supplied between the inspection potential pad 31 and the ground pad GND. (The inspection voltage Vh is determined in accordance with the threshold voltage of the inspection TFT 35 so that the inspection TFT 35 conducts under the scanning signal.) The signal line inspection unit 50 includes an inspection potential pad 51, a monitor pad 52, and these. A resistance element 53 connected between the pads 51 and 52, an inspection wiring 54 set in parallel with the scanning line 3 and connected to the monitor pad 52, and a source / source connected between the inspection wiring 54 and the ground pad GND, respectively. There are m inspection thin film transistors (inspection TFTs) 55 having gates connected to the drain path and the corresponding signal line 4 located between the signal line driver 9 and the display region SR. At the time of inspection, the inspection voltage Vh is supplied between the inspection potential pad 51 and the ground pad GND. (The inspection voltage Vh is determined corresponding to the threshold voltage of the inspection TFT 55 so that the inspection TFT 55 conducts under a video signal of a specific level.) The driver inspection unit 60 includes an inspection potential pad 31D and a monitor pad 32D. A resistance element 33D connected between these pads 31D and 32D, and an inspection wiring 34D connected in parallel with the signal line 4 and connected to the monitor pad 32D,
Source / drain paths connected between the inspection wiring 34D and the ground pad GND and the corresponding output buffer 8A.
N inspection thin film transistors (inspection TFTs) 35D each having a gate connected to the input terminal of. At the time of inspection, the inspection voltage Vh is supplied between the inspection potential pad 31D and the ground pad GND. (The inspection voltage Vh is determined in accordance with the threshold voltage of the inspection TFT 35D so that the inspection TFT 35D conducts under the scanning signal input to the output buffer 8A.) That is, the driver inspection section 60 of the driver inspection unit 60 operates. ) 35D is configured substantially the same as the scan line inspection unit 30 except that each senses the potential at the input end of the output buffer 8A.

The scanning line inspection section 70 includes the inspection potential pad 31E.
A monitor pad 32E, a resistance element 33E connected between these pads 31E and 32E, an inspection wiring 34E connected in parallel to the signal line 4 and connected to the monitor pad 32E, and an inspection wiring 34E and a ground pad, respectively. GND
Source / drain path connected between and TF for inspection
N inspection thin film transistors (inspection TFTs) having a gate connected to the end of the corresponding scanning line 3 far from T35
35E. At the time of inspection, the inspection voltage Vh is supplied between the inspection potential pad 31E and the ground pad GND. (The inspection voltage Vh is determined in accordance with the threshold voltage of the inspection TFT 35E so that the inspection TFT 35E conducts under the scanning signal.) The driver inspection unit 80 includes the inspection potential pad 51D, the monitor pad 52D, and these pads. A resistance element 53D connected between 51D and 52D, an inspection wiring 54D set in parallel with the scanning line 3 and connected to the monitor pad 52D,
M inspection thin film transistors (inspection TFTs) 55D each having a source / drain path connected between the inspection wiring 54D and the ground pad GND and a gate connected to the input terminal of the corresponding output buffer 9A of the signal line driver 9
And At the time of inspection, the inspection voltage Vh is supplied between the inspection potential pad 51D and the ground pad GND. (The inspection voltage Vh is determined in accordance with the threshold voltage of the inspection TFT 55D so that the inspection TFT 55D conducts under the video signal of the specific level input to the output buffer 9A.) That is, the driver inspection unit 80 is The inspection TFT 55D has substantially the same configuration as the signal line inspection unit 50 except that the inspection TFT 55D senses the potential at the input end of the output buffer 9A.

The signal line inspection section 90 includes the inspection potential pad 51E.
A monitor pad 52E, a resistance element 53E connected between these pads 51E and 52E, an inspection wiring 54E connected in parallel with the scanning line 3 and connected to the monitor pad 52E, and an inspection wiring 54E and a ground pad, respectively. GND
Source / drain path connected between and TF for inspection
M inspection thin film transistors (inspection TFTs) 55 having a gate connected to the end of the signal line 4 far from T55
With E and. At the time of inspection, the inspection voltage Vh is supplied between the inspection potential pad 51E and the ground pad GND.
(The inspection voltage Vh is determined corresponding to the threshold voltage of the inspection TFT 55E so that the inspection TFT 55E conducts under a video signal of a specific level.) In the fifth embodiment, the scanning line driver 8 selectively drives. The n scanning lines 3 (Y1 to Yn) are electrically separated from the inspection TFT 35D by the output buffer 8A of the scanning line driver 8. The potential of each scanning line 3 changes similarly to the second embodiment due to a defect generated in the TFT 5 connected to this scanning line 3. As described in the second embodiment, for example, when the electric resistance between the gate and the source of the TFT 5 is extremely lowered due to a defective gate insulating film, the potential of the scanning line 3 is supplied to the scanning line 3. It is significantly reduced from the level of the scanning signal. Therefore, if the potential of the scanning line 3 is sensed by the inspection TFT 35 for the inspection of the scanning line driver 8, the scanning line driver 8 is defective even though the scanning signal is supplied to this scanning line 3. May be considered. Therefore, the inspection TFT 35D is used to detect the potential of the input end of the output buffer 8A electrically separated from the scanning line 3. That is, the output buffer 8A
The potential at the input terminal of is not affected by defects mainly occurring in the display circuit 6, such as disconnection of the scanning line 3, short circuit, and defective gate insulation of the TFT 5. Therefore, the malfunction of the scanning line driver 8 can be reliably distinguished from the defect of the display circuit 6 by the inspection procedure of the first embodiment.

The m signal lines 4 (X1-Xm) selectively driven by the signal line driver 9 are electrically separated from the inspection TFT 55D by the output buffer 9A of the signal line driver 9. The potential of each signal line 4 changes due to a defect generated in the TFT 5 connected to this signal line 4. For example, when the electric resistance between the gate and the source of the TFT 5 is extremely lowered due to a defective gate insulating film, the potential of the signal line 4 is significantly lowered from the level of the video signal supplied to the signal line 4. Therefore, if the potential of the signal line 4 is sensed by the inspection TFT 55 for the inspection of the signal line driver 9, the signal line driver 9 is defective although the video signal is supplied to the signal line 4. May be considered. Therefore, the inspection TFT 55D is used to detect the potential of the input end of the output buffer 9A electrically separated from the signal line 4. That is, the output buffer 9A
Since the potential at the input end of the signal line 4 is not affected by defects such as disconnection, short circuit of the signal line 4 and defective gate insulation of the TFT 5, which are mainly generated in the display circuit 6, the signal line driver 9 of the first embodiment is subjected to the inspection procedure. Malfunctions can be reliably distinguished from defects in the display circuit 6.

In the fifth embodiment as described above, two inspection TFTs 35 and 35 are further provided as in the fourth embodiment.
E is provided for each scanning line 3. In this case, the potentials of the monitor pads 32 and 32E may cause malfunction of the scanning line driver 8, short circuit and disconnection of the scanning line 3 connected to this scanning line driver 8, element breakdown of the TFT 5 connected to this scanning line 3, and the like. Monitored to find defects. That is, first, it can be confirmed by the inspection procedure of the first embodiment that none of the scanning lines 3 is short-circuited to the other scanning lines 3 in the state where the scanning line driver 8 operates normally. After this confirmation, the potential of the monitor pad 32 and the potential of the monitor pad 32E are measured for each scanning line 3, and the disconnection of the scanning line 3 can be found by comparing the measurement results. If the wire is broken, the monitor pad 32 becomes the voltage level Von described in the first embodiment, and the monitor pad 32E becomes the voltage level Voff. If the measurement result is neither the voltage level Voff nor Von, the scanning line 3
It can be considered that defective gate insulation occurs in any of the TFTs 5 connected to the.

Two more inspection TFTs 55 and 55
E is provided for each signal line 4. In this case, the potentials of the monitor pads 52 and 52E are such that the signal line driver 9 malfunctions, the signal line 4 connected to the signal line driver 9 is short-circuited and disconnected, and the TFT 5 connected to the signal line 4 is destroyed. Monitored to find defects. That is, first, it can be confirmed by the inspection method of the first embodiment that none of the signal lines 4 is short-circuited to the other signal lines 4 while the signal line driver 9 is operating normally. After this confirmation, the potential of the monitor pad 52 and the potential of the monitor pad 52E are measured for each signal line 4, and the disconnection of the signal line 4 can be found by comparing the measurement results. If the wire is broken, the monitor pad 52 becomes the voltage level Von described in the first embodiment, and the monitor pad 52E becomes the voltage level Voff. If these measurement results are neither the voltage levels Voff nor Von, the signal line 4
It can be considered that element breakdown has occurred in any of the TFTs 5 connected to.

According to the fifth embodiment, among the defects in the display circuit 6, especially the disconnection of the scanning line 3, the disconnection of the signal line 4 and the defective gate insulation of the TFT 5 can be detected more reliably.

The defect inspection of the array substrate of the fifth embodiment is carried out as shown in FIGS. 8 and 9, for example. Step S
Steps 1 to S12 are performed to address the defects associated with scan line 3. Therefore, first, all the signal lines 4 are set in an electrically floating state and the scanning line driver 8 is driven. In step S1, the potential of the scanning line 3 sensed by the scanning line inspection unit 70 is checked. When it is detected in step S2 that the potential of the scanning line 3 is abnormal,
The potential of the scanning line 3 sensed by the scanning line inspection unit 30 is checked in step S3. In step S4, it is determined whether the disconnection of the specific scanning line 3 is detected from the check result. If no disconnection is detected, the potential of the scanning line 3 sensed by the driver inspection unit 60 is checked in step S5. In step S6, it is determined whether a malfunction of the scanning line driver 8 has been detected based on the check result. If this malfunction is not detected, the drive timing of the scan line 3 sensed by the scan line inspection units 70 and 30 is checked in step S7. In step S8, it is determined from the check result whether or not a short circuit between the specific scanning lines 3 has been detected. If this short circuit is not detected, step S9
Then, the scanning line driver 8 is driven with a specific potential applied to all the signal lines 4, and the scanning line inspection units 70 and 30 are driven.
The drive waveform of the scanning line 3 sensed at is checked.
In step S10, it is determined whether a short circuit between the specific scanning line 3 and the signal line 4 has been detected from the check result.

When a disconnection of the specific scanning line 3 is detected in step S4, a malfunction of the scanning line driver 8 is detected in step S6, a short circuit between the specific scanning lines 3 is detected in step S8, and If a short circuit between the specific scan line 3 and the signal line 4 is detected in step S10, it is determined in step S11 by actually observing whether repair work is possible. If possible, repair work is performed in step S12.

If there is no abnormality in step S2, if a short circuit between the specific scanning line 3 and the signal line 4 is not detected in step S10, and if repair work is performed in step S12, step S13 is executed. It

Steps S13 to S22 are executed in order to deal with the defect relating to the signal line 4. Therefore, the signal line driver 9 is driven with all the scanning lines 3 set in an electrically floating state. In step S13,
The potential of the signal line 4 sensed by the signal line inspection unit 90 is checked. When it is detected in step S14 that the potential of the signal line 4 is abnormal, the potential of the signal line 4 sensed by the signal line inspection unit 50 is checked in step S15. In step S16, it is determined whether the disconnection of the specific signal line 4 is detected from the check result. If no disconnection is detected, the potential of the signal line 4 sensed by the driver inspection unit 80 is checked in step S17. In step S18, it is determined from the check result whether a malfunction of the signal line driver 9 has been detected. If this malfunction is not detected, the drive timing of the signal line 4 sensed by the signal line inspection units 90 and 50 is checked in step S19. In step S20, it is determined from the check result whether a short circuit between the specific signal lines 4 has been detected.

When the disconnection of the specific signal line 4 is detected in step S16, the malfunction of the signal line driver 9 is detected in step S18, and the short circuit between the specific signal lines 4 is detected in step S20. Is step S2
It is judged by actually observing whether repair work is possible in 1. If possible, repair work is performed in step S22.

If the repair work is impossible in step S11 or S21, there is no abnormality in step S14, a short circuit between the specific signal lines 4 is not detected in step S20, and the repair work is performed in step S22. In this case, comprehensive evaluation is performed in step S23.
In this comprehensive evaluation, the array substrate in which no defect is detected or the defect is repaired is regarded as a product having no defect. The defective inspection thin film transistor is
It is separated from each wiring by the repair process. If the array substrate has a non-repairable defect, the substrate is discarded.

When detecting a defect relating to the signal line 4, the output voltage from the signal line driver 9 is set to a level sufficient to drive the inspection thin film transistor.
Defect inspection can also be performed in a different sequence. For example, this sequence may start with the step of detecting a defect on the signal line 4. The repair work may be performed after the comprehensive evaluation. However, this repair work should be performed during the manufacture of the array substrate to improve its reliability. For a defective array substrate that cannot be easily repaired, the substrate may be discarded without performing the repair work after considering the yield and the manufacturing cost.

Here, the characteristic configurations of the first to fifth embodiments will be supplemented. Array substrate 100 described above
Then, for example, the gates of the n inspection thin film transistors 35 are respectively connected to one set of pixel wirings such as the n scanning lines 3, and further the inspection potential pad 31, the monitor pad 32, the resistance element 33, the inspection wiring 34, Ground pad GN
The inspection wiring portion including D is connected to the source / drain paths of these inspection thin film transistors 35 in order to detect the operating state according to the gate potential. When the array substrate 100 is inspected, a voltage such as a scanning signal is supplied to the thin film transistor 5 serving as a switching element via each scanning line 3. For example, a defect such as a disconnection, a short circuit, or a device destruction is caused by the scanning line 3
Alternatively, when it exists in the thin film transistor 5 which is a switching element connected to the scanning line 3, the potential of the scanning line 3 changes depending on the kind of the defect. For this reason,
The inspection thin film transistor 35 operates so as to sense the potential of the scanning line 3. Specifically, the conductivity or electric resistance of the inspection thin film transistor is controlled by the potential of the scanning line 3 and set to a value that reflects the type of defect. Therefore, a current is passed through the inspection thin film transistor 35 by using the inspection wiring portion, and these inspection thin film transistors 3 are
By measuring the voltage drop at 5, the defect information as described above can be obtained. Further, by collecting the defect information sequentially for one set of all the scan lines 3, it is possible to specify in which of the scan lines 3 the defect exists.

Further, the inspection wiring portion is electrically insulated from each scanning line 3 by the gate insulating film of the corresponding inspection thin film transistor 35. In this structure, since the gate and the source / drain path of one inspection thin film transistor 35 are electrically connected by a defect such as a defective gate insulating film, the scanning line 3 connected to the gate of this inspection thin film transistor 35 is used for another scan. The conventional problem of shorting to line 3 can be avoided. This structure can also be used to repair the scan line 3 connected to it by cutting off the gate of the defective transistor 35 with a laser beam.

Further, n inspection thin film transistors 35 are provided.
By connecting the source / drain paths in parallel by using the inspection wiring 34, it is possible to prevent the wiring structure of the array substrate 100 from being extremely complicated in order to enable reliable defect inspection. Further, since the switching element is composed of the thin film transistor 5, these can be formed simultaneously with the inspection thin film transistor 35 in the same process.
This means that no separate process is required to form the inspection thin film transistor 35.

As described above, according to the present invention, it is possible to reliably inspect defects existing in pixel wirings or switching elements without requiring a drastic change in circuit components or a complicated wiring structure. Since these defect inspections can be performed almost independently, it is easy to specify the location of the defect. Further, with respect to the defect of the inspection thin film transistor included in the inspection auxiliary circuit, it can be repaired to prevent the decrease in the yield of the array substrate.

Further, after the array substrate is manufactured or after the main circuit components of the array substrate are formed, a defect inspection can be performed by using the inspection auxiliary circuit. This defect inspection can be performed regardless of the manufacturing process of the counter substrate and the bonding process of integrating the array substrate and the counter substrate with the liquid crystal layer. Of course, it is not necessary to perform a defect inspection after the liquid crystal display device is completed. Therefore, it is not necessary to discard the defect-free counter substrate and the liquid crystal layer due to the defects generated in the array substrate, and it is possible to improve the yield of the entire liquid crystal display device. As described above, it is preferable to be able to detect electrical circuit defects early in the manufacturing process of the liquid crystal display device, in order to maintain the reliability of the liquid crystal display device as well as to reduce the manufacturing cost accompanying the improvement in yield.

The present invention is not limited to the above-described first to fifth embodiments, and can be variously modified without departing from the gist thereof. In the liquid crystal display device of each embodiment, the scanning line driver 8 and the signal line driver 9 are provided on one side of the display region SR on the array substrate. However, the present invention can also be applied to an array substrate having a structure in which the first and second scanning line drivers are provided on both sides of the display region SR in the scanning line direction and the odd scanning lines and the even scanning lines are independently driven. Further, the present invention can be applied to an array substrate having a structure in which first and second signal line drivers are provided on both sides of the display region SR in the signal line direction and the odd signal line and the even signal line are driven independently. In these cases, the above-mentioned inspection TFTs are also symmetrically arranged corresponding to the arrangement of the first and second scanning line drivers or the first and second signal line drivers.

Further, the position of the inspection TFT of each embodiment can be changed on the array substrate 100 in consideration of the ease of inspection or the positions of other components. For example, the inspection TFTs 35 and 55 shown in FIG. 3 are not limited to be arranged between the scanning line driver 8 and the display region SR and between the signal line driver 9 and the display region SR, respectively.
If the display area SR has an empty space, these can be arranged in this space. Also, scan line 3
If the signal line 4 and the signal line 4 are formed so as to extend further across the scanning line driver 8 and the signal line driver 9, the inspection transistors 35D and 55D are arranged outside the scanning line driver 8 and the signal line driver 9, respectively. The gate may be connected to the scan line 3 and the signal line 4.

In the above embodiments, the ground pad GND is used.
Is set to a reference potential of 0V, and the inspection TFTs 35, 35
D, 35E, 55, 55D, and 55E are connected to their respective source / drain paths. This reference potential is not limited to 0V, but monitor pads 32, 32D, 32E, 5
TF for inspection in relation to the potentials of 2, 52D, and 52E
It can be changed within a range in which T can be conducted. Therefore, the inspection voltage of the specific waveform is applied to the monitor pads 32, 32D, 32E, 52, 52D, and 5 during the defect inspection.
It may be applied between 2E and the ground pad GND.

Further, the resistance elements 33, 33D, 33E, 5
5, 55D, and 55E can also be configured by TFTs having an ON resistance, an OFF resistance, or the like as the electric resistance Rx. Further, these resistance elements may be provided outside the liquid crystal display device in order to reduce the number of pads.

Further, for example, the inspection TFTs 35, 35D, 35 having a gate insulation defect formed on the array substrate 100.
E, 55, 55D, or 55E, if a defect inspection finds that there is a gate insulation defect inspection TFT
The influence of this defect can be eliminated by electrically floating the source / drain path of 1) or by separating the gate of the inspection TFT from the scanning line 3 or the signal line 4 by a laser trimming device. When a liquid crystal display device is completed by using the array substrate 100 restored in this way, the liquid crystal display device becomes a product that performs a normal display operation.

The present invention can also be applied to the decoder type scanning line driver 8D shown in FIG. The scanning line driver 8D decodes a numerical signal supplied from the liquid crystal controller and changing in a binary order to obtain n.
The scanning lines 3 of the book are sequentially and selectively driven. In particular, since the numerical signal directly specifies the scan line to be driven for defect inspection, the scan line can be selected more easily than in the case of using a shift register that repeats the shift operation to specify the scan line.

The present invention can also be applied to the analog switch type signal line driver 9D shown in FIG. In this case, the inspection thin film transistor 55D is connected to the analog switch as shown in FIG.

[0075]

As described above, according to the present invention, it is possible to provide an array substrate of a liquid crystal display device which enables an inspection for accurately specifying a defective portion without significantly complicating the structure.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing a planar structure of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a diagram schematically showing a cross-sectional structure of the liquid crystal display device shown in FIG.

FIG. 3 is a diagram showing in detail a circuit formed on the array substrate shown in FIG.

FIG. 4 is a diagram showing a circuit formed on an array substrate of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a circuit formed on an array substrate of a liquid crystal display device according to a third embodiment of the present invention.

FIG. 6 is a diagram showing a circuit formed on an array substrate of a liquid crystal display device according to a fourth embodiment of the present invention.

FIG. 7 is a diagram showing a circuit formed on an array substrate of a liquid crystal display device according to a fifth embodiment of the present invention.

8 is a flow chart for explaining a defect inspection of the array substrate shown in FIG.

9 is a flowchart for explaining a defect inspection of the array substrate shown in FIG.

FIG. 10 is a diagram showing an example in which the present invention is applied to a scanning line driver of a decoder system.

FIG. 11 is a diagram showing an example in which the present invention is applied to an analog switch type signal line driver.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Pixel electrode 3 ... Scan line 4 ... Signal line 5 ... Switching element 30 ... Inspection auxiliary circuit 31 ... Inspection potential pad 32 ... Monitor pad 33 ... Resistor element 34 ... Inspection wiring part 35 ... Inspection thin film transistor GND ... Ground pad

Claims (18)

[Claims] 1. An insulating substrate, a plurality of pixel electrodes arranged in a matrix on the insulating substrate, and a set of first electrodes formed along a row of the plurality of pixel electrodes on the insulating substrate. One pixel wiring, a set of second pixel wirings formed along a column of a plurality of pixel electrodes on the insulating substrate, and an insulating substrate adjacent to intersections of the first and second pixel wirings. A plurality of switching elements formed on the switching element for supplying the video signal from the corresponding second pixel wiring to the corresponding pixel electrode in response to the scanning signal from the corresponding first pixel wiring; and at least one set of first and second switching elements. An inspection auxiliary circuit for sensing the potential of the pixel wiring is provided,
The inspection auxiliary circuit has a plurality of inspection thin film transistors whose gates are respectively connected to one set of pixel wirings, and an inspection connected to the source / drain paths of these inspection thin film transistors for detecting the operating state according to the gate potential. A first inspection unit including a wiring portion, and the inspection wiring portion is a source / source of the plurality of thin film transistors for inspection.
First drain paths are connected in parallel with each other
A second test pad, a third test pad to which a test voltage is applied with reference to the first test pad, and a second test pad
And a resistance element connected between the third inspection pads to divide the inspection voltage in cooperation with the electric resistances of the plurality of inspection thin film transistors, the array substrate of the liquid crystal display device. 2. The second inspection pad is connected to source / drain paths of the inspection thin film transistors through a common inspection wiring formed along the plurality of inspection thin film transistors. An array substrate of the liquid crystal display device according to item 1. 3. The array substrate includes a first driver for supplying a scanning signal to the first pixel wiring and a second driver for supplying a video signal.
The array substrate of the liquid crystal display device according to claim 1, further comprising a second driver that supplies the pixel wiring. 4. The array substrate of the liquid crystal display device according to claim 3, wherein gates of the inspection thin film transistors of the first inspection unit are connected to the one set of first pixel wirings, respectively. 5. The liquid crystal display according to claim 4, wherein the gates of the inspection thin film transistors of the first inspection unit are connected to the one set of first pixel wirings through a plurality of buffer circuits, respectively. Array board for the device. 6. The first driver is the first set of the first driver.
The inspection auxiliary circuit includes a plurality of buffer circuits each having an output terminal connected to the pixel wiring, and the inspection auxiliary circuit has a plurality of inspection thin film transistors each having a gate connected to an input terminal of each of the plurality of buffer circuits, and operates according to a gate potential. 5. The array of the liquid crystal display device according to claim 4, further comprising a second inspection section including an inspection wiring section connected to the source / drain paths of the inspection thin film transistors for detecting the state. substrate. 7. The gate of the inspection thin film transistor of the first inspection unit is connected to an end of each of the one set of first pixel wirings in an area outside the matrix array of pixel electrodes, and the inspection auxiliary circuit has a gate. A plurality of inspection thin film transistors respectively connected to the other end of the one set of first pixel wirings in an area outside the matrix array of the pixel electrodes, and these inspection thin film transistors for detecting an operating state according to a gate potential. 7. The array substrate of the liquid crystal display device according to claim 6, further comprising a third inspection section including an inspection wiring section connected to the source / drain path of the. 8. The gate of the inspection thin film transistor of the first inspection unit is connected to an end of the one set of first pixel wirings in an outer region of the matrix array of pixel electrodes, and the inspection auxiliary circuit has a gate. A plurality of inspection thin film transistors respectively connected to the other end of the one set of the first pixel wirings in an area outside the matrix array of the pixel electrodes, and these inspection thin film transistors for detecting an operation state according to a gate potential. 5. The array substrate of the liquid crystal display device according to claim 4, further comprising a second inspection section including an inspection wiring section connected to the source / drain path of the. 9. The array substrate of the liquid crystal display device according to claim 3, wherein gates of the inspection thin film transistors of the first inspection unit are connected to the one set of second pixel wirings, respectively. 10. The liquid crystal display according to claim 9, wherein a gate of the thin film transistor for inspection of the first inspection unit is connected to the one set of second pixel wirings via a plurality of buffer circuits, respectively. Array board for the device. 11. The second driver includes a plurality of buffer circuits each having an output end connected to the one set of second pixel wirings, and the inspection auxiliary circuit has a gate at each input end of the plurality of buffer circuits. The second inspection unit further includes a plurality of inspection thin film transistors connected to each other, and an inspection wiring unit connected to the source / drain paths of the inspection thin film transistors to detect an operating state according to the gate potential. 10. The method according to claim 9, wherein
An array substrate of the liquid crystal display device described in 1. 12. The gate of the inspection thin film transistor of the first inspection unit is connected to an end of the one set of second pixel wirings in an area outside the matrix array of pixel electrodes, and the inspection auxiliary circuit has a gate. A plurality of inspection thin film transistors respectively connected to the other end of the one set of second pixel wirings in an area outside the matrix array of pixel electrodes, and these inspection thin film transistors for detecting an operating state according to a gate potential. 3. A third inspection section further comprising an inspection wiring section connected to the source / drain paths of the above.
An array substrate of the liquid crystal display device according to item 1. 13. The gate of the inspection thin film transistor of the first inspection unit is connected to an end of the one set of second pixel wirings in an area outside the matrix array of pixel electrodes, and the inspection auxiliary circuit has a gate. A plurality of inspection thin film transistors respectively connected to the other end of the one set of second pixel wirings in an area outside the matrix array of pixel electrodes, and these inspection thin film transistors for detecting an operating state according to a gate potential. 10. A second inspection section further comprising an inspection wiring section connected to the source / drain path of the above.
An array substrate of the liquid crystal display device described in 1. 14. An insulating substrate, a plurality of pixel electrodes arranged in a matrix on the insulating substrate, and a set of first electrodes formed on the insulating substrate along a row of the plurality of pixel electrodes. One pixel wiring, a set of second pixel wirings formed along a column of a plurality of pixel electrodes on the insulating substrate, and an insulating substrate adjacent to intersections of the first and second pixel wirings. A plurality of switching elements formed on the switching element for supplying the video signal from the corresponding second pixel wiring to the corresponding pixel electrode in response to the scanning signal from the corresponding first pixel wiring; and at least one set of first and second switching elements. An inspection auxiliary circuit for sensing the potential of the pixel wiring, and the first and second pixel wirings of each set are connected so as to receive a scanning signal and a video signal via a plurality of buffer circuits, respectively. The inspection auxiliary circuit has a plurality of inspection thin film transistors whose gates are respectively connected to the input ends of the plurality of buffer circuits, and source / drain of these inspection thin film transistors for detecting the operating state according to the gate potential. An array substrate of a liquid crystal display device, comprising: a first inspection section including an inspection wiring section connected to a path. 15. An insulating substrate, a plurality of pixel electrodes arranged in a matrix on the insulating substrate, and a set of first pixel electrodes formed on the insulating substrate along a row of the plurality of pixel electrodes. One pixel wiring, a set of second pixel wirings formed along a column of a plurality of pixel electrodes on the insulating substrate, and an insulating substrate adjacent to intersections of the first and second pixel wirings. A plurality of switching elements which are formed on the switching element and which supply the video signal from the corresponding second pixel wiring to the corresponding pixel electrode in response to the scanning signal from the corresponding first pixel wiring; A second driver for supplying a video signal, and the first set of the first driver
An array substrate including a first driver that supplies a scanning signal to the pixel wiring, an inspection auxiliary circuit that senses the potentials of the first and second pixel wirings, an insulating substrate, and a counter formed on the insulating substrate. A counter substrate including electrodes and a liquid crystal layer held between the array substrate and the counter substrate, and the inspection auxiliary circuit has a plurality of inspection thin film transistors whose gates are connected to the one set of first pixel wirings, respectively. In addition, a first inspection unit including an inspection wiring unit connected to the source / drain paths of these inspection thin film transistors for detecting an operating state according to the gate potential, and a gate for the set of second pixel wirings. In order to detect a plurality of test thin film transistors connected to each other and the operating state according to the gate potential, the source / drain of these test thin film transistors is detected. And a second inspection unit composed of the inspection line section connected to in path, the first and second
Each inspection wiring portion of the inspection portion has first and second inspection pads in which source / drain paths of the plurality of inspection thin film transistors are connected in parallel with each other, and an inspection voltage is based on the first inspection pad. And a resistance element connected between the second and third test pads to divide the test voltage in cooperation with electric resistances of the plurality of test thin film transistors. Liquid crystal display device. 16. An insulating substrate, a plurality of pixel electrodes arranged in a matrix on the insulating substrate, and a set of first pixel electrodes formed on the insulating substrate along a row of the plurality of pixel electrodes. One pixel wiring, a set of second pixel wirings formed along a column of a plurality of pixel electrodes on the insulating substrate, and an insulating substrate adjacent to intersections of the first and second pixel wirings. A plurality of switching elements which are formed on the switching element and which supply the video signal from the corresponding second pixel wiring to the corresponding pixel electrode in response to the scanning signal from the corresponding first pixel wiring; A second driver for supplying a video signal, and the first set of the first driver
An array substrate including a first driver that supplies a scanning signal to the pixel wiring, an inspection auxiliary circuit that senses the potentials of the first and second pixel wirings, an insulating substrate, and a counter formed on the insulating substrate. A counter substrate including electrodes and a liquid crystal layer held between the array substrate and the counter substrate, and the inspection auxiliary circuit has a plurality of inspection thin film transistors whose gates are connected to the one set of first pixel wirings, respectively. In addition, a first inspection unit including an inspection wiring unit connected to the source / drain paths of these inspection thin film transistors for detecting an operating state according to the gate potential, and a gate for the set of second pixel wirings. In order to detect a plurality of test thin film transistors connected to each other and the operating state according to the gate potential, the source / drain of these test thin film transistors is detected. A second inspection section including an inspection wiring section connected to an in-path, wherein the first driver includes a plurality of buffer circuits each having an output terminal connected to the one set of first pixel wirings, The second driver includes a plurality of buffer circuits each having an output terminal connected to the one set of second pixel wirings, and the inspection auxiliary circuit has a gate connected to each input terminal of the plurality of buffer circuits of the first driver. A plurality of inspection thin film transistors, and a third inspection unit including an inspection wiring unit connected to the source / drain paths of the inspection thin film transistors for detecting the operating state according to the gate potential; A plurality of thin film transistors for inspection, which are respectively connected to input terminals of a plurality of buffer circuits of the second driver;
A liquid crystal display device further comprising: a fourth inspection section configured by an inspection wiring section connected to the source / drain paths of these inspection thin film transistors for detecting an operating state according to a gate potential. 17. A gate of the thin film transistor for inspection of the first inspection unit is connected to an end of the one set of first pixel wirings in an area outside the matrix array of pixel electrodes, and an inspection of the second inspection unit is performed. The gates of the thin film transistors are connected to the ends of the one set of second pixel wirings in the outer region of the pixel electrode matrix array, and the inspection auxiliary circuit has the gate in the outer region of the pixel electrode matrix array. A plurality of inspection thin film transistors respectively connected to the other end of the first pixel wiring of the set, and an inspection wiring portion connected to the source / drain paths of these inspection thin film transistors for detecting the operating state according to the gate potential. And a gate in a region outside the matrix array of the pixel electrodes. In addition, a plurality of inspection thin film transistors respectively connected to the other ends of the one set of the second pixel wirings, and connected to the source / drain paths of these inspection thin film transistors in order to detect the operating state according to the gate potential. The liquid crystal display device according to claim 16, further comprising: a sixth inspection unit configured with an inspection wiring unit. 18. A step of forming a plurality of pixel electrodes arranged in a matrix on an insulating substrate and forming a set of first pixel wirings on the insulating substrate along a row of the plurality of pixel electrodes. And a step of forming a set of second pixel wirings along the column of a plurality of pixel electrodes on the insulating substrate, and corresponding second pixel wirings in response to the scanning signals from the corresponding first pixel wirings, respectively. Forming a plurality of switching elements, each of which supplies a video signal from the wiring to the corresponding pixel electrode, on the insulating substrate adjacent to the intersection of the first and second pixel wirings; In order to detect a plurality of inspection thin film transistors connected to each and the operating state according to the gate potential, the source / drain paths of these inspection thin film transistors are detected. Forming an inspection auxiliary circuit that senses the potentials of at least one set of first and second pixel wirings, the inspection element including an inspection wiring section connected to the plurality of switching elements. The method for manufacturing an array substrate of a liquid crystal display device, comprising: a thin film transistor formed by the same process as the inspection thin film transistor.