JPH09148894A - Voltage control oscillator stable against fluctuation in power source voltage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an oscillator reducing the influence of the fluctuation in power source voltage. SOLUTION: This oscillator is composed of an oscillator 101 outputting the signal of the frequency according to the potential difference of a power source line 201 and a power source line 202 from a signal line 208, nMOSFET 103 in which a power source terminal 105 is connected with drain, a power source line 201 is connected with a source and a control signal line 204 is connected with a gate, and a level converter 102 in which the signal making the potential obtained in the power source line 201 a high level and the potential obtained in the power source line 207 a low level is converted into the signal making the potential obtained in the power source line 206 the high level and the potential obtained in the power source line 207 the low level in the signal line 208 and the signal is outputted to an output signal line 203. In this case, because the potential of the source of the n MOSFET 103 is determined by gate voltage and drain current and the potential does not depend on drain potential, the oscillation frequency of the oscillator 101 does not fluctuate even if the potential of the power source terminal 105 fluctuates.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage controlled oscillator, and more particularly to a voltage controlled oscillator in which fluctuations in oscillation frequency are small with fluctuations in power supply voltage.

[0002]

2. Description of the Related Art As a conventional voltage controlled oscillator, for example, a reference (Ian A. Young et al., "A PLL Clock Generator wi
th 5 to 110 MHz Lock Range for Microprocessors ", 1
992 IEEE International Solid State Circuits Confer
ence Digest of Technical Papers, pp. 50-51, 1992
11) shows a configuration example described in (Year).

Referring to FIG. 11, in the conventional voltage controlled oscillator, a delay element 912 having a differential amplifier configuration is connected in a plurality of stages, and a final stage output is fed back to a first stage input to form a ring shape. Connected ring oscillator, pseudo bias device 911, voltage-current converter 910
And consisting of

The delay element 912 has pMOS transistors MP102 whose sources are connected to each other to form a differential pair,
MP103, a pMOS transistor MP101 connected between the differential pair and the first power supply terminal 920 and functioning as a constant current source, and differential pair transistors MP102, MP.
A load resistance (voltage control resistor) 901 of voltage control type (variable in resistance value depending on voltage) connected between the drain of 103 and the second power supply terminal 921. Delay element 91
The low level of the second output (thus the output of the oscillator) is set to the potential level of the second power supply terminal 921, and the high level (Hi
When the current value of the constant current source MP101 is I and the resistance value of the voltage control resistor 901 is R, the gh) level is higher than the potential level of the second power supply terminal 921 by a voltage RI.

The delay time between the inputs and outputs of the delay element 912 is the difference between the potential level of the current control signal line 930 and the potential level of the first power supply terminal 920, and the potential level of the voltage control signal line 931 and the second level. Of the power supply terminal 921 and the potential difference of the power supply terminal 921. That is, it is determined by the gate-source potential (constant current value) of the pMOS transistor MP101 of the constant current source and the resistance value of the voltage control resistor 901 which is the load resistance.

The oscillation frequency of the signal obtained from the output terminal 922 by the voltage-current converter 910 is determined by the potential difference between the potential level of the control terminal 923 and the potential level given from the second power supply terminal 921.

In the pseudo bias device 911, the potential level applied to the amplitude control terminal 924 is set to the high level and the second
The potential level of the current control signal line 930 and the voltage control signal line 931 are set so that a signal for making the potential level applied to the power supply terminal 921 of the low level is obtained from the output terminal 922.
The potential level of is determined.

That is, like the delay element 912, the pseudo bias device 911 is provided with a pMOS transistor of a constant current source, a pMOS transistor differential pair, and a voltage control resistor 901 as a load resistance, and an input from an amplitude control terminal 924. To an inverting input terminal, and a connection point (node N1) between a transistor of the differential pair and the voltage control resistor 901 is connected to a non-inverting input terminal. The potential of the node N1 is controlled to be equal to the high-level reference potential input to the amplitude control terminal 924, and the output of the operational amplifier OP1 is used as the voltage control signal line 931 to control the voltage control resistor 901 of the delay element 912.
Output to With such a configuration, even when the constant current value of the delay element 912 changes (oscillation frequency changes), the signal amplitude output from the output terminal 922 of the oscillator is kept constant.

[0009]

In the conventional voltage controlled oscillator described above, the potential level of the signal applied to the control terminal 923 normally fluctuates in synchronization with the voltage level of the second power supply terminal 921. Even if the voltage level of the power supply terminal 921 changes, the influence of the signal obtained from the output terminal 922 on the oscillation frequency is small.

However, in the above conventional voltage controlled oscillator,
When the voltage level of the first power supply terminal 920 changes, the voltage-current converter 910 controls the potential level of the current control signal line 930 so that the input / output delay time of the delay element 912 does not change. When the frequency at which the voltage level of the power supply terminal 920 fluctuates becomes so high that the voltage / current converter 910 cannot follow it, the input / output delay time of the delay element 912 fluctuates, so that the oscillation frequency of the signal obtained from the output terminal 922 changes. It will fluctuate.

Here, the frequency that the voltage-current converter 910 cannot follow means the parasitic capacitance of the current control signal line 930 and the gate capacitance of the pMOS transistor whose gate terminal is connected to the current control signal line 930, and the voltage-current conversion. It is determined by the characteristics of the pMOS transistor that constitutes the device 910. For example, it is impossible to deal with a temporary voltage drop in the LSI chip caused by a current that flows or stops when some circuits move or stop.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a voltage controlled oscillator which solves the above-mentioned problems of the prior art and reduces the influence of fluctuations in the power supply voltage.

[0013]

In order to achieve the above-mentioned object, the present invention is inserted between a high potential side power source line and a low potential side power source line and responds to a voltage difference between the two power source lines. In a voltage controlled oscillator including an oscillator whose oscillation frequency is variable, at least one power source line of the high potential side power source line and the low potential side power source line and a power source line provided corresponding to the power source line and supplying power to the power source line. A voltage-controlled oscillator characterized in that a MOS transistor is inserted between a power supply terminal and a gate terminal of the MOS transistor, and a control signal is applied to control the oscillation frequency of the oscillator.

In the voltage controlled oscillator of the present invention, preferably, the MO is provided between the power supply line and the power supply terminal.
A feature is that a bipolar transistor is inserted instead of the S transistor.

Further, in the voltage controlled oscillator of the present invention, preferably, the amplitude of the output signal of the oscillator is set to the high potential side power source line and the low potential side power source line corresponding to the inserted transistor. And a means for shifting to at least one power supply level of the power supply levels of the two power supply terminals for supplying power to each of the two.

The present invention comprises a first power supply terminal, a second power supply terminal, and an output terminal, and oscillates according to the voltage difference obtained at the first power supply terminal and the second power supply terminal. An oscillator having a variable frequency, the second power supply terminal, a third power supply terminal, an input terminal, and an output terminal are provided, and the input terminal is connected to the output terminal of the oscillator. A level converter that converts the signal amplitude of the signal obtained from the signal amplitude corresponding to the voltage difference obtained at the second power supply terminal and the third power supply terminal and outputs the signal amplitude from the output terminal. A source and a drain of a MOS transistor are respectively connected between the power supply terminal of the MOS transistor and the third power supply terminal, and the oscillation frequency of the oscillator is controlled by the gate terminal of the MOS transistor. control To provide a vibrator.

The present invention also includes a first power supply terminal and a second power supply terminal.
An oscillator whose oscillation frequency changes according to a voltage difference obtained at the first power supply terminal and the second power supply terminal, a first power supply terminal, and an output terminal, 3 the power supply terminal, the input terminal, and the output terminal, the input terminal is connected to the output terminal of the oscillator, the signal amplitude of the signal obtained from the input terminal is the first power supply terminal and the A level converter that converts into a signal amplitude corresponding to a voltage difference obtained at a third power supply terminal and outputs from a output terminal, and a MOS transistor is provided between the second power supply terminal and the third power supply terminal. A voltage-controlled oscillator is characterized in that the source and the drain are connected to each other and the oscillation frequency of the oscillator is controlled by the gate terminal of the MOS transistor.

Further, the present invention comprises a first power supply terminal, a second power supply terminal, and an output terminal, and is responsive to a voltage difference obtained at the first power supply terminal and the second power supply terminal. An oscillator whose oscillation frequency changes, a third power supply terminal, a fourth
Power source terminal, an input terminal, and an output terminal, the input terminal is connected to the output terminal of the oscillator, and the signal amplitude of a signal obtained from the input terminal is the third power source terminal and the fourth power terminal. A level converter that converts to a signal amplitude corresponding to the voltage difference obtained at the power supply terminal of and outputs from the output terminal,
A source terminal and a drain terminal of the first MOS transistor are respectively connected between the first power supply terminal and the third power supply terminal, and the gate terminal of the first MOS transistor connects the oscillator The oscillation frequency is controlled, and the source terminal and the drain terminal of the second MOS transistor are connected between the second power supply terminal and the fourth power supply terminal, respectively, and the gate terminal of the second MOS transistor is connected. According to the present invention, there is provided a voltage controlled oscillator, wherein the oscillation frequency of the oscillator is controlled.

The present invention further comprises a first power supply terminal, a second power supply terminal, and an output terminal, which are responsive to the voltage difference obtained at the first power supply terminal and the second power supply terminal. An oscillator whose oscillation frequency changes, and the second power supply terminal,
A third power supply terminal, an input terminal, and an output terminal,
The input terminal is connected to the output terminal of the oscillator,
A level converter that converts a signal amplitude of a signal obtained from the input terminal into a signal amplitude corresponding to a voltage difference obtained at the second power supply terminal and the third power supply terminal and outputs the signal amplitude from an output terminal, An emitter terminal and a collector terminal of a bipolar transistor are respectively connected between the first power supply terminal and the third power supply terminal, and the oscillation frequency of the oscillator is controlled by the base terminal of the bipolar transistor. A voltage controlled oscillator is provided.

The present invention comprises a first power supply terminal, a second power supply terminal, and an output terminal, and oscillates according to the voltage difference obtained at the first power supply terminal and the second power supply terminal. An oscillator having a variable frequency, the first power supply terminal, a third power supply terminal, an input terminal, and an output terminal are provided, and the input terminal is connected to the output terminal of the oscillator. A level converter which converts the signal amplitude of the signal obtained from the signal amplitude corresponding to the voltage difference obtained at the first power supply terminal and the third power supply terminal and outputs the signal amplitude from the output terminal, An emitter terminal and a collector terminal of a bipolar transistor are respectively connected between the power supply terminal of the second bipolar transistor and the power supply terminal of the second bipolar transistor, and the oscillation frequency of the oscillator is controlled by the base terminal of the second bipolar transistor. To provide that voltage-controlled oscillator.

The present invention also provides a first power supply terminal and a second power supply terminal.
An oscillator whose oscillation frequency changes according to a voltage difference obtained at the first power supply terminal and the second power supply terminal; a third power supply terminal; Power source terminal, an input terminal, and an output terminal, the input terminal is connected to the output terminal of the oscillator, and the signal amplitude of a signal obtained from the input terminal is the third power source terminal and the third power source terminal. A level converter for converting into a signal amplitude corresponding to the voltage difference obtained at the power supply terminal 4 and outputting from the output terminal;
And an emitter terminal and a collector terminal of the first bipolar transistor are respectively connected between the first power supply terminal and the third power supply terminal, and a base terminal of the first bipolar transistor is used to connect the oscillator of the oscillator. The oscillation frequency is controlled, and the second power supply terminal and the fourth power supply terminal are connected.
The power supply terminal of the second bipolar transistor is connected to the emitter terminal and the collector terminal of the second bipolar transistor, and the base terminal of the second bipolar transistor controls the oscillation frequency of the oscillator. I will provide a.

In the present invention, the oscillator further comprises an input terminal in addition to the first power supply terminal, the second power supply terminal and the output terminal, and the oscillation frequency can be controlled by the voltage value of the input terminal. You may.

[0023]

The present invention takes advantage of the fact that the potential of the source terminal of a MOS transistor is determined by the voltage of the gate terminal and the drain current and does not depend on the potential of the drain terminal.
Provided is a voltage controlled oscillator that is resistant to fluctuations in power supply voltage (that is, is less susceptible to fluctuations in power supply voltage).

Specifically, for an oscillator in which the oscillation frequency changes due to the voltage difference between the first power supply terminal and the second power supply terminal, the source is connected to the first and / or second power supply terminals in which the voltage fluctuates. A MOS transistor having a terminal connected to the power supply terminal of the oscillator and a drain terminal connected to the varying power supply terminal is provided.

The potentials of the first power supply terminal and the second power supply terminal of the oscillator, that is, the source potential of the MOS transistor are determined by the potential of the gate terminal and the drain current of the connected MOS transistor.

Since the drain current is also determined by the potential of the gate terminal and the current consumption of the oscillator, the power supply of the oscillator is uniquely determined by the gate potential of the MOS transistor. Therefore, the oscillation frequency of the oscillator is determined by the gate potential.

As described above, even if the voltage of the drain terminal of the MOS transistor fluctuates, the voltage of the source terminal does not fluctuate, so that the oscillator according to the present invention is not affected by the fluctuation of the power supply voltage.

The voltage controlled oscillator according to the present invention can be realized in the same manner even if the MOS transistor is a bipolar transistor.

[0029]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is a diagram showing a configuration of a voltage controlled oscillator according to a first embodiment of the present invention.

Referring to FIG. 1, the voltage controlled oscillator according to the present embodiment has a first power supply line 201 and a second power supply terminal 1.
The second power supply line 202 connected to 06, the oscillator 101 that outputs a signal having an oscillation frequency corresponding to the potential difference obtained from the signal line 208, and the drain terminal is connected to the first power supply terminal 105. The potential obtained from the first power supply line 201 and the nMOS transistor 103 having the source terminal connected to the power supply line 201 and the gate terminal connected to the control signal line 204 is set to the high level, and the second power supply terminal 106 is connected.
A signal whose potential obtained by the second power supply line 202 connected to the low level is low is supplied from the signal line 208, and the signal level is obtained by the third power supply line 206 connected to the first power supply terminal 105. Output signal line 2 obtained by converting the potential to a high level and converting the potential obtained by the fourth power supply line 207 connected to the second power supply terminal 106 to a low level
And a level converter 102 for outputting to 03.

FIG. 2 shows an example of the configuration of the oscillator 101 according to the embodiment of the present invention.

Referring to FIG. 2, oscillator 101 is formed by connecting an odd number of stages of inverters (CMOS type inverters, 5 stages in the figure) in a ring shape. It should be noted that the configuration of the oscillator shown in FIG. 2 is merely for explanation and does not limit the present invention.

FIG. 3 shows an example of the configuration of the level converter 102 in the voltage controlled oscillator according to the embodiment of the present invention.

Referring to FIG. 3, the level converter 102 is
An nMOS and pMOS transistor MN31, which is connected in series between the first power supply line 201 and the fourth power supply line 207 and whose gate terminals are both connected to the signal line 208,
CMOS type inverter composed of MP32 and signal line 2
08 and the inverted output from the CMOS type inverter are respectively input to the gate terminal, and the source terminal is the fourth power supply line 20.
Two nMOS transistors MN commonly connected to 7
33, MN34, and the two nMOS transistors M
The drain signal terminals of N33 and MN34 are cross-connected to the gate terminal, and are composed of two pMOS transistors MP35 and MP36 inserted between the third power supply line 206 and the drain terminals of the two nMOS transistors, and the output signal line 203 is taken out from the connection point of the gate terminal of the pMOS transistor MP36 and the drain terminal of the nMOS transistor MN33, and the high level of the output signal line 203 is converted to the potential of the third power supply line 206.
It should be noted that the configuration of the level converter 102 shown in FIG. 3 is merely for explanation and does not limit the present invention.

Referring to FIG. 1, an nMOS transistor 1
Since the source terminal of 03 is connected to the first power supply line 201, the potential V _hin of the first power supply line 201 depends on the potential V _hc of the control signal line 204 and the current I flowing through the first power supply line 201. It is determined by the following equation (1).

[0037]

(Equation 1)

In the equation (1), K is the gain coefficient of the nMOS transistor 103, and V _t is the nMOS transistor 1
The threshold voltage of 03, α is a predetermined constant. In the equation (1), the drain current I _DS of the nMOS transistor is, for example, K / 2 to the power α of the difference (V _GS −V _t ) between the gate-source voltage V _GS and the threshold voltage V _t in the saturation region.
It is derived from the fact that it is approximately equal to the value multiplied by (V _GS = V _hc −V _{hin in} FIG. 1).

Therefore, even if the potential applied to the first power supply terminal 105 changes, the potential (V _hin ) of the first power supply line 201 does not change.

Since the oscillation frequency of the oscillator 101 changes depending on the potential difference between the first power supply line 201 and the second power supply line 202, the oscillation frequency can be controlled by the potential (V _hc ) of the control signal line 204.

The high level of the signal on the signal line 208 from the oscillator 101 is set to the level of the first power supply line 201,
Since the low level is set to the level of the second power supply line 202, the level converter 102 sets the high level to the level of the third power supply line 206 and the low level to the level of the fourth power supply line 2.
The signal is converted into a signal of level 07 (equal potential to the second power supply line 202) and output from the output signal line 203.

If the level conversion is not necessary (for example, if the output amplitude may be small), the level converter 102 may be omitted to realize a voltage controlled oscillator in which the influence of the power supply voltage is reduced. can do.

The method of reducing the fluctuation of the power supply voltage by using the nMOS transistor 103 according to the present embodiment is not limited to the voltage controlled oscillator, and the oscillator 101 is provided in another circuit. It can also be replaced by etc.

[Second Embodiment] FIG. 4 is a circuit diagram showing a configuration of a voltage controlled oscillator according to a second embodiment of the present invention.

With reference to FIG. 4, the voltage controlled oscillator of this embodiment corresponds to the potential difference between the voltages obtained from the second power supply line 202 and the first power supply line 201 connected to the first power supply terminal 105. An oscillator 101 that outputs a signal of an oscillation frequency from a signal line 208, a drain terminal is connected to the second power supply terminal 106, a source terminal is connected to the second power supply line 202, and a gate terminal is connected to the control signal line 205. PM
A signal that sets the potential obtained by the OS transistor 104 and the first power supply line 201 to a high level and sets the potential obtained by the second power supply line 202 to a low level is supplied from the signal line 208, and the signal level is The signal obtained by setting the potential obtained by the third power supply line 206 connected to the first power supply terminal 105 to the high level and the potential obtained by the fourth power supply line 207 connected to the second power supply terminal 106 at the low level Level converter 109 for converting into the output signal and outputting to the output signal line 203
And consisting of

The oscillator 101 according to the present embodiment has the configuration shown in FIG. 2 as in the first embodiment. That is, the oscillator 101 can be realized by a ring-shaped connection of inverters in odd stages. It should be noted that the configuration of the oscillator shown in FIG. 2 is for explanation only, and does not limit the present invention in any way.

FIG. 5 shows the configuration of the level converter 109 in this embodiment. Referring to FIG. 5, level converter 1
09 is connected in series between the second power supply line 202 and the third power supply line 206, and has both gate terminals of the signal line 2
NMOS and pMOS transistor M connected to 08
CMOS type inverter composed of N51 and MP52,
Two nMOS transistors MN53 and MN54 in which the signal line 208 is connected to the gate terminal, the inverted output of the CMOS inverter is connected to the gate terminal, and the source terminal is commonly connected to the fourth power supply line 207; The drain terminals of the transistors MN53 and MN54 are cross-connected to the gate terminals, and the third power supply line 206 and two nMs are connected.
2 inserted between the drain terminal of the OS transistor
The output signal line 203 is composed of two pMOS transistors MP55 and MP56.
Of the nMOS transistor MN53 and the drain terminal of the nMOS transistor MN53. The configuration of the level converter 109 shown in FIG. 5 is merely for the purpose of explanation and does not limit the present invention.

Referring to FIG. 4, nMOS transistor 1
Since the source terminal of 04 is connected to the second power supply line 202, the potential V _lin of the second power supply line 202 depends on the potential V _lc of the control signal line 205 and the current I flowing through the second power supply line 202. It is determined by the following equation (2).

[0049]

(Equation 2)

In the equation (2), K'is a gain coefficient of the pMOS transistor 104, V _t 'is a threshold voltage of the pMOS transistor 104, and α'is a constant.

Therefore, even if the potential applied to the second power supply terminal 106 changes, the potential of the second power supply line 202 does not change.

Since the oscillation frequency of the oscillator 101 changes depending on the potential difference between the first power supply line 201 and the second power supply line 202, the oscillation frequency can be controlled by the potential of the control signal line 205.

The signal on the signal line 208 has the first high level.
Since the low level is the level of the second power line 202, the level converter 109 causes the high level to be the level of the third power line 206 and the low level to be the fourth power line. The signal is converted into a signal of level 207 and output from the output signal line 203. If the level conversion is not necessary, the effect of the present invention can be obtained by deleting the level converter.

The method of reducing the fluctuation of the power supply voltage using the MOS transistor of this embodiment is not applicable only to the voltage controlled oscillator, and the oscillator 101 can be replaced with another circuit or the like.

[Third Embodiment] FIG. 6 is a diagram showing the structure of a voltage controlled oscillator according to a third embodiment of the present invention.

Referring to FIG. 6, the voltage-controlled oscillator of this embodiment outputs a signal having an oscillation frequency corresponding to the potential difference between the voltages obtained from the first power supply line 201 and the second power supply line 202 from the signal line 208. The drain terminal is connected to the output oscillator 101 and the first power supply terminal 105, and the first power supply line 20
1 has a source terminal connected to it, and a control signal line 204 has a gate terminal connected to it.
The drain terminal is connected to the power supply terminal 106 of the, the source terminal is connected to the second power supply line 202, and the control signal line 205 is connected.
PMOS transistor 104 whose gate terminal is connected to
Then, a signal in which the potential obtained by the first power supply line 201 is high level and the potential obtained by the second power supply line 202 is low level is supplied from the signal line 208, and the signal level is changed to the first power supply line. Third power line 20 connected to terminal 105
The potential obtained at 6 is set to the high level, and the second power supply terminal 1
And a level converter 110 for converting a potential obtained by the fourth power supply line 207 connected to 06 to a signal having a low level and outputting the signal to the output signal line 203.

The oscillator 101 according to the present embodiment may have a structure as shown in FIG. 2 as in the case of the first embodiment.

FIG. 7 shows an example of the configuration of the level converter 110 according to this embodiment. Referring to FIG. 7, level converter 110 includes first power supply line 201 and second power supply line 20.
2 and a CMOS type inverter which is connected in series and has gate terminals connected to the signal line 208 and which is composed of nMOS and pMOS transistors MN71 and MP72, and a CMOS inverter which connects the signal line 208 to the gate terminal. Two nMOs whose inverting output is connected to the gate terminal and whose source terminal is commonly connected to the fourth power supply line 207.
S transistors MN73 and MN74 and the two nM
The drain terminals of the OS transistors MN73 and MN74 are cross-connected to the gate terminals, and two pMOS transistors M are inserted between the third power supply line 206 and the drain terminals of the two nMOS transistors MN73 and MN74.
P75 and MP76, and the output signal line 203 is p
It is taken out from the connection point between the gate terminal of the MOS transistor MP76 and the drain terminal of the nMOS transistor MN73. It should be noted that the configuration of the level converter 102 shown in FIG. 7 is merely for explanation and does not limit the present invention.

Referring to FIG. 6, nMOS transistor 1
Since the source terminal of 03 is connected to the first power supply line 201, the potential V _hin of the first power supply line 201 depends on the potential V _hc of the control signal line 204 and the current I flowing through the first power supply line 201. It is determined by the following equation (3).

[0060]

(Equation 3)

[0061] formula (3), K is the gain factor of the nMOS transistor 103, V _t is the nMOS transistor 1
03 is a threshold voltage, and α is a constant.

Therefore, even if the potential applied to the power supply terminal 105 changes, the potential of the first power supply line 201 does not change.

Further, since the source terminal of the pMOS transistor 104 is connected to the second power supply line 202, the potential V _lin of the second power supply line 202 is _equal to the potential V _lc of the control signal line 205 and the second power supply. It is determined by the current I flowing through the line 202 as in the following equation (4).

[0064]

(Equation 4)

In the equation (4), K ′ is a gain coefficient of the pMOS transistor 104, V _t ′ is a threshold voltage of the pMOS transistor 104, and α ′ is a constant.

Therefore, even if the potential applied to the second power supply terminal 106 changes, the potential of the second power supply line 202 does not change.

Since the oscillation frequency of the oscillator 101 changes depending on the potential difference between the first power supply line 201 and the second power supply line 202, the oscillation frequency can be controlled by the potentials of the control signal lines 204 and 205.

The signal on the signal line 208 has the first high level.
Since the low level of the power supply line 201 is the level of the second power supply line 202, the level converter 110 causes the high level to be the level of the third power supply line 206 and the low level to be the fourth power supply line. The signal is converted into a signal of level 207 and output from the output signal line 203. If the level conversion is not necessary, the effect of the present invention can be obtained by deleting the level converter.

The method of reducing the fluctuation of the power supply voltage using the MOS transistor of this embodiment is not applicable only to the voltage controlled oscillator.
The oscillator 101 can be replaced with another circuit or the like.

[Fourth Embodiment] FIG. 8 is a circuit diagram showing a structure of a voltage controlled oscillator according to a fourth embodiment of the present invention. This embodiment is an nMOS transistor 10 in the voltage controlled oscillator according to the first embodiment shown in FIG.
This is equivalent to the configuration in which 3 is replaced by the npn bipolar transistor 107.

Referring to FIG. 8, the voltage controlled oscillator according to the present embodiment has a first power supply line 201 and a second power supply terminal 10.
An oscillator 101 that outputs a signal of an oscillation frequency corresponding to the potential difference of the voltage obtained from the second power supply line 202 connected to 6 from a signal line 208, and a collector terminal is connected to the first power supply terminal 105. The potential obtained at the first power supply line 201 and the npn bipolar transistor 107 having the emitter terminal connected to the power supply line 201 and the base terminal connected to the control signal line 204 is set to the high level, and the second power supply line 202 is provided. A signal whose potential to be set to a low level is supplied from the signal line 208, and the signal level thereof is set to a high level as a potential obtained by the third power supply line 206 connected to the first power supply terminal 105, and the second power supply terminal is set to a high level. A level converter 102 that converts a potential obtained by the fourth power supply line 207 connected to the signal 106 into a low level signal and outputs the signal to the output signal line 203. .

The oscillator 101 according to the present embodiment can be configured as shown in FIG. 2 like the one described in the first embodiment. FIG. 3 shows an example of the configuration of the level converter 102 in this embodiment. FIG.
Also, the configurations of the oscillator and the level converter shown in FIG. 3 and FIG. 3 are for the purpose of explanation only, and not for limiting the present invention.

Referring to FIG. 8, since the emitter terminal of npn bipolar transistor 107 is connected to first power supply line 201, the potential V of first power supply line 201 is V.
_hin is determined by the potential V _hc of the control signal line 204 as in the following equation (5).

V _hin = V _hc −V _be (5)

Here, V _be is the npn transistor 107
Is a constant indicating the base-emitter voltage of. Therefore, even if the potential applied to the first power supply terminal 105 changes, the potential of the first power supply line 201 does not change.

Since the oscillation frequency of the oscillator 101 changes depending on the potential difference between the first power supply line 201 and the second power supply line 202, the oscillation frequency can be controlled by the potential of the control signal line 204.

The signal on the signal line 208 has the first high level.
Since the low level is the level of the second power supply line 202, the level converter 102 causes the high level to be the level of the third power supply line 206 and the low level to be the fourth power supply line. The signal is converted into a signal of level 207 and output from the output signal line 203. If the level conversion is not necessary, the effect of the present invention described above can be obtained even if the level converter is deleted.

The method of reducing the fluctuation of the power supply voltage using the bipolar transistor of this embodiment is not applicable only to the voltage controlled oscillator, and the oscillator 101 can be replaced with another circuit or the like. Is.

[Fifth Embodiment] FIG. 9 is a diagram showing a structure of a voltage controlled oscillator according to a fifth embodiment of the present invention. In this embodiment, the pMOS transistor 1 in the voltage controlled oscillator according to the second embodiment shown in FIG.
It is equivalent to a configuration in which 04 is replaced with a pnp bipolar transistor 108.

Referring to FIG. 9, the voltage controlled oscillator according to the present embodiment has a second power supply line 202 and a first power supply terminal 10.
The oscillator 101 that outputs a signal having an oscillation frequency corresponding to the potential difference of the voltage obtained from the first power supply line 201 connected to the signal line 5 from the signal line 208, and the collector terminal to the second power supply terminal 106 are connected to the second power supply terminal 106. The pnp bipolar transistor 108 whose emitter terminal is connected to the power supply line 202 and whose base terminal is connected to the control signal line 205, and the potential obtained by the first power supply line 201 are set to a high level and are obtained by the second power supply line 202. A signal whose potential to be set to a low level is supplied from the signal line 208, and the signal level thereof is set to a high level as a potential obtained by the third power supply line 206 connected to the first power supply terminal 105, and the second power supply terminal is set to a high level. A level converter 109 for converting a potential obtained by the fourth power supply line 207 connected to the control line 106 into a low level signal and outputting the signal to the output signal line 203. .

The configuration of the oscillator 101 in the present embodiment can be configured as shown in FIG. 2 as in the case of the configuration described in the first embodiment. 5 shows an example of the configuration of the level converter 109 according to this embodiment. The configurations of the oscillator and the level converter shown in FIG. 2 and FIG. 5, respectively, are for the purpose of explanation only, and are not for limiting the present invention.

Referring to FIG. 9, since the emitter terminal of pnp bipolar transistor 108 is connected to second power supply line 202, potential V of second power supply line 202 is V.
_{The lin} is determined by the potential V _lc of the control signal line 205 as in the following equation (6).

V _lin = V _lc −V _be ′ (6)

Here, V _be is the pnp transistor 10
8 constant (base-emitter voltage). Therefore, even if the potential applied to the second power supply terminal 106 changes, the potential of the second power supply line 202 does not change.

Since the oscillation frequency of the oscillator 101 changes depending on the potential difference between the first power supply line 201 and the second power supply line 202, the oscillation frequency can be controlled by the potential of the control signal line 205.

The signal on the signal line 208 has the first high level.
The low level is the level of the second power supply line 202, and the level converter 109 causes the high level to be the level of the third power supply line 206 and the low level is the fourth power supply line. The signal is converted into a signal of level 207 and output from the output signal line 203. If the level conversion is not necessary, the above-described effects of the present invention can be obtained even if the level converter is deleted.

The method of reducing the fluctuation of the power supply voltage using the bipolar transistor of this embodiment is not applicable only to the voltage controlled oscillator, and the oscillator 101 can be replaced with another circuit or the like.

[Sixth Embodiment] FIG. 10 is a diagram showing a structure of a voltage controlled oscillator according to a sixth embodiment of the present invention.
This embodiment is equivalent to the configuration in which the nMOS transistor 103 and the pMOS transistor 104 in the voltage controlled oscillator according to the third embodiment shown in FIG. 6 are replaced with the npn bipolar transistor 107 and the pnp bipolar transistor 108.

Referring to FIG. 10, the voltage-controlled oscillator of the present embodiment outputs a signal having an oscillation frequency corresponding to a potential difference between voltages obtained from first power supply line 201 and second power supply line 202 from signal line 208. The collector terminal is connected to the oscillator 101 for outputting and the first power supply terminal 105, and the first power supply line 2
Npn bipolar transistor 1 whose emitter terminal is connected to 01 and whose base terminal is connected to the control signal line 204
07, a pnp bipolar transistor 108 having a collector terminal connected to the second power supply terminal 106, an emitter terminal connected to the second power supply line 202, and a base terminal connected to the control signal line 205; and a first power supply. A signal whose potential obtained by the line 201 is high level and whose potential obtained by the second power supply line 202 is low level is supplied from the signal line 208, and the signal level thereof is connected to the first power supply terminal 105. The fourth power supply line 2 connected to the second power supply terminal 106 is set to a high level potential obtained by the power supply line 206
And a level converter 110 for converting the electric potential obtained at 07 into a low level signal and outputting it to the output signal line 203.

The configuration of the oscillator 101 in this embodiment may be the one shown in FIG. 2 as in the case of the first embodiment. 7 shows an example of the configuration of the level converter 110 according to this embodiment. The configurations shown in FIGS. 2 and 7 are not intended to limit the invention.

Referring to FIG. 10, since the emitter terminal of npn bipolar transistor 107 is connected to first power supply line 201, the potential V _hin of first power supply line 201 is V _hin.
Is determined by the potential V _hc of the control signal line 204 as in the following equation (7).

V _hin = V _hc −V _be (7)

Here, V _be is a constant of the npn bipolar transistor 107. Therefore, even if the potential applied to the first power supply terminal 105 fluctuates, the first power supply line 2
The potential of 01 does not change.

Also, the pnp bipolar transistor 10
Since the emitter terminal of 8 is connected to the second power supply line 202, the potential V _lin of the second power supply line 202 is determined by the potential V _lc of the control signal line 205 as in the following equation (8). .

V _lin = V _lc −V _be ′ (8)

Here, V _be is the pnp transistor 10
It is a constant of 8. Therefore, even if the potential applied to the second power supply terminal 106 changes, the potential of the second power supply line 202 does not change.

Since the oscillation frequency of the oscillator 101 changes depending on the potential difference between the first power supply line 201 and the second power supply line 202, the oscillation frequency can be controlled by the potentials of the control signal lines 204 and 205.

The signal on the signal line 208 has the first high level.
Since the low level is the level of the second power supply line 202, the level converter 110 causes the high level to be the level of the third power supply line 206 and the low level to be the fourth power supply line. The signal is converted into a signal of level 207 and output from the output signal line 203. If the level conversion is not necessary, the effect of the present invention can be obtained by deleting the level converter.

The method of reducing the fluctuation of the power supply voltage using the bipolar transistor according to the present embodiment is not applicable only to the voltage controlled oscillator, and the oscillator 101 is replaced with another circuit or the like. It is also possible.

[Seventh Embodiment] FIG. 12 shows another configuration example of an oscillator 101 as another embodiment of the present invention. FIG.
2, this oscillator is configured so that the control signal line 209 and the control signal line 210 can control the drive currents of the odd-numbered CMOS inverters in which the output of the output stage is fed back to the input of the input stage. There is.

In addition to the first power supply terminal, the second power supply terminal and the output terminal, this oscillator has an input terminal (control signal line 209,
The input terminal for 210) is provided, and the oscillation frequency can be changed by the voltage value of this input terminal.

This oscillator has an odd number of CMOS inverters (five in this example), as in the oscillator shown in FIG.
Although they are connected in a ring shape, a pMOS transistor MPi-2 is formed between the pMOS transistor MPi-1 and the power supply line 201 which form the CMOS inverter of each stage.
(I = 1, ... 5) is provided, and the control signal line 20 is provided at its gate.
9 are connected. Similarly, the nMOS transistor MNi-1 and the power supply line 2 which form the CMOS inverter of each stage
02 and nMOS transistor MNi-2 (i =
1, ... 5) are provided, and the control signal line 201 is connected to the gate thereof.

Now, let us consider a case where the oscillator shown in FIG. 12 is applied to the voltage controlled oscillator of the first embodiment shown in FIG.

This voltage controlled oscillator has a control signal line 204
The oscillation frequency can be controlled by the control signal line 209 and the control signal line 210.

The respective voltage levels of the control signal line 209 and the control signal line 210 are CMO which constitutes the oscillator 101.
The rising time and the falling time of the output signal of the S inverter are controlled respectively. Therefore, in normal use,
In order to equalize the rising time and the falling time, the voltage levels V _f and V _r of the control signal line 209 and the control signal line 210 have a certain correlation, for example,
It is determined by the following equation (9).

V _r = f (V _f ) ... (9)

Here, the function f is determined by the characteristics of the pMOS transistor and the nMOS transistor connected to the control signal line 209 and the control signal line 210, respectively.

That is, in a usual application, this voltage controlled oscillator can control the oscillation frequency by the two voltage levels of the control signal line 204 and the control signal line 209.

The above equation (9) will be described in detail below.

Now, pMO connected to the control signal line 209
Since the relationship between the gate voltage (voltage of 209) V _{f of the} S transistors (MP1-2, MP2-2, etc.) and the drain current _If is the gate-source voltage V _GS = Vdd−V _f , It is expressed by equation (10).

[0111]

(Equation 5)

Here, V _t is the threshold voltage of the PMOS transistor, α and K are constants determined by the transistor, and V dd is the potential of the power supply line 201. Similarly, an nMOS transistor (MN1 connected to the control signal line 210)
-2, MN2-2, etc.) gate voltage (voltage of 210)
The relationship between V _r and drain current I _r is expressed by the following equation (11).

[0113]

(Equation 6)

Here, V _t 'is a threshold voltage of the nMOS transistor, and α'and K'are constants determined by the transistor.

In order for the rise time and the fall time of the signal obtained from the signal line 208 to be the same, I _f = I _r must be satisfied. Therefore, the following equation (1)
2) is established.

[0116]

(Equation 7)

Here, K = K ', α = α', V _t = V _t '
Assuming that, V _r = Vdd−V _f (13)

That is, in this case, the function f (x) = Vdd-x in the above equation (9).

In general, variations in device characteristics due to variations in the threshold value and gate length of transistors constituting a voltage controlled oscillator, variations in characteristic values such as resistance values and capacitance values of wiring, temperature, power supply voltage, etc. The variation in the operating environment causes the gain of the voltage controlled oscillator, that is, the rate of change of the oscillation frequency with respect to the voltage level of the control signal line.

In this voltage controlled oscillator, the control signal line 20
4 and the control signal line 209, the oscillation frequency can be controlled, so that one control signal line can be used to compensate for variations in the above-mentioned devices.

Further, instead of the oscillator shown in FIG. 12, a circuit configuration shown in FIG. 13 may be used. This is C
The output of each stage of the MOS ring oscillator, connect one end of an nMOS transistor (MN ₁ ~MN _n), the capacity and the other end of the nMOS transistor _{(MN 1 ~MN n) (C} 1 ~C n)
And the control signal line 210 is connected to the gate of the nMOS transistor. The impedance of the nMOS transistor is controlled by the voltage of the control signal line 210.

[0122]

As described above, the voltage controlled oscillator of the present invention utilizes the fact that the potential of the source terminal of a MOS transistor is determined by the voltage of the gate terminal and the drain current, and does not depend on the potential of the drain terminal. The present invention provides a voltage controlled oscillator having excellent resistance to fluctuations in power supply voltage.

In the present invention, the first power supply terminal and the second power supply terminal
For an oscillator whose oscillation frequency changes depending on the voltage difference of the power supply terminal of the power supply, the first and / or second power supply terminal whose voltage fluctuates has a MOS transistor whose source terminal is the power supply terminal of the oscillator and whose drain terminal is the power supply whose fluctuation The potentials of the first power supply terminal and the second power supply terminal of the oscillator, that is, the source potentials of the MOS transistors are determined by the potentials of the gate terminals and the drain currents of the connected MOS transistors. Since the current is also determined by the potential of the gate terminal and the current consumption of the oscillator, the power supply of the oscillator is uniquely determined by the gate potential of the MOS transistor, and the oscillation frequency of the oscillator is determined by the gate potential of the MOS transistor. ,
Even if the voltage of the drain terminal of the MOS transistor fluctuates, the voltage of the source terminal does not fluctuate, so the oscillator of the present invention is not affected by the fluctuation of the power supply voltage.

In the voltage controlled oscillator of the present invention, the same effect can be obtained by using a bipolar transistor instead of the MOS transistor.

Further, in the present invention, the same effect as above can be obtained even if the input terminal is provided as the oscillator and the oscillation circuit or the like is controlled with respect to the voltage value thereof.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a configuration of a voltage controlled oscillator according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a configuration of an oscillator according to an embodiment of the present invention.

FIG. 3 is a diagram showing an example of a configuration of a level converter according to an embodiment of the present invention.

FIG. 4 is a diagram for explaining a configuration of a voltage controlled oscillator according to a second embodiment of the present invention.

FIG. 5 is a diagram showing an example of a configuration of a level converter according to a second embodiment of the present invention.

FIG. 6 is a diagram for explaining a configuration of a voltage controlled oscillator according to a third embodiment of the present invention.

FIG. 7 is a diagram showing an example of a configuration of a level converter according to a third embodiment of the present invention.

FIG. 8 is a diagram for explaining a configuration of a voltage controlled oscillator according to a fourth embodiment of the present invention.

FIG. 9 is a diagram for explaining a configuration of a voltage controlled oscillator according to a fifth embodiment of the present invention.

FIG. 10 is a diagram for explaining the configuration of a voltage controlled oscillator according to a sixth embodiment of the present invention.

FIG. 11 is a diagram showing a configuration of a conventional voltage controlled oscillator.

FIG. 12 is a diagram for explaining the configuration of a voltage controlled oscillator according to a seventh embodiment of the present invention.

FIG. 13 is a diagram for explaining another example of the voltage controlled oscillator according to the seventh embodiment of the present invention.

[Explanation of symbols]

 101 oscillator 102, 109, 110 level converter 103 nMOS transistor 104 pMOS transistor 105, 106 power supply terminal 107 npn bipolar transistor 108 pnp bipolar transistor 201, 202, 206, 207 power supply line 203 output signal line 204, 205 control signal line 208 signal line

Claims (10)

[Claims] 1. A voltage-controlled oscillator comprising an oscillator inserted between a high-potential-side power line and a low-potential-side power line and having an oscillation frequency variable according to a voltage difference between the two power lines. A MOS transistor is inserted between at least one power source line of the high potential side power source line and the low potential side power source line, and a power source terminal provided corresponding to the power source line and supplying power to the power source line. A voltage-controlled oscillator characterized in that a control signal is applied to a gate terminal of a transistor to control an oscillation frequency of the oscillator. 2. The voltage controlled oscillator according to claim 1, wherein a bipolar transistor is inserted between the power supply line and the power supply terminal instead of the MOS transistor. 3. The amplitude of the output signal of the oscillator is set to the power supply level of two power supply terminals for supplying power to the high potential side power supply line and the low potential side power supply line, respectively, corresponding to the inserted transistor. The voltage controlled oscillator according to claim 1, further comprising means for shifting to at least one of the power supply levels. 4. A first power supply terminal, a second power supply terminal, and an output terminal, wherein an oscillation frequency is set in accordance with a voltage difference obtained at the first power supply terminal and the second power supply terminal. A variable oscillator, the second power supply terminal, a third power supply terminal, an input terminal, and an output terminal, wherein the input terminal is connected to the output terminal of the oscillator and is obtained from the input terminal. A level converter that converts the signal amplitude of the generated signal into a signal amplitude corresponding to a voltage difference obtained at the second power supply terminal and the third power supply terminal and outputs the signal amplitude from an output terminal, the first power supply MO between the terminal and the third power supply terminal
Connect the source and drain of the S transistor,
A voltage-controlled oscillator, wherein an oscillation frequency of the oscillator is controlled by a gate terminal of the MOS transistor. 5. A first power supply terminal, a second power supply terminal, and an output terminal, wherein an oscillation frequency is set in accordance with a voltage difference obtained at the first power supply terminal and the second power supply terminal. An oscillator that changes, a first power supply terminal, a third power supply terminal, an input terminal, and an output terminal. The input terminal is connected to the output terminal of the oscillator, and the output terminal is obtained from the input terminal. A level converter that converts the signal amplitude of the generated signal into a signal amplitude corresponding to a voltage difference obtained at the first power supply terminal and the third power supply terminal and outputs the signal amplitude from an output terminal, the second power supply MO between the terminal and the third power supply terminal
Connect the source and drain of the S transistor,
A voltage-controlled oscillator, wherein an oscillation frequency of the oscillator is controlled by a gate terminal of the MOS transistor. 6. A first power supply terminal, a second power supply terminal, and an output terminal, wherein an oscillation frequency is set in accordance with a voltage difference obtained at the first power supply terminal and the second power supply terminal. A variable oscillator, a third power supply terminal, a fourth power supply terminal, an input terminal, and an output terminal are provided, and the input terminal is connected to the output terminal of the oscillator and is obtained from the input terminal. A level converter that converts a signal amplitude of a signal into a signal amplitude corresponding to a voltage difference obtained at the third power supply terminal and the fourth power supply terminal and outputs the signal amplitude from an output terminal, the first power supply terminal Between the first power supply terminal and the third power supply terminal
The source terminal and the drain terminal of the MOS transistor are connected to each other, the oscillation frequency of the oscillator is controlled by the gate terminal of the first MOS transistor, and the second power supply terminal and the fourth power supply terminal are connected. Second between
The voltage controlled oscillator, wherein the source terminal and the drain terminal of the MOS transistor are connected to each other, and the oscillation frequency of the oscillator is controlled by the gate terminal of the second MOS transistor. 7. A first power supply terminal, a second power supply terminal, and an output terminal, wherein an oscillation frequency is set in accordance with a voltage difference obtained at the first power supply terminal and the second power supply terminal. A variable oscillator, the second power supply terminal, a third power supply terminal, an input terminal, and an output terminal, wherein the input terminal is connected to the output terminal of the oscillator and is obtained from the input terminal. A level converter that converts the signal amplitude of the generated signal into a signal amplitude corresponding to a voltage difference obtained at the second power supply terminal and the third power supply terminal and outputs the signal amplitude from an output terminal, the first power supply An emitter terminal and a collector terminal of a bipolar transistor are respectively connected between a terminal and the third power supply terminal, and the oscillation frequency of the oscillator is controlled by the base terminal of the bipolar transistor. Vessel. 8. A first power supply terminal, a second power supply terminal, and an output terminal, wherein an oscillation frequency is set in accordance with a voltage difference obtained at the first power supply terminal and the second power supply terminal. A variable oscillator, the first power supply terminal, a third power supply terminal, an input terminal, and an output terminal are provided, and the input terminal is connected to the output terminal of the oscillator and is obtained from the input terminal. A level converter that converts the signal amplitude of the generated signal into a signal amplitude corresponding to a voltage difference obtained at the first power supply terminal and the third power supply terminal and outputs the signal amplitude from an output terminal, the second power supply A voltage characterized in that an emitter terminal and a collector terminal of a bipolar transistor are respectively connected between a terminal and the third power supply terminal, and the oscillation frequency of the oscillator is controlled by the base terminal of the second bipolar transistor. Controlled oscillator. 9. A first power supply terminal, a second power supply terminal, and an output terminal, wherein an oscillation frequency is set in accordance with a voltage difference obtained at the first power supply terminal and the second power supply terminal. A variable oscillator, a third power supply terminal, a fourth power supply terminal, an input terminal, and an output terminal are provided, and the input terminal is connected to the output terminal of the oscillator and is obtained from the input terminal. A level converter that converts a signal amplitude of a signal into a signal amplitude corresponding to a voltage difference obtained at the third power supply terminal and the fourth power supply terminal and outputs the signal amplitude from an output terminal, the first power supply terminal Between the first power supply terminal and the third power supply terminal
The emitter terminal and the collector terminal of the bipolar transistor are connected to each other, and the oscillation frequency of the oscillator is controlled by the base terminal of the first bipolar transistor, and the second power supply terminal and the fourth power supply terminal are connected. Second between
The voltage-controlled oscillator, wherein the bipolar transistor has an emitter terminal and a collector terminal connected to each other, and the oscillation frequency of the oscillator is controlled by the base terminal of the second bipolar transistor. 10. The oscillator further comprises an input terminal in addition to the first power supply terminal, the second power supply terminal and the output terminal, and the oscillation frequency can be controlled by the voltage value of the input terminal. The voltage controlled oscillator according to claim 1, 2, 3, or 4.