JPH09148304A - Dry etching process - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain a high dry etching efficiency of a polishing stop layer and trench in a trench etching process of shallow trench isolation which is intended to flatten an insulating film based on chemical-mechanical polishing(CMP). SOLUTION: A polishing stop layer 4 is made up of a polysilicon film 3 as its upper film and a silicon nitride (Si-N) film 2 as its lower film, the latter film is etched usually with use of a fluorine etchant. When a chlorine or bromine etchant, however, is generated in such a high-concentration plasma system that produces an ion current density as high as 5mA/cm<2> or, more the SiN can be etched, whereby a series of etching operations starting with the etching of the polishing stop layer 4 and ending in the formation of trenches 8 in a silicon substrate 1 can be continuously carried out within an identical chamber, thus leading to an improved throughput in fabrication of a semiconductor device and also to low costs thereof.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dry etching method applied to the field of fine processing such as semiconductor device manufacturing, and particularly in shallow trench isolation which is premised on filling an insulating film by a chemical mechanical polishing (CMP) method. , A method for efficiently performing etching for forming a polishing stopper layer and a trench.

[0002]

2. Description of the Related Art An element isolation technique for forming an element isolation region for electrically isolating a large number of element formation regions from each other on a silicon (Si) substrate is one of the process techniques that are the basis of semiconductor device manufacturing. . For example, in a large-capacity memory device, the width of the element isolation region (that is, the element isolation width) is a factor that substantially determines the size of the memory cell and thus the degree of integration. In addition, the element isolation region has a great influence on the circuit characteristics such as electric field concentration according to its shape, or junction leakage current caused by substrate residual stress generated at the time of its formation. Therefore, the element isolation technique needs to be studied from all aspects such as size, shape, and circuit characteristics.

A conventional element isolation method is LOCO.
The S (LOCal Oxidation of Silicon) method has been widely used, but in recent years, the shallow trench isolation has been attracting attention as an alternative. This is a method in which a trench is formed in a silicon substrate, the trench is filled with an insulating film (typically a SiOx film), and the surface of the substrate is flattened. According to this method, unlike the LOCOS method, bird's beaks do not occur in the element isolation region, which is advantageous for higher integration in the horizontal direction of the substrate, and the thickness of the element isolation region can be arbitrarily set by the depth of the trench. Therefore, it is easy to secure the field inversion voltage, and the substantial distance between the diffusion layers can be secured, so that the punch-through resistance is improved. Further, if the impurities are selectively implanted into the side wall surface and the bottom surface of the trench by using the oblique rotation ion implantation technique, the subthreshold characteristic can be improved or the junction leakage and the junction capacitance can be reduced.

Although the shallow trench isolation has many merits as described above, it has not been put to practical use since there are many problems to be solved such as the complexity of the process. However, recently, the filling of a flat groove with an insulating film, which is one of the problems, is one of chemical mechanical polishing (CM
P) method is expected to be resolved. CMP
In this method, the surface plate on which the polishing cloth is attached is brought into contact with the substrate held by the polishing head, and both the surface plate and the polishing head are rotated while supplying the slurry containing the abrasive to the contact interface between the two. This is a technique for flattening the surface of the substrate.

In the CMP method, the point at which polishing is stopped and how to determine the end point of polishing are decisive factors for the degree of flatness to be achieved. A technique using a polishing stopper layer 4 as shown in FIG. 5 is known as a method for easily performing the polishing stop and the end point determination. This figure shows a state in which a trench 8 is formed in a silicon substrate 1 (Si) and the substrate surface other than the trench 8 is covered with a polishing stopper layer 4. The polishing stopper layer 4 is formed of the silicon nitride film 2
(SiN) and the polysilicon film 3 (polySi) are laminated in this order.

FIG. 6 shows a state in which the trench 8 is filled with a silicon oxide film 9 (SiOx). Since the silicon oxide film 9 needs to be uniformly buried deep in a narrow trench, in recent years, ECR has been performed.
By CVD using high-density plasma such as (electron cyclotron resonance) plasma and ICP (inductive coupling) plasma, a film is formed while competitively advancing the deposition process and the sputter etching process. Silicon oxide film 9 at this time
In the above, the portion covering the edge of the trench 8 grows while being scraped off, so that a protrusion as shown in the figure finally occurs in the flat portion other than the trench.

When CMP is performed to flatten the silicon oxide film 9 including removal of the protrusions, the polishing end point is approached when the polysilicon film 3 is exposed as shown in FIG. It can be judged from the color change of the substrate surface. This is the silicon oxide film 9 or the silicon nitride film 2.
Is transparent, whereas the polysilicon film 3 has a brown color. When the polishing is further continued, as shown in FIG. 8, the silicon nitride film 2 having a lower polishing rate than the polysilicon film 3 is exposed, so that the CMP can be finished at this point with good controllability.

[0008]

By the way, in order to carry out CMP using the polishing stopper layer 4 as described above, as is clear from FIG. , Polysilicon / silicon nitride / (single crystal) silicon, which have different etching characteristics, must be etched in a common pattern.

Conventionally, as shown in FIG. 1, first, a resist pattern 5 (PR) having a predetermined opening 6 is formed on the polishing stopper layer 4, and thereafter, the above three types of materials are used for a plurality of plasmas. Dry etching is sequentially performed while transferring the substrate between the chambers of the apparatus. That is, first, the substrate is carried into an etching apparatus for processing a gate electrode, the polysilicon film 3 is dry-etched using a chlorine-based gas as shown in FIG. 2, and then the substrate is changed to an etching apparatus for processing an insulating film. After carrying in, the silicon nitride film 2 is dry-etched using a fluorocarbon-based gas as shown in FIG.
Further, the substrate is returned to the etching device for processing the gate electrode again, and the silicon substrate 1 is dry-etched using a chlorine-based gas as shown in FIG.

However, in such a method of changing the etching apparatus for each material, the throughput and the particle level are deteriorated, a plurality of etching apparatuses are required, and the area occupied by the apparatus in the clean room increases. There is a great risk of cost efficiency being reduced. If a multi-chamber device in which a plurality of chambers are connected to each other by a vacuum transfer path is used, the problem of particles can be solved to some extent, but the size of the entire device is still inevitable. It is therefore an object of the present invention to solve such a problem and to provide a method for efficiently performing etching for forming a polishing stopper layer and a trench in shallow trench isolation.

[0011]

The present invention is based on CMP.
Shallow trench eye based on embedded insulating film
When performing trench etching for solation,
Silicon such as polysilicon film and single crystal silicon substrate
Dry etching between the system material film (or substrate) and these
And silicon nitride films with different
Or bromine-based species as a common etchant
By trying to achieve the above objectives
It is. In other words, to make the etchants common
Of the etching equipment and the etching chamber
Achieve common processes to improve process efficiency. In the present invention
The etching device used should be at least 5 mA / c
m ^Two The so-called high-density
Plasma etching equipment is particularly suitable. Also,
The etching gas used for etching is chlorine-based gas or
Is based on at least one of brominated gases
However, there is an etch between the polysilicon film and the silicon substrate.
O only when ching_Two It is good to contain gas.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION In the present invention, a silicon nitride film, which has been generally etched by using a fluorine-based etchant, is also etched by using a chlorine-based etchant or a bromine-based etchant. in this way,
When performing dry etching using an etchant that is not necessarily considered optimal from the viewpoint of interatomic bond energy with silicon atoms, a so-called high-density plasma device that can obtain high ion current density is used. Is advantageous.

The high-density plasma device is an ECR plasma etching device that uses electron cyclotron resonance (ECR) discharge by microwave input, an inductively coupled plasma etching device that uses inductively coupled discharge by high frequency input, and also high frequency input. A typical example is a helicon wave plasma etching apparatus that utilizes the Landau damping process of a helicon wave propagating in a magnetic field. All of these devices use ions generated with a high probability under a low gas pressure of several mTorr (on the order of 10 ^-1 Pa) and having a long mean free path, so that the ion bombardment on the surface to be etched is relatively low. Highly anisotropic processing can be realized while suppressing.

Here, as an example of such a high-density plasma etching apparatus, a configuration example of a helicon wave plasma etching apparatus previously proposed by the present inventor will be described with reference to FIG. The plasma generation unit of this apparatus is provided in parallel with a plasma generation chamber 11 made of a dielectric material for generating a helicon wave plasma P _H therein and a top plate 12 of the plasma generation chamber 11.
= 0 mode single-loop antenna 20 for excitation, half-turn antenna 25 for m = 1 mode excitation partially circling the side wall surface of the same plasma generation chamber 11,
The solenoid coil 18 that circulates in the plasma generation chamber 11 further outside the half-turn antenna 25 and generates a magnetic field along the axial direction is a main constituent element. The constituent material of the plasma generation chamber 1 is, for example, quartz, and its diameter is, for example, 35 cm.

The mounting of the above two systems of high frequency antennas is
The biggest feature of this device is that both antennas are
R through each power feeding system branched from the common RF power source 24
F power is supplied. That is, the single loop antenna 20 is connected to the relay circuit (R / R) as phase adjusting means.
C) 23, drive amplifier 22 as output adjusting means, impedance matching matching network (M /
N) 21 is supplied with RF power in this order, and the half-turn antenna 25 is supplied with a drive amplifier 27 and a matching network (M / N) 26 in this order. The relay circuit 23 is a single loop
Since the purpose is to shift the phases of the high frequencies supplied to the antenna 20 and the half-turn antenna 25 from each other, they may be connected to the half-turn antenna 25 side contrary to the illustrated example. The frequency of the RF power supply 24 is 13.56 MHz, for example. The phase shift caused by the relay circuit 23 is set to, for example, π / 2.

The solenoid coil 18 has a double structure. The inner solenoid coil 18a mainly contributes to the propagation of the helicon wave and the outer solenoid coil mainly contributes to the transportation of the helicon wave plasma P _H. 18b. This solenoid coil is connected to a DC power supply (D / C) 19.

A diffusion chamber 13 is connected to the plasma generation chamber 11, and the helicon wave plasma P _H is drawn into the diffusion chamber 13 along the divergent magnetic field formed by the solenoid coil 18. The side wall surface and the bottom surface of the diffusion chamber 13 are made of a conductive material such as stainless steel. The diffusion chamber 13 is evacuated to a high vacuum through the upper exhaust hole 14 in the direction of arrow A, and is supplied with a predetermined etching gas through the gas supply pipe 15 in the direction of arrow B. The pressure is maintained. Further, the diffusion chamber 13 is connected to the load lock chamber (not shown) from the side wall surface thereof via the gate valve 33. The gas supply pipe 15 includes a first cylinder 16 containing Cl ₂ or HBr,
A second cylinder 17 containing O ₂ gas is connected, and the gas flow rate can be controlled independently by opening / closing each valve.

Further, in order to converge the divergent magnetic field in the vicinity of the wafer stage 29 to the outside of the diffusion chamber 13 and to suppress the disappearance of electrons and active species in plasma by the chamber wall, auxiliary magnetic field generating means. A multi-pole magnet 28 is provided as. The multi-pole magnet 28 generates a multi-cusp magnetic field in the diffusion chamber 13 to confine plasma. The arrangement position of the multi-pole magnet 28 is not limited to the example shown in the figure, and may be another place such as around the support of the wafer stage 29. In addition, or
This may be replaced with a solenoid coil, and the plasma may be confined by forming a mirror magnetic field.

Further, inside the diffusion chamber 13, a conductive wafer stage 29 electrically insulated from the wall surface is accommodated, on which a wafer W as a substrate to be processed is held and dry-etched. Is supposed to do. The wafer stage 29 is supplied with a coolant from a chiller (not shown) in order to maintain the wafer W in process at a desired low temperature, and a cooling pipe 30 for circulating the coolant in the directions of arrows C ₁ and C _2. Has been inserted. In the case of controlling the wafer temperature as described above, it is effective to improve the heat conduction between the wafer W and the wafer stage 29. For this purpose, an electrostatic chuck may be used.

Further, on the wafer stage 29, a bias applying high frequency power source 32 for applying a substrate bias to the wafer W in order to control the energy of ions entering from the plasma, is provided with a second matching network (M / M). N) 31 is connected. Here, the frequency of the high frequency power source 31 for bias application is 13.56 MH.
z.

The above-mentioned helicon wave plasma etching apparatus enables simultaneous excitation of m = 0 mode and m = 1 mode, thereby compensating for the bias of the electron density distribution in the radial direction of the chamber, which is inherent in both modes, and makes it uniform. The present inventor has independently proposed that a high plasma density be obtained. However, the high-density plasma etching apparatus used in the present invention may of course have a conventionally known configuration. In any case, the high-density plasma etching apparatus used in the present invention should be an apparatus capable of achieving an ion current density of at least 5 mA / cm ² . This value is on the order of 10 ¹¹ / cm ³ when converted to plasma density. If the ion current density is lower than the above value, the etching reaction cannot proceed at a practical rate. In the present invention, the upper limit of the ion current density is not particularly specified, but too high ion current density causes shape anomalies due to charge accumulation, or unstable etching due to re-dissociation of reaction products or deposition on chamber walls. Therefore, it is better to decide in consideration of practical performance.

By the way, the silicon nitride film can be etched substantially only with a chlorine-based gas or a bromine-based gas by using the above high-density plasma etching apparatus. It is preferable to add O ₂ gas at the time of etching the substrate. When O ₂ is added, silicon chloride or silicon bromide, which is an etching reaction product, can be changed in situ to silicon oxide, and anisotropic processing can be performed by utilizing its strong side wall protection effect. . In the present invention,
The process from the etching start of the polysilicon film to the etching end of the silicon substrate is performed in the same chamber, but at the time when the material to be etched is switched, it is sufficient to supply / stop the O ₂ gas only and the control is easy.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described.

Example 1 In this example, the above-mentioned helicon wave plasma device having two antennas was used to etch a polysilicon film with a Cl ₂ / O ₂ mixed gas, etch a silicon nitride film with a Cl ₂ gas, The silicon substrate was continuously etched with a Cl ₂ / O ₂ mixed gas. The process of this embodiment will be described with reference to FIGS.

First, FIG. 1 shows a sample wafer used in this embodiment. In this figure, a polishing stopper layer 4 which is a two-layer film of a silicon nitride film 2 (SiN) having a thickness of about 100 nm and a polysilicon film 3 having a thickness of about 100 nm is formed on a silicon substrate 1 (Si), Resist pattern 5 on this
The state where (PR) is formed is shown. The resist pattern 5 is provided with openings 6 according to the trench pattern.

Next, the material film exposed inside the opening 6 is sequentially etched. That is, the polysilicon film 3
, Etching of the silicon nitride film 2, and trench etching of the silicon substrate 1.

First, etching of the polysilicon film 3 is performed.
For example, Cl ₂ flow rate 100 SCCM O ₂ flow rate 5 SCCM pressure 1 Pa source power 2.5 kW (13.56 MHz) RF bias power 100 W (13.56 MHz) wafer temperature 20 ° C. The source power is the single loop antenna 20 and the half turn antenna 25.
Are similarly applied to both. As a result of this etching, as shown in FIG. 2, the polysilicon film 3 was anisotropically processed and the opening 7 was formed.

Next, the silicon nitride film 2 is etched.
For example, Cl ₂ flow rate 100 SCCM pressure 1 Pa source power 2.5 kW (13.56 MHz) RF bias power 300 W (13.56 MHz) wafer temperature 20 ° C. Here, although the etchant is a chlorine-based species, anisotropic etching proceeds at a high speed of about 200 nm / min due to the high ion current density of 30 mA / cm ² or more and the contribution of the increased substrate bias. ,
As shown in FIG. 3, the opening 7 was formed deeper.

Next, the silicon substrate 1 is etched by, for example, Cl ₂ flow rate 100 SCCM O ₂ flow rate 5 SCCM pressure 1 Pa source power 2.5 kW (13.56 MHz) RF bias power 100 W (13.56). MHz) Wafer temperature was 20 ° C. As a result of this etching, as shown in FIG. 4, a trench 8 having a depth of about 800 nm having an anisotropic shape was formed.

In the present embodiment, as described above, the same conditions are adopted for etching the polysilicon film 3 and the silicon substrate 1, and O ₂ is omitted for etching the silicon nitride film 2 while the substrate bias is increased. Adopted. Moreover, O ₂
Even when used together, the addition amount thereof is smaller than that of Cl ₂ , and the influence on the pressure in the chamber is small. Therefore, the switching of these series of etching conditions is
_This can be performed substantially only by controlling the opening / closing of the valve of the second cylinder 17 that houses ₂ , and the three types of material films or substrates can be continuously and efficiently etched while the substrates are kept in the same chamber. I was able to.

After this, as shown in FIG.
₂ Plasma ashing, resist pattern 5
Was removed. After that, as described in the section of the prior art, it was possible to proceed to the steps of depositing the silicon oxide film 9 and planarizing by CMP.

Example 2 In this example, a series of etchings from the polysilicon film 3 to the silicon substrate 1 were carried out using an etching gas mainly composed of bromine gas. The sample wafer used is the same as in Example 1.

The etching conditions are, for example, [etching conditions for the polysilicon film 3] HBr flow rate 100 SCCM O ₂ flow rate 5 SCCM pressure 1 Pa source power 2.5 kW (13.56 MHz) RF bias power 100 W ( Wafer temperature 20 ° C. [Etching conditions for silicon nitride film 2] HBr flow rate 100 SCCM pressure 1 Pa Source power 2.5 kW (13.56 MHz) RF bias power 300 W (13.56 MHz) Wafer temperature 20 ° C. [Etching conditions for silicon substrate 1] HBr flow rate 100 SCCM O ₂ flow rate 5 SCCM pressure 1 Pa Source power 2.5 kW (13.56 MHz) RF bias power 100 W (13.56 MHz) Wafer The temperature was set to 20 ° C.

In this example, since the etching rate of the silicon nitride film 2 was lower than that of the example 1 because the bromine-based etchant was used, the etching rate was 100 nm / min, which is still practically sufficient. I was able to do it.

The two embodiments have been described above.
The present invention is not limited to these embodiments, and the configuration of the sample wafer, the details of the configuration of the etching apparatus used, and the details of the etching conditions can be appropriately changed or selected.

[0036]

As is apparent from the above description, according to the present invention, a laminated system of a polysilicon film / silicon nitride film / silicon substrate having different dry etching characteristics can be installed in the same chamber of a single etching apparatus. Since it is possible to continuously etch with, the trench etching for shallow trench isolation, which is premised on the flattening of the insulating film by CMP, can be performed very efficiently.
Moreover, it becomes possible to perform it precisely. The present invention greatly contributes to improvement in throughput of semiconductor device manufacturing and cost reduction through improvement in efficiency of element isolation process.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing a state where a resist pattern is formed on a polishing stopper layer in a process example in which the present invention is applied to trench processing for shallow trench isolation.

FIG. 2 is a schematic cross-sectional view showing a state where a polysilicon film is dry-etched using the resist pattern of FIG. 1 as a mask.

FIG. 3 is a schematic cross-sectional view showing a state where the silicon nitride film of FIG. 2 is dry-etched.

FIG. 4 is a schematic cross-sectional view showing a state in which a trench has been formed by dry etching the silicon substrate of FIG.

5 is a schematic cross-sectional view showing a state where the resist pattern of FIG. 4 is ashed.

FIG. 6 is a schematic cross-sectional view showing a state in which a silicon oxide film is deposited on the entire surface of the base body so as to fill the trench in FIG.

7 is a schematic cross-sectional view showing a state in which the silicon oxide film of FIG. 6 is removed by chemical mechanical polishing until the polysilicon film is exposed.

8 is a schematic cross-sectional view showing a state in which chemical mechanical polishing is further continued until the silicon nitride film of FIG. 7 is exposed.

FIG. 9 is a schematic cross-sectional view showing a configuration example of a helicon wave plasma etching apparatus used in the present invention.

[Explanation of symbols]

 1 Silicon Substrate 2 Silicon Nitride Film 3 Polysilicon Film 4 Polishing Stop Layer 5 Resist Pattern 8 Trench

Claims (4)

[Claims] 1. An etching mask formed on a polishing stopper layer comprising a silicon substrate and a polishing stopper layer formed on the silicon substrate and a silicon nitride film and a polysilicon film stacked in this order from the lower layer side. A dry etching method of forming a trench in the silicon substrate by sequentially performing dry etching through the silicon substrate, wherein a single etching apparatus is used to etch the silicon substrate from the start of etching the polysilicon film to the end of etching the silicon substrate. The dry etching method in which the dry etching is carried out by using an etching gas mainly containing at least one of chlorine-based gas and bromine-based gas while keeping the same in the same chamber. 2. The dry etching method according to claim 1, wherein an apparatus capable of achieving an ion current density of at least 5 mA / cm ² is used as the etching apparatus. 3. The dry etching method according to claim 1, wherein the etching gas contains O ₂ gas only when the polysilicon film and the silicon substrate are etched. 4. The dry etching method according to claim 1, wherein the trench is filled with an insulating film to form an element isolation region.