JPH09147559A - Dynamic ram - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce current dissipation of a sense amplifier by disconnecting the bit line side used as the reference voltage from the sense amplifier when a signal amplitude of the bit line pair is increased to a certain degree. SOLUTION: When the amplifying operation of a sense amplifier is divided into two stages, the switch MOSFET Q2 turns off synchronously with the amplifying operation of the second stage as the reference voltage side, in synchronization with the amplifying operation of the second stage in which the power switch MOSFET is turned on to give a heavy current. Namely, the shared switch control signal SHRL1 is changed to the H or L level. In the case of obtaining a high level amplified signal, the potential of the bit line/BLL is kept at the intermediate voltage because the bit line/BLL set to the reference voltage side is disconnected and only the internal node of the sense amplifier is changed to the L level. Because the discharge current of the bit line/BLL is cut off, current dissipation in the sense amplifier can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic RAM (Random Access Memory), and more particularly to a technique effective when used in a half precharge system.

[0002]

2. Description of the Related Art A pair of bit lines (or data lines) are arranged in parallel, and when a read signal from a memory cell is obtained on one bit line, the precharge voltage of the other bit line is used as a reference voltage. There is a folded bit line type dynamic RAM which is used for amplification by a sense amplifier. As an example of such a dynamic RAM, there is JP-A-6-68666.

[0003]

The dynamic memory cell stores information in the form of electric charge in a capacitor, and the information is read out by the charge distribution of the capacitor and the bit line by the selection operation of the word line. . In order to restore the storage charge that is about to be destroyed in the storage capacitor due to the charge distribution with the bit line to the original state, the capacitor is rewritten by the high level / low level potential of the bit line amplified by the sense amplifier. Is done. The inventor of the present application has noticed that what is required to rewrite the memory cell as described above is the bit line to which the memory cell is connected among the bit line pair. Therefore, when the potential difference between the pair of bit lines becomes large to some extent due to the amplifying operation of the sense amplifier, it is considered that the bit line used for obtaining the reference voltage is disconnected from the sense amplifier to achieve low power consumption.

An object of the present invention is to provide a dynamic RAM which realizes low power consumption. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0005]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a half precharge type dynamic RAM having a memory array in which dynamic memory cells are arranged in a matrix at an intersection of one of a plurality of bit line pairs and a word line, the dynamic line selected by the word line selecting operation is selected. Signal read from the memory cell to one of the bit line pair is amplified by a sense amplifier using the precharge voltage of the other bit line as a reference voltage, and the sense amplifier amplifies the signal of the bit line pair. The bit line side used as the reference voltage is disconnected from the sense amplifier when the amplitude is increased to some extent.

[0006]

1 and 2 are block diagrams of an embodiment of a dynamic RAM to which the present invention is applied. FIG. 1 shows a memory array and its peripheral selection circuit, and FIG. 2 shows an input / output interface unit such as an address buffer and an input / output buffer and a timing control circuit. Each circuit block in the figure is formed on one semiconductor substrate by a known semiconductor integrated circuit manufacturing technique.

In FIG. 1, two memory mats MAT are shown.
0 and MAT1, a sense amplifier SA01 is provided. That is, the sense amplifier SA01 is a shared sense amplifier selectively used for the two memory mats MAT0 and MAT1. Sense amplifier SA
Although not shown, a selection switch is provided in the input / output unit 01 of complementary bit lines (or sometimes called complementary data lines or complementary digit lines) arranged substantially in parallel with the memory mats MAT0 or MAT1. Connected.

Other memory mats MAT2 and MAT3,
MAT4, MAT5 and MAT6, MAT7 are also paired, respectively, and sense amplifiers SA23, SA
45 and SA67 are provided in common. A total of eight memory mats MAT0 to MAT7 and four sense amplifiers SA01 to SA67 as described above constitute one memory array MARY0. This memory array MARY
For 0, a Y decoder YDEC is provided. A memory array MARY1 is provided symmetrically with the Y decoder YDEC interposed therebetween. The memory array MARY1 has the same internal structure as the memory array MARY0, although the internal structure is omitted. A plurality of sets are provided in terms of memory capacity based on the circuit blocks as described above.

Decoders XD0 to XD7 are provided in each of the memory mats MAT0 to MAT7. These decoders XD0 to XD7 decode the output signal AXi of the predecoder circuit XPD to form four word line selection signals. These decoders XD0 to XD7 and mat control circuits MATCTRL01 to MATCTRL67 to be described next
And word drivers WD0 to WD7 for forming word line selection signals in accordance with the output signals. The word driver includes a word driver corresponding to a spare word line for repairing a defect.

The pair of memory mats MAT0, MAT
A mat control circuit MATCTRL01 is provided corresponding to 1. Other paired memory mats MAT2 and MAT
Similar mat control circuits MATCTRL23, MATCTRL45, MATC
A TRL 67 is provided. Mat control circuit MAT CTR
L01 to MATCTRL67 are mat selection signals MSi
And the signal XE, the sense operation timing signal φSA, and the decoding signal of the lower two bits of the address signal, one mat control circuit for the selected memory mat switches one of the four word lines to one. Select signal X to select
It outputs iB and the like.

In addition to this, the mat control circuit MATCTRL
01 to MATCTRL67 keep the bit line selection switch corresponding to the left or right memory mat corresponding to the selected memory mat in the on state, and set the bit line selection switch corresponding to the non-selected memory mat to the off state. And a timing signal for starting the amplification operation of the sense amplifier. Further, as described later, in order to reduce current consumption, the bit line selection switch for supplying the reference voltage to the sense amplifier in the selected memory mat is turned off when the amplified signal of the sense amplifier becomes large to some extent. .

When the defective word line is accessed, the selection signal XiB is set by the low level of the signal XE.
And the like are inhibited from being output, and the operation of selecting a defective word line is stopped. Instead, the selection signal XRi on the redundant circuit side
Since B is formed, the spare word line is selected.

In FIG. 2, the timing control circuit TG
Is a row address strobe signal / RAS, a column address strobe signal / CAS supplied from an external terminal,
Receiving the write enable signal / WE and the output enable signal / OE, it determines the operation mode and correspondingly forms various timing signals necessary for the operation of the internal circuit. In this specification and the drawings, the symbol / is used to mean that the low level is the active level.

Signals R1 and R3 are row-system internal timing signals, and are used for a row-system selection operation to be described later. The timing signal φXL is a signal for taking in and holding a row-related address, and is supplied to the row address buffer RAB. That is, the row address buffer RAB fetches an address input from the address terminals A0 to Ai in response to the timing signal φXL and causes the latch circuit to hold the address.

The timing signal φYL is a signal for fetching and holding the column address, and is supplied to the column address buffer CAB. That is, the column address buffer RAB fetches an address input from the address terminals A0 to Ai in response to the timing signal φYL and causes the latch circuit to hold the address.

The signal φREF is a signal generated in the refresh mode, and is supplied to the multiplexer AMX provided in the input part of the row address buffer.
In the refresh mode, control is performed to switch to the refresh address signal formed by the refresh address counter circuit RFC. The refresh address counter circuit RFC counts the refreshing step pulse φRC formed by the timing control circuit TG to generate a refresh address signal. In this embodiment, an auto refresh and a self refresh are provided.

The timing signal φX is a word line selection timing signal, is supplied to the decoder XIB, and is 4 based on the decoded signal of the address signal of the lower 2 bits.
Word line selection timing signals XiB are formed. The timing signal φY is a column selection timing signal and is supplied to the column system predecoder YPD to output the column selection signals AYix, AYjx, AYkx. The lower 2 bit address signal of the lower 2 bit address signal is used as a signal for turning off the bit line selection switch for supplying the reference voltage to the sense amplifier when the amplified signal of the sense amplifier becomes large to some extent. To be done.

The timing signal φW is a control signal instructing a write operation, and the timing signal φR is a control signal instructing a read operation. These timing signals .phi.W and .phi.R are supplied to the input / output circuit I / O to activate the input buffer included in the input / output circuit I / O during the write operation and bring the output buffer into the output high impedance state. On the other hand, at the time of the read operation, the output buffer is activated, and the input buffer is set to the output high impedance state.

The timing signal φMS is a signal for instructing a mat selection operation, is supplied to the row address buffer RAB, and is synchronized with this timing, the mat selection signal M.
Si is output. Timing signal φSA is a signal for instructing the operation of the sense amplifier. Based on the timing signal φSA, in addition to the activation pulse of the sense amplifier being formed, a control signal for precharge termination operation of the complementary bit line and operation for disconnecting the bit line on the non-selected memory mat side is formed. Also used for.

In this embodiment, the row redundancy circuit X-R is used.
DE is exemplarily shown as a representative. That is, the circuit X-RED includes a storage circuit for storing a defective address and an address comparison circuit. The stored defective address is compared with the internal address signal BXi output from the row address buffer RAB, and when they do not match, the signal XE is set to the high level, and the signal XEB is set to the low level to enable the operation of the normal circuit. When the input internal address signal BXi matches the stored defective address, the signal XE is set to a low level to inhibit the operation of selecting a defective word line of the normal circuit, and the signal XE
By setting B to a high level, a selection signal XRiB for selecting one spare word line is output.

Although not shown in FIG. 2, a circuit similar to the above row system circuit is also provided in the column system, and when a memory access to the defective bit line is detected thereby, the defective bit line by the column decoder YD is detected. The selection signal is selected, and instead, a selection signal for selecting a spare bit line is formed.

FIG. 3 shows a circuit diagram of a main portion of an embodiment of the memory array portion of the dynamic RAM according to the present invention. In the figure, 4 of the memory mat MAT0
One word line, two pairs of complementary bit lines and their associated sense amplifiers and precharge circuits are exemplarily shown as representatives, and the memory mat MAT1 is shown as a black box. Further, a circuit symbol is added as a representative only to the MOSFETs forming each circuit corresponding to the pair of complementary bit lines BLL and / BLL.

The dynamic memory cell comprises an address selecting MOSFET Qm and an information storing capacitor Cs. The gate of the address selection MOSFET Qm is connected to a word line WLi.
Is connected to the bit line / BLL, and the source is connected to the information storage capacitor Cs. The other electrode of the information storage capacitor Cs is made common and the plate voltage VP
L is given. Two memory cells are alternately arranged with respect to the bit line pair. For example, word line WL
The drains of the address selection MOSFETs of the two memory cells corresponding to 0 and WL1 are made common and the bit line BL
L.

When the two memory cells are arranged adjacent to each other in this way, the drains of the two MOSFETs can be formed in common, and the two memory cells can be connected to the bit line BLL by one contact hole. You can The word lines WL2 and WL3 are omitted, but other word lines WLi and WL (i− are shown as an example.
As in 1), the MO for address selection of two memory cells
The drains of the SFETs are commonly connected to the bit line / BLL.

In the configuration in which two memory cells are alternately connected to the bit pair BLL and / BLL as described above, the lower 2 bits of the row-system address signal forming the selection signal of the word line WL are set. The address signal A1 makes it possible to determine which of the complementary bit lines BLL and / BLL the selected memory cell is connected to. For example, if the address A1 is low level, the word lines WL0 and W
Since L1 and the like are selected, it is known that the selected memory cell is connected to the bit line BLL side. If the address signal A1 is at the high level, word lines WL2 and WL3 and the like are selected. It can be seen that the selected memory cell is connected to the / BLL side. From this, the bit line used to supply the reference voltage to the sense amplifier can also be identified.

The bit lines BLL and / BLL are arranged in parallel as shown in the figure, and are appropriately crossed as needed to balance the capacitance and noise of the bit lines. The complementary bit lines BLL and / BLL are
The switch MOSFETs Q1 and Q2 are connected to the input / output node of the sense amplifier. The sense amplifier has N-channel type MOSFETs Q5 and Q6 and a P-channel type M in which a gate and a drain are cross-connected to form a latch form
It is composed of OSFETs Q7 and Q8. The sources of the N-channel MOSFETs Q5 and Q6 are the common source line CS
N. P-channel MOSFET Q7 and Q
The sources of 8 are connected to the common source line CSP. As exemplarily shown in the common source line CSP, a power switch MOSFETQ of a P-channel type MOSFET
14 is provided and when the timing signal φSAP is set to the low level, the MOSFET Q14 is turned on,
Supplies the voltage required for the operation of the sense amplifier. An unillustrated N-channel MOSFET is provided on the common source line CSN corresponding to the N-channel MOSFETs Q5 and Q6, and supplies the ground potential of the circuit at the operation timing of the line.

The power switch MOSFET for activating the sense amplifier is turned on so that a relatively small current can be supplied at the time when the sense amplifier starts the amplification operation in order to perform a stable sensing operation. Then, the amplifying operation is performed stepwise by turning on the power switch MOSFET that causes a large current to flow when the potential difference between the bit lines BLL and / BLL becomes large to some extent by the amplifying operation of the sense amplifier. To be

The input / output node of the sense amplifier is provided with a MOSFET Q11 for short-circuiting the complementary bit line, and a precharge circuit composed of switch MOSFETs Q9 and Q11 for supplying the half precharge voltage HVC to the complementary bit line. A precharge signal PCB is commonly supplied to the gates of these MOSFETs Q9 to Q11. The input / output node of the sense amplifier is connected to the memory mat M via shared switch MOSFETs Q1 and Q2.
It is connected to the bit lines BLL and / BLL of AT0, and is connected to a similar bit line (not shown) of the memory mat MAT1 via shared switch MOSFETs Q3 and Q4.

The MOSFETs Q12 and Q13 are column switches which are switch-controlled by a column selection signal YS.
Configure. In this embodiment, one column selection signal YS
Thus, four pairs of bit lines can be selected. Therefore, the column selection signal YS is provided at the input / output nodes of four sense amplifiers corresponding to the two pairs of bit lines exemplarily shown in the figure and the remaining two pairs of bit lines (not shown). The power is commonly supplied to the gates of the MOSFETs constituting the column switch, and the four pairs of bit lines and the four pairs of input / output lines I / O are connected via the switch MOSFETs.

In this embodiment, the shared switch MOSFETs Q1 and Q2 do not have common gates as in the prior art, but control signals SHRL0 and SHRL, respectively.
RL1 is supplied. This means that the control signals SHLL0 and SHLL1 are similarly supplied to the other shared switch MOSFETs Q3 and Q4, respectively. These control signals SHRL0, SHRL1 and SHLL0
And SHLL1 are in the ON state when the memory is in the non-selected state, and the MOSFET of the precharge circuit is
The complementary bit lines of the left and right memory mats MAT0 and MAT1 are short-circuited by Q11, and the precharge voltage HVC is applied via the MOSFETs Q9 and Q10.

As shown in the timing chart of FIG. 4, when the word line WL0 of the memory mat MAT0 is selected by the memory access, for example, the unselected memory mat M is selected.
Shared switch control signal SH corresponding to AT1 side
RR0,1 is changed from the high level to the low level, and the shared switch MOSFETs Q3 and Q4
Etc. are turned off. As a result, the read signal from the memory cell connected to the word line WL0 appears on the bit line BLL due to charge distribution with the stored charge of the capacitor of the memory cell. The minute voltage of the bit line BLL is amplified by the amplifying operation of the sense amplifier using the precharge voltage of the other bit line / BLL as a reference voltage.

Although not particularly limited, when the amplification operation of the sense amplifier is divided into two stages as described above,
The shared switch MOSFET Q2 corresponding to the bit line / BLL on the reference voltage side is turned off in synchronization with the second-stage amplification operation in which the power switch MOSFET that allows a large current to flow is turned on. . That is, the shared switch control signal SHRL1 is changed from the high level to the low level. Such a change in the shared switch control signal SHRL1 is a combination of the address signal A1 being at a low level and a timing signal for turning on the power switch MOSFET for the second-stage amplifying operation of the sense amplifier. Formed.

Such a shared switch MOSFE
Due to the off state of TQ2, the sense amplifier is disconnected from the bit line / BLL and acts to reduce the current that charges it up or discharges it.
When a high-level amplified signal is obtained as shown in the figure, the potential of the bit line / BLL stays at the intermediate potential by disconnecting the bit line / BLL on the side of the reference voltage. Only the internal node of is changed to low level. Such bit line / BL
By cutting off the discharge current of L, the current consumption in the sense amplifier can be reduced.

The disconnection of the bit line on the reference voltage side as described above not only acts to reduce the operating current of the sense amplifier, but also speeds up the signal change of the corresponding internal node on the reference voltage side. Therefore, as a result, the signal change of the bit line BLL on the read signal side is also accelerated. That is, when amplifying the bit line BLL to a high level, the bit line / BLL is disconnected, so that the N-channel MOSFET of the sense amplifier.
As a result of the high-speed discharging by Q6, the conductance of the P-channel MOSFET Q7 whose gate is supplied with such a low level signal increases. When the bit line BLL is amplified to the low level,
As a result of the bit line / BLL being disconnected, the charge-up by the P-channel MOSFET Q8 of the sense amplifier is performed at high speed, and as a result, the N-channel MOSFET Q whose gate is supplied with such a high level signal.
Increase the conductance of 5. By speeding up the signal change at the internal node of the sense amplifier as described above, it is possible to reduce the direct current (through current) flowing through the N-channel type MOSFET and the P-channel type MOSFET forming the sense amplifier.

When one of the complementary bit lines is separated as described above, the read signal is the full amplitude signal of the sense amplifier and the column switch MO.
Since it is transmitted to the input / output line I / O via the SFETs Q12, Q13, etc., no problem occurs. In the write operation, of the complementary signals transmitted through the input / output line I / O, only the signal to be transmitted to the memory cell maintains the above-mentioned ON state in the shared switch MOSFET Q1.
Alternatively, since it is transmitted to the memory cell through Q2, no problem occurs.

The functions and effects obtained from the above embodiment are as follows. (1) In a half precharge type dynamic RAM having a memory array in which dynamic memory cells are arranged in a matrix at an intersection of one of a plurality of bit line pairs and a word line, it is selected by the word line selecting operation. A minute signal read from the dynamic memory cell to one of the bit line pairs is amplified by a sense amplifier using the precharge voltage of the other bit line as a reference voltage. By disconnecting the bit line side used as the reference voltage from the sense amplifier when the signal amplitude is increased to some extent, the effect that the current consumption in the sense amplifier can be reduced is obtained.

(2) Since the signal change at the internal node of the sense amplifier can be made faster by the above (1), a change in the amplified signal of the bit line connected to the memory cell can be achieved while reducing the direct current in the sense amplifier. The effect of being able to speed up is obtained.

(3) The bit line pairs are arranged substantially in parallel, two dynamic memory cells are alternately arranged with respect to the bit line pairs, and two dynamic memory cells are arranged. By sequentially connecting to the word line, the bit line from which the minute signal is read and the bit line forming the reference voltage are determined corresponding to the address signal of the lower 2nd bit of the X address signal. There is an effect that the address signal can be used as it is for the switch control of the switch MOSFET.

(4) A shared sense amplifier is used in which the sense amplifier is commonly used for two bit line pairs.
A shared switch MO for connecting one of the two pairs of bit lines selected to the sense amplifier.
By using the SFET together with the switch MOSFET that disconnects the bit line on the reference voltage side, it is possible to obtain an effect that low power consumption and high speed can be realized with a simple configuration.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the sense amplifier may have a configuration in which the sense amplifier and the bit line are provided in one-to-one correspondence in addition to the shared sense amplifier as described above. As for the arrangement of the memory cells, two memory cells are provided for each adjacent word line as described above, or the memory cells may be alternately connected to the bit lines BLL and / BLL for each adjacent word line. In this case, the address control signal A0 of the least significant bit may be used to form the switch control signal of the bit line to be cut off. The present invention can be widely used for dynamic RAM. That is, the dynamic RAM is a synchronous dynamic RAM.
Also, of course, those using dynamic type memory cells such as image memories such as pseudo static type RAM and 2-port memory are also included.

[0041]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a half precharge type dynamic RAM having a memory array in which dynamic memory cells are arranged in a matrix at an intersection of one of a plurality of bit line pairs and a word line, the dynamic line selected by the word line selecting operation is selected. Signal read from the memory cell to one of the bit line pair is amplified by a sense amplifier using the precharge voltage of the other bit line as a reference voltage, and the sense amplifier amplifies the signal of the bit line pair. By disconnecting the bit line side used as the reference voltage from the sense amplifier when the amplitude is increased to some extent, the current consumption in the sense amplifier can be reduced.

As described above, the change in the signal at the internal node of the sense amplifier can be made fast, so that the change in the amplified signal of the bit line to which the memory cell is connected can be made fast while reducing the direct current in the sense amplifier.

The bit line pairs are arranged substantially in parallel,
Two dynamic memory cells are alternately arranged with respect to the bit line pair, and the two dynamic memory cells are sequentially connected to the word line.
By deciding a bit line from which a minute signal is read out and a bit line forming a reference voltage corresponding to the address signal of the lower 2nd bit of the X address signal, the address signal is used as it is for the switch. MO
It can be used for SFET switch control.

A shared switch MOSFET that uses a shared sense amplifier in which a sense amplifier is commonly used for two pairs of bit lines, and connects any one of the above two pairs of bit lines to the sense amplifier.
And a switch MO for disconnecting the bit line on the reference voltage side.
When used in combination with SFET, low power consumption and high speed can be realized with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a memory array and its peripheral selection circuit in a dynamic RAM to which the present invention is applied.

FIG. 2 is a block diagram showing an embodiment of an input / output interface section and a timing control circuit in a dynamic RAM to which the present invention is applied.

FIG. 3 is a circuit diagram of essential parts showing an embodiment of a memory array section of a dynamic RAM according to the present invention.

FIG. 4 is a timing chart for explaining an example of the operation of the dynamic RAM according to the present invention.

[Explanation of symbols]

MAT0 to MAT7: Memory mat, MARY0, MA
RY1 memory array, XD0 to XD7 decoder circuit, WD0 to WD7 word driver, SA01 to SA
67: sense amplifier, XDEC: row decoder circuit, A
RYCTRL: array control circuit, YDEC: column decoder circuit, MATCTRL0 to MATCTRL3: mat control circuit, TG: timing control circuit, I / O: input / output circuit, RAB: row address buffer, CAB: column address buffer, AMX: multiplexer, RFC
... Refresh address counter circuit, XPD, YPD
... Pretecoder circuit, X-DEC ... Row system redundant circuit, X
IB ... Decoder circuit, Qm ... Address selection MOSFE
T, Cs ... Information storage capacitors, Q1 to Q14 ... MOS
FET, BLL, / BLL ... Bit line, WL0 to WLi
... Word line, CSP, CSN ... Common source line, SHRL
0-SHRR1 ... Shared switch control signal, YS ...
Column selection signal, HVC ... Half precharge voltage.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroyuki Uchida 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. (72) Inventor Hiroshi Yoshida 5 Kamimizumoto-cho, Kodaira-shi, Tokyo Chome No. 20-1 Hitate Super L.S.I. Engineering Co., Ltd. (72) Inventor Rinyo Watanabe 5-20-1 Joumizuhoncho, Kodaira-shi, Tokyo Incorporated company Hitachi Ltd. Semiconductor Business Division

Claims (3)

[Claims] 1. A memory array in which dynamic memory cells are arranged in a matrix at an intersection of one of a plurality of bit line pairs and a word line, and a precharge circuit for applying the same precharge voltage to each of the plurality of bit line pairs. ,
A sense amplifier that amplifies a minute signal read from the dynamic memory cell selected by the word line selecting operation to one of the bit line pairs using the precharge voltage of the other bit line as a reference voltage; A switch MOSFET which is provided between the sense amplifier and the bit line pair, and which disconnects the bit line side used as the reference voltage when the sense amplifier increases the signal amplitude of the bit line pair by the amplification operation to some extent. A dynamic RAM that is characterized by: 2. The bit line pairs are arranged substantially in parallel, two dynamic memory cells are alternately arranged with respect to the bit line pairs, and the two dynamic memory cells are arranged in order. By connecting to the word line, the bit line from which the minute signal is read out and the bit line forming the reference voltage are determined corresponding to the address signal of the lower 2nd bit of the X address signal. 2. The dynamic RAM according to claim 1, wherein a signal is used to control the switch of the switch MOSFET. 3. The sense amplifier is commonly provided for two pairs of bit lines provided around the sense amplifier, and the switch MOSFET is one of the two pairs of bit lines. 2. The dynamic RAM according to claim 1, wherein the dynamic RAM also serves as a shared switch MOSFET for connecting the selected one to the sense amplifier.