JPH06338199A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To lower the probability of the occurrence of defects when a defective word or bit line is switched to a standby word or bit line so as to improve the operating margin of a semiconductor storage device by providing standby bit or word lines at nearly the central part of the memory mat of the storage device. CONSTITUTION:Word lines WL0-WLn are arranged in parallel in the longitudinal direction. Paired complementary bit lines, the one ends of which are connected to paired input-output nodes of sense amplifiers SA, are arranged in parallel in the transversal direction. The complementary bit lines BL1T and BL1B having odd numbers having twist sections in which the arrangement of the lines are changed to each other at their central parts. In addition, two standby word lines RWL0 and RWL1 are provided at the left-side central parts of the twist sections and two standby word lines RWL2 and RWL3 are provided on the right-side central parts. As a result, the occurrence of defects at the central part of a memory mat is relatively reduced against the occurrence of defects at edge sections. Therefore, the defect remedying probability when a normal word line is switched to a standby work line without tests due to a defect can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a technique effective for use in a defect relief circuit having a twisted portion on a complementary bit line.

[0002]

2. Description of the Related Art A dynamic RAM (random access memory) which is provided with a spare word line or a bit line (sometimes called a data line or a digit line) to repair a defective bit line or a defective data line. There is memory). Regarding the defect repair technique for such a dynamic RAM, there is, for example, JP-A-3-214699.

[0003]

The conventional dynamic RAM has a problem that the defect cannot be relieved even if the defective word line is switched to the spare word line. Therefore, it is conceivable to test the spare word line, identify whether there is a defect, and perform defect relief.
However, in order to identify whether or not there is a defect in the spare word line, a test mode different from the normal operation is set and then the memory cell connected to the spare word line or bit line is accessed. Because it will be a test,
The procedure and the generation of the test pattern will be different from the normal test pattern. Therefore, in the mass-produced dynamic RAM, it is currently difficult to perform a test operation for each spare word line and each spare bit line in order to shorten the test time.

In the conventional dynamic RAM,
Spare word lines or bit lines are located at the edges of the memory mat. The inventor of the present application has considered increasing the practical defect repair probability by paying attention to the fact that the defect occurrence rate at the end of the memory mat is relatively higher than that at the central portion of the memory mat. In addition, in the present inventor,
If a spare word line is provided at the end of the memory mat, a bit line twist section is provided in the center to reduce the effect of capacitive coupling with adjacent bit lines. It has been found that there is a problem that the bit line capacitance is unbalanced as a result.

An object of the present invention is to provide a semiconductor memory device which can increase the probability of defect relief. Another object of the present invention is to provide a semiconductor memory device having an improved operation margin. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, the spare bit line or word line is arranged in the approximate center of the memory mat.

[0007]

According to the above-mentioned means, since the probability of failure occurrence in the spare word line or bit line is low, the failure probability in switching the defective word line or bit line to the spare word line or bit line is low. can do.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a dynamic type R according to the present invention.
A schematic pattern diagram of one embodiment of the memory mat portion of the AM is shown. The respective circuits and wirings in the figure are formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. The respective circuits and wirings in the figure are drawn almost in conformity with the actual geometrical arrangement on the semiconductor substrate.

In the figure, the word lines WL0 to WLn are arranged side by side so as to extend in the vertical direction. A pair of complementary bit lines whose one ends are connected to a pair of input / output nodes of the sense amplifier SA are arranged side by side so as to extend in the horizontal direction. Although not particularly limited, in this embodiment, in order to cancel the influence of capacitive coupling between adjacent bit lines by the differential sense amplifier SA, the odd-numbered complementary bit lines BL1T and BL1B are A twist portion is provided in the central portion, the arrangements of which are interchanged with each other.

In this embodiment, two spare word lines RWL0 and RWL1 are provided in the central portion on the left side of the twisted portion in order to increase the defect repair rate with a simple structure, and the twisted portion is sandwiched therebetween. Two spare word lines RWL2 and RWL3 are provided in the central portion on the right side.

In this structure, the number of intersecting word lines can be made the same including the spare word lines when viewed from the complementary bit line side. As a result, the number of memory cells connected to the left and right of the twisted portion in the bit line can be made equal, so that it is possible to balance the capacitance and expand the operation margin.

That is, as a word line, generally, four word lines are selected by a unit decoder, and one of them is selected. Therefore, when the above-mentioned twist portion is provided, a spare word is prepared. The side where the line is provided is the word line 4
The pitch becomes longer, and the number of connected memory cells increases, resulting in the above imbalance. On the other hand, in the present application, as described above, a total of four spare word lines can be arranged side by side with two twisted parts sandwiched therebetween, so that a common spare decoder can be provided for them.

In this embodiment, the spare bit line is also RBL.
2 like 0T, RBL0B and RBL1T, RBL1B
A pair is provided at the center of the memory mat. These complementary bit lines RBL0T, RBL0B and RBL1T, RBL
A sense amplifier SA is provided in 1B. The spare bit lines RBL0T, RBL0B and RBL1T, RB
The sense amplifier provided corresponding to L1B is controlled like other sense amplifiers. Therefore, unlike the spare word line, the spare bit lines RBL0T, RBL0B and RBL0B
In BL1T and RBL1B, the sense amplifier SA is operated regardless of whether or not there is defect relief. For one of these bit lines, RBL1T and RBL1B have a twisted portion at the center. As a result, it is possible to maintain the regularity between the one having no twist portion of the bit line and the one having the twist portion as a whole.

In FIG. 1, the memory cell MC is connected to a portion indicated by a circle at an intersection of a word line and one of complementary bit lines. The memory cell MC is composed of an address selection MOSFET and an information storage capacitor, as is well known. The gate of the address selecting MOSFET is connected to the word line, and one of the source and drain is connected to the bit line. The other source and drain of the address selection MOSFET are connected to one electrode of the capacitor.

In the above structure, the defect occurrence rate in the central portion of the memory mat is relatively lower than the defect occurrence rate in the end portion of the memory mat. Therefore, it is possible to increase the defect relief probability when the spare word line is uniformly switched without testing the spare word line due to a defect in one of the normal word lines. In this embodiment, even if the test on the spare word line is omitted as described above, the probability of defect repair can be increased, so that it is effective when applied to a dynamic RAM or the like which is a mass-produced general-purpose memory. .

The row address centering on the twist section can simplify the data scramble logic. That is, the level of the read data is reversed due to the replacement of the complementary bit lines, so it is necessary to logically correct it and write / read the data for the test. In such a data scramble process, the physical levels of the memory cells divided by sandwiching the twist part are inverted and input to the sense amplifier, so that the inversion / high level of the 1-bit address corresponding to the twist part is inverted / reduced. Only non-reversal processing is required. This is effective in the test mode when the defective word line is switched to the spare word line.

FIG. 2 is a circuit diagram showing an embodiment of the spare word line selection circuit. The signal XEB is a signal that goes high when an access to a defective word line is detected. This signal XEB and the RAS timing signal R2
Are supplied to the NAND gate circuit G1, and the output signal of the NAND gate circuit G1 enables the spare word line selection circuit through the inverter circuit N1.

The signal MSi is a mat select signal, and the signals BX1B, BX1T and BX0B, BX0T are signals corresponding to the address signals of the lower 2 bits, and select one of the four word lines. Used for. The NAND gate circuits G2 to G5 are enabled by the output signal of the inverter circuit N1 and the mat selection signal MSi, and the internal address signals BX1B, BX1T and BX0.
By decoding B and BX0T, one of the selection signals XR0B to XR3B of one spare word line is set to the low level. As a result, instead of the defective word line, the spare word line corresponding to one of the spare word line selection signals XR0B to XR3B set to the low level is brought into the selected state.

FIG. 3 is a timing diagram of an embodiment for explaining the word line selection operation. The row address signal is taken in by the low level of the row address strobe signal RASB. That is, the internal signal R1 is set to the high level by the low level of the signal RASB, and the address signal Ai is set to the row address (ROW).
Is taken in as.

The level of the internal signal BXi is determined corresponding to the fetched row address ROW. By decoding the internal signal BXi, the mat selection signal MS0 is set to the high level. The signal R1 is compared with the defective address, and when the defective address is not accessed, the signal XE is set to the high level. The internal signal R2 is set to the high level after the signal R1. The signal R2 and the signal XE bring the word line selection timing signal X0B corresponding to one word line out of four word lines to the low level. Since the selection signals for four word lines are formed by the predecoder circuit that decodes other row-related address signals, the word line WL0 is brought into the selected state of the high level in synchronization with the low level of the signal XB0. To be done.

In the next memory cycle, when the memory access is to the defective word line, the signal XE is kept at the low level. As a result, the selection operation of the defective word line is prohibited, and the signal XEB as shown in FIG.
Becomes high level, and at the timing when the signal R2 is made high level, the selection signal XRB corresponding to the spare word line is
0 is set to low level. In synchronism with the low level of the signal XR0B, the spare word line RWL0 is brought into the high level selected state.

FIG. 4 and FIG. 5 are block diagrams showing an embodiment of a main part of the dynamic RAM according to the present invention. FIG. 4 shows a memory array and its peripheral selection circuit, and FIG. 5 shows an input / output interface unit such as an address buffer and an input / output buffer and a timing control circuit.

In FIG. 4, two memory mats MAT
A sense amplifier SA01 is provided between 0 and MAT0. That is, the sense amplifier SA01 is a shared sense amplifier that is selectively used for the two memory mats MAT0 and MAT1. Sense amplifier SA
The input / output unit 01 is provided with a selection switch (not shown) and is connected to the complementary bit line of the memory mat MAT0 or MAT1.

Other memory mats MAT2 and MAT3,
MAT4, MAT5 and MAT6, MAT7 are also paired, and sense amplifiers SA23, SA are provided respectively.
45 and SA67 are commonly provided. With the total of 8 memory mats and 4 sense amplifiers as described above, 1
One memory array MARY0 is configured. A Y decoder YD is provided for this memory array MARY0. The memory array MA is symmetrically arranged with the Y decoder YD in between.
RY1 is provided. This memory array MARY1 is
Although the internal structure is omitted, the above memory array MAR
The configuration is similar to that of Y0.

Decoders XD0 to XD7 are provided in each of the memory mats MAT0 to MAT7. These decoders XD0 to XD7 decode the output signal address signal AXi of the predecoder circuit XPD and form word line selection signals for four lines. The decoders XD0 to XD7 and mat control circuits MATCTRL01 to MAT described below.
Word drivers WD0 to WD7 are provided which form word line selection signals in accordance with the output signal of CTRL 67. This word driver also includes a word driver corresponding to the spare word line.

The pair of memory mats MAT0 and MAT
A mat control circuit MATCTRL01 is provided corresponding to 1. Another pair of memory mats MAT2, MAT
Similar mat control circuits MATCTRL23, MATCTRL45, and MATC for 3 to MAT6 and MAT7
A TRL 67 is provided. Mat control circuit MAT CTR
L01 to MATCTRL67 are mat selection signals MSi
One of the four word lines in one mat control circuit for the selected memory mat in response to the signal XE, the sense operation timing signal φSA, and the decoded signal of the lower 2 bits of the address signal. A selection signal XiB for selecting is output. In addition to this, the bit line selection switches corresponding to the left or right memory mats corresponding to the selected memory mat are left in the ON state, and the bit line selection switches corresponding to the unselected memory mats are turned off. And a timing signal for starting the amplification operation of the sense amplifier.

When the defective word line is accessed, the selection signal XiB is set by the low level of the signal XE.
Since the output of the above is prohibited, the operation of selecting the defective word line is stopped. Instead of this, the selection signal XRi on the redundant circuit side
Since B is formed, the spare word line is selected.

In FIG. 5, the timing control circuit TG
Is a row address strobe signal RASB, a column address strobe signal CASB, supplied from an external terminal,
Upon receiving the write enable signal WEB and the output enable signal OEB, various timing signals necessary for determining the operation mode and correspondingly operating the internal circuit are formed.

The signals R1 and R2 are row-system internal timing signals and are used as shown in FIG. The timing signal φXL is a signal for fetching and holding a row address, and is supplied to the row address buffer RAB. That is, the row address buffer RAB fetches the address input from the address terminals A0 to Ai by the timing signal φXL and holds it in the latch circuit.

The timing signal φYL is a signal for fetching and holding the column address and is supplied to the column address buffer CAB. That is, the column address buffer RAB fetches the address input from the address terminals A0 to Ai by the timing signal φYL and causes the latch circuit to hold the address.

The signal φREF is a signal generated in the refresh mode and is supplied to the multiplexer AMX provided in the input section of the row address buffer.
In the refresh mode, control is performed to switch to the refresh address signal formed by the refresh address counter circuit RFC. The refresh address counter circuit RFC counts the refreshing step pulse φRC formed by the timing control circuit TG to generate a refresh address signal.

The timing signal φX is a word line selection timing signal, is supplied to the decoder XIB, and is 4 based on the decoded signal of the address signal of the lower 2 bits.
The same word line selection timing signal XiB is formed. The timing signal φY is a column selection timing signal and is supplied to the column system predecoder YPD to output the column selection signals AYix, AYjx, AYkx.

The timing signal φW is a control signal for instructing a write operation, and the timing signal φR is a control signal for instructing a read operation. These timing signals .phi.W and .phi.R are supplied to the input / output circuit I / O to activate the input buffer included in the input / output circuit I / O during the write operation and bring the output buffer into the output high impedance state. On the other hand, during the read operation, the output buffer is activated and the input buffer is set to the output high impedance state.

The timing signal φMS is a signal for instructing a mat selection operation, is supplied to the row address buffer RAB, and is synchronized with this timing, the mat selection signal M.
Si is output. Timing signal φSA is a signal instructing the operation of the sense amplifier. Based on the timing signal φSA, in addition to the activation pulse of the sense amplifier being formed, a control signal for precharge termination operation of the complementary bit line and operation for disconnecting the bit line on the non-selected memory mat side is formed. Also used for.

In this embodiment, the row redundancy circuit X-R is used.
DE is exemplarily shown as a representative. That is, the circuit X-RED includes a storage circuit for storing a defective address and an address comparison circuit. The stored defective address is compared with the internal address signal BXi output from the row address buffer RAB, and when they do not match, the signal XE is set to the high level and the signal XEB is set to the low level to enable the operation of the normal circuit. When the input internal address signal BXi matches the stored and defective address, the signal XE is set to low level to inhibit the defective word line selecting operation of the normal circuit, and the signal XE
A selection signal XRiB for selecting one spare word line by the selection circuit as shown in FIG.
Is output.

Although not shown in FIG. 5, a circuit similar to the above row system circuit is also provided in the column system, and when a memory access to a defective bit line is detected thereby, the defective bit by the column decoder YD is detected. A selection signal for stopping the line selection operation and replacing the spare bit line is formed instead.

The functions and effects obtained from the above-mentioned embodiment are as follows. That is, (1) By arranging the spare bit line or word line in substantially the central portion of the memory mat, the probability of occurrence of a defect in the spare word line or bit line is small, and the defective word line or bit line is used. It is possible to obtain the effect of reducing the probability of occurrence of defects when the line is switched to the spare word line or the bit line.

(2) By providing the same number of spare word lines on both sides of the word line with the twisted portion of the complementary bit line interposed, it is possible to balance the capacitance between the complementary bit lines and improve the operation margin. The effect that it can be achieved is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, when the spare word lines are arranged on both sides of the twisted portion of the complementary bit line in the same number as described above to balance the capacitance of the bit lines, the spare word lines may be different due to other layouts. Complementary bit lines may be arranged around the memory mat.

In FIG. 4, a similar memory array and a Y decoder may be provided and four memory arrays may constitute one dynamic RAM. Further, it is also possible to configure four memory arrays as one group and to provide four groups to configure one dynamic RAM. As described above, the actual memory array configuration of the dynamic RAM can take various embodiments.

As a semiconductor memory device having complementary bit lines, there is a static type RAM in addition to the folded bit line type dynamic RAM. Static type RA
Also in M, since the influence of the coupling between the bit lines can be reduced by providing the twist portion for every other complementary bit line, the same number of spare word lines are provided with the twist portion of the complementary bit line interposed therebetween. As a result, it is possible to improve the operation margin in the same manner, and at the same time, simplify the data scramble.

The present invention can be applied to various ROMs in addition to the dynamic RAM and static RAM having the complementary bit lines as described above. RAM or ROM is 1
In addition to one memory integrated circuit, it may be built in a digital integrated circuit such as a microcomputer.

[0043]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, by arranging the spare bit line or word line in the substantially central portion of the memory mat,
By utilizing the fact that the probability of failure occurrence in the spare word line or bit line is small, it is possible to reduce the failure occurrence probability when the defective word line or bit line is switched to the spare word line or bit line.

[Brief description of drawings]

FIG. 1 is a schematic pattern diagram showing one embodiment of a memory mat section of a dynamic RAM according to the present invention.

FIG. 2 is a circuit diagram showing an example of a spare word line selection circuit.

FIG. 3 is a timing chart showing an embodiment for explaining a word line selection operation.

FIG. 4 is a block diagram showing an embodiment of a memory array section and peripheral circuits in the dynamic RAM according to the present invention.

FIG. 5 is a block diagram showing an embodiment of an input / output interface section and a timing control circuit in the dynamic RAM according to the present invention.

[Explanation of symbols]

MAT0 to MAT7 ... Memory mat, MARY0, MA
RY1 ... Memory array, XD0 to XD7 ... Decoder circuit, WD0 to WD7 ... Word driver, SA01 to SA
67 ... Sense amplifier, YD ... Column decoder circuit, MA
TCTRL0 to MATCTRL3 ... Mat control circuit, T
G ... Timing control circuit, I / O ... Input / output circuit, RAB
... row address buffer, CAB ... column address buffer, AMX ... multiplexer, RFC ... refresh address counter circuit, XPD, YPD ... pre-coder circuit, X-DEC ... column system redundant circuit, XIB ... decoder circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yukie Hide Suzuki 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Hiroyuki Yoshida 2350 Kiura Miura, Inashiki-gun, Ibaraki Japan Texas Instruments Co., Ltd. In-house (72) Inventor Takashi Inui 2350 Kihara, Miura-mura, Inashiki-gun, Ibaraki Japan Textile Instruments Co., Ltd. (72) Inventor Shigeki Numaga 2350 Kihara, Miura-mura, Inashiki-gun, Ibaraki Nippon Textiles Instruments Co., Ltd.

Claims (3)

[Claims] 1. A semiconductor memory device comprising a spare bit line or word line arranged substantially in the center of a memory mat. 2. The bit line is composed of a pair of complementary bit lines, and a twisted portion and a twisted portion that are not provided in the central portion are alternately arranged. 2. The semiconductor memory device according to claim 1, wherein the same number of spare word lines are provided on both sides of the twist portion. 3. The semiconductor memory device according to claim 1, wherein a dynamic memory cell is arranged at an intersection of the bit line and the word line.