JPH09146788A - Logical emulation method and system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform the emulation regardless of the frequency of data which are transferred between an emulation controller and an emulator by programming an emulation model, a test bench, a queuing extension control circuit, and a programmable dividing circuit to a logical emulator. SOLUTION: An emulator 100 can equivalently obtain various circuits by programming the proper value to an array of internal storage elements. The emulator 100 also can program the arraying way of external inputs/outputs 410, 420 and the input/output attributes. Then the emulator 100 includes an emulation model 110, a test bench 120, a queuing extension control circuit 130 and a dividing circuit 140. The test data are permanently generated to perform the tests by emulation as long as a finite amount of data are previously secured to generate an emulation test pattern in the emulator 100.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic emulation method and system, and more particularly, to a controller for interpreting a wait extension signal for instructing to fix data on a transmission terminal for a period in which the signal is valid, The present invention relates to a logic emulation method and system for connecting a device (emulator) that realizes a variable logic circuit.

[0002]

2. Description of the Related Art FIG. 18 is a diagram for explaining a conventional logic emulation. The system shown in the figure is an emulator 10 having an emulation model 11,
The test device 20, the clock generator 40, and the controller 30 are included.

The emulator 10 has external terminals 12-16.
Is set. Here, the emulator 10 is a general-purpose logic device that can equivalently realize various logic circuits by setting (programming) appropriate values in an array of internal storage elements. The output can be performed electrically, and the arrangement method and input / output attributes can be programmed. The emulation model 11 is a logic circuit when programmed in the emulator 10.

The test apparatus 20 has a function to be connected to the outside of an actual LSI, and tests according to the operating speed and the number of terminals. The specifications of the test apparatus 20 are strongly related to the specifications of the emulation model 11, and correspond to the operating speed and the number of terminals.

The controller 30 fixes the potential of the terminal used for transmitting data. In the conventional logic emulation, a test device 20 corresponding to a function to be connected to the outside of an actual LSI is created in advance, the emulation model 11 is programmed in the emulator 10, and the terminal of the emulation model 11 is connected to the external terminal 12 of the emulator 10. , 13 and the terminals 12 and 13 are connected to the test apparatus 20.

[0006]

Therefore, if the emulation model changes frequently, the performance to be tested will change regardless of the operating speed condition and the number of terminals, and the test equipment must be recreated. The labor for that makes the emulation work less efficient.

Further, when the test apparatus is created as an entity different from the emulation model, it is necessary to adjust the clock for operating the emulation model and the clock for operating the test apparatus. Consider a case in which the data from the control device is transmitted to the test bench or the emulation model by connecting the emulation control device to the emulator.

While the existing system operates in units of a predetermined clock cycle, the test bench or emulation model has a problem that the complexity of the original logic circuit affects the situation of the program in the emulator. In addition, the frequency at which stable operation is possible varies depending on the complexity of the original logic circuit and the options in the middle of configuration. Also, the maximum operating frequency of the test bench or emulation model is usually significantly lower than the operating frequency of the controller.

In order to adjust the data from the control device at a frequency that matches the operating speed of the test bench or the emulation model, a waiting extension signal can be given to the control device, but the operation required for the waiting extension control circuit is required. The speed (fw) is usually not achievable with a test bench or emulation model. Also, in a certain test bench or emulation model, f
Although it was possible to operate at w, if the configuration is reconfigured due to modification of the logic circuit, it may become impossible to operate at an operation speed satisfying fw.

Therefore, when the data from the control unit is transmitted to the test bench or the emulation model, conventionally, the data is received without using the waiting extension signal of the control unit or the waiting extension signal is generated. It is necessary to provide a fixed circuit on the outside.

The present invention has been made in view of the above points, and a logic emulation method and system capable of performing emulation without being affected by the frequency of data exchanged between the emulation control device and the emulator. The purpose is to provide.

Still another object of the present invention is to maintain a stable phase of a clock signal between a test bench or an emulation model and a waiting extension control circuit, and to emulate a long time with high reliability. A possible logic emulation method and system.

[0013]

The present invention generates an emulation model, which is a logic circuit when a logic circuit is programmed in an emulator, and a test pattern to be given to the emulation model in order to confirm the operation of the emulation model. In addition, a test bench that stores the output of the emulation model in its own memory, and a waiting extension for instructing the control device to fix the data of the transmission terminal for the period when the signal is "valid". A waiting extension control circuit for generating a signal and a programmable frequency dividing circuit are programmed in a logic emulator, which has a communication output, a communication input, and a waiting control signal input, and is updated during a period when the waiting control signal input is "valid". It has a function to maintain the communication output that is made until the waiting control signal input becomes "invalid". , 該待 if control signal input is "valid"
In a logic emulation method that is performed by connecting a logic emulation control device having a function of storing a communication input at a time when the input changes from "invalid" to "invalid", the value of the input changes from "valid" to "invalid" in the waiting extension control circuit. In this case, the wait extension signal which is "invalid" over the cycle width of the clock signal separately provided and which is "valid" under other conditions is generated, and the output of the wait extension signal is set to the first of the logic emulator. The external terminal W is set, the input to the waiting extension control circuit is set to the second external terminal of the logic emulator, and the frequency divider circuit provides the emulation model, the waiting extension control circuit, and the clock signal provided to the test bench.
It is generated by dividing from one clock signal provided from the external terminal of the logic emulator, the division ratio is set to the third external terminal P of the logic emulator, and the test bench or emulation model updates the input externally. To output some of the signals that change from “valid” to “invalid” to the external terminals of the logic emulator, and set one of the external terminals to the second external terminal. , Some of the input terminals of the test bench or emulation model are set to the external terminals of the logic emulator, the communication output from the emulation controller is connected to the external terminals, and the output terminals of the test bench or emulation model are Some of them to the external terminals of the logic emulator, and the communication input to the emulation control device Connect to the terminal, connect the third external terminal P of the logic emulator to the wiring for setting the division ratio, and connect the first external terminal W of the logic emulator to the waiting extension signal input of the control device. A logic emulation method characterized by.

Further, according to the present invention, the frequency dividing circuit is provided with an output terminal K capable of setting a frequency dividing ratio, and the input terminal of the circuit for generating the waiting extension signal is connected to the output terminal K of the frequency dividing circuit. . Further, according to the present invention, the waiting extension control circuit voluntarily invalidates the waiting extension signal, and a terminal for instructing its cycle is provided.
Set to the fourth external terminal T of the logic emulator,
This is implemented by connecting a wire that gives a value to the external terminal T of.

Further, according to the present invention, the period elapsed from the time when the output terminal K finally changed from "valid" to "invalid",
When the period set as a cycle until the waiting extension signal is voluntarily set to "invalid" is exceeded, the waiting extension signal is voluntarily set to "invalid", and thereafter, the output terminal K is changed from "valid" to "invalid". Until the time becomes "", the waiting extension control circuit that voluntarily turns the waiting extension signal "invalid" with the set period as a cycle is used.

Further, according to the present invention, the waiting extension control circuit is provided with a terminal L, the terminal L is set as an external terminal of the logic emulator, and the waiting extension signal is voluntarily set while the value of the terminal L is "valid". By using the waiting extension control circuit that has the function of suppressing the operation of disabling, the signal that becomes "valid" during the period when the input is required to be stable in the emulation model is output to the outside of the logic emulator. The output is set to the terminal, and the external terminal is connected to the terminal L.

Further, according to the present invention, the waiting extension control circuit is provided with a terminal L in addition to the output terminal K, the terminal L is set as an external terminal of the logic emulator, and finally the value of the terminal L is "valid".
If the period that has elapsed after being "disabled" exceeds the period set as the cycle until the waiting extension signal is voluntarily set to "invalid", the waiting extension signal is voluntarily set to "invalid".
After that, inputting in the emulation model using the waiting extension control circuit that voluntarily turns the waiting signal to "invalid" with the set period as the cycle until the value of the terminal L changes from "valid" to "invalid". Is set to be output to the external terminal of the logic emulator during the period when it is required to be stable, and the external terminal of the logic emulator is connected to the terminal L.

The present invention generates an emulation model which is a logic circuit when a logic circuit is programmed in an emulator, and a test pattern to be given to the emulation model in order to confirm the operation of the emulation model, and the emulation model. A test bench that stores the output of its own in its own memory, and a wait extension that generates a wait extension signal to instruct the control unit to fix the data of the transmission terminal for the period when the signal is "valid". A logic emulator including means for programming a control circuit and a programmable frequency divider circuit in the logic emulator; and a communication output, a communication input, and a waiting control signal input, wherein the waiting control signal input is "valid" Be sure to update the communication output until the waiting control signal input becomes "invalid". Means for lifting, a logic emulation controller including means for storing a communication input of time 該待 focus control signal input changes from "valid" to "invalid",
In a logic emulation system including a clock generator that generates a clock, the waiting extension control circuit described above uses a clock signal provided by the clock generator when the input value changes from "valid" to "invalid". It is "invalid" over the cycle width, and under other conditions,
A means for generating a waiting extension signal which is "valid" and setting the output of the waiting extension signal to the first external terminal W of the logic emulator, and an input means for receiving an input from the second external terminal of the logic emulator. The above-mentioned frequency dividing circuit divides and generates a clock signal provided to the emulation model, the waiting extension control circuit, and the test bench from one clock signal provided from the external terminal of the logic emulator, and divides it. The frequency ratio is the third external terminal P of the logic emulator.
And an eleventh external terminal for outputting some of the signals changing from "valid" to "invalid" when the test bench or the emulation model externally requests input update. Output to one of the external terminals, and set one of the external terminals to the second external terminal,
Set some of the input terminals of the test bench or emulation model to the external terminals of the logic emulator, connect the communication output from the emulation control device to the external terminals, and connect the output terminals of the test bench or emulation model. Some of them are set to external terminals of the logic emulator, the communication input to the emulation control device is connected to the external terminals, and the wiring for setting the division ratio is connected to the third external terminal P of the logic emulator. And a connection means for connecting the first external terminal W of the control terminal to the waiting extension signal input of the control device.

In the logic emulation system of the present invention, the first external terminal W for setting the output of the waiting extension controller, the input of the waiting extension controller, and the test bench or the emulation model update the input. A second external terminal K for setting any of the output signals that change from “valid” to “invalid” when requesting to the outside, and a third external terminal P for setting the division ratio of the frequency dividing circuit. , A test bench or a fourth external terminal connected to either the input terminal of the emulation model and setting the output from the controller.

The frequency divider circuit of the above logic emulator has an output terminal K for setting a frequency division ratio as an input to the waiting extension controller. Further, the waiting extension control device of the logic emulator is voluntary on the basis of the instruction inputted via the fifth external terminal T for setting the instruction of the cycle for "invalidating" the waiting extension signal. Waiting extension signal is "invalid"
Including means to.

In the waiting extension control device for the logic emulator, the output terminal K is finally from "valid" to "invalid".
When the period that has elapsed from the time when it became a period exceeds the period set as the cycle until the waiting extension signal is "invalidated" voluntarily, the waiting extension signal is voluntarily made "invalid". , And thereafter, means for voluntarily making the waiting extension signal "invalid" with the set period as a cycle until the output terminal K changes from "valid" to "invalid".

Further, the waiting extension control device of the logic emulator suppresses the operation of voluntarily making the waiting extension signal "invalid" during the period in which the external terminal L and the external terminal L are "valid". And means for outputting to the external terminal of the logic emulator a signal that is "valid" during the period when the input is required to be stable in the emulation model, using the suppressing means.

The waiting extension control circuit of the logic emulator has a terminal L set as an external terminal of the logic emulator, which is set separately from the output terminal K in the signal control circuit,
When the period that has passed since the value of the terminal L was changed from "valid" to "invalid" exceeds the period set as the cycle until the waiting extension signal is "invalidated" voluntarily, The invalidation means for invalidating the waiting extension signal, and the invalidation means for generating the waiting extension signal which is valid during the period when the input is required to be stable in the emulation model are generated by the terminal. It has means for outputting to L.

As described above, in the present invention, the test bench is programmed in the emulator together with the emulation model having a function of supplying data to the emulation model of the emulator and temporarily storing the emulation result. As a result, the test bench and the emulation model will operate based on the same operating clock, and the frequency of data given to the emulation model and the frequency of data collected from the emulation model will differ from the operation frequency of the emulation model. It does not happen and therefore there is no need to adjust the operating clock.

Also, the waiting extension control circuit is programmed in the emulator by separating the emulation model and the operating clock. Since the waiting extension control circuit does not depend on the size or configuration of the emulation model, it can always operate at a constant speed even if it is combined with any emulation model or even if the emulation model is modified. It is possible to send a waiting extension control signal adapted to the operating speed to the control device connected to the.

Further, the frequency dividing circuit having a configuration in which the frequency dividing ratio can be changed after the configuration is programmed by separating the emulation model and the operating clock. Since the dividing ratio can be changed without configuration after the maximum operating frequency of the emulation model is known from the configuration result, the number of configuration steps can be reduced.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows the configuration of the logic emulation system of the present invention. The configuration of the logic emulation system shown in the figure includes an emulator 100, a control device 200, and a clock generation device 300.
The emulator 100 can equivalently realize various logic circuits by programming appropriate values in the array of internal storage elements. I / O to the device
The external input / output 410 and 420 can be electrically performed, and the arrangement method and input / output attributes can be programmed. The emulator 100 has an emulation model 110, a test bench 120, a waiting extension control circuit 130, and a frequency dividing circuit 140.

The emulation model 110 is a logic circuit when a logic circuit is programmed in the emulator 100. The test bench 120 generates a test pattern given to the emulation model 110 in order to confirm the operation of the emulation model 110, and
It has a function of storing the output (test result) of the emulation model 110 in its own memory.

The waiting extension control circuit 130 controls the transmission terminal over a period in which the signal is "valid" in the control device 200 having the function of fixing the potential of the terminal used for transmitting data. It is a circuit that generates a waiting extension signal for instructing the control device 200 to fix the data.

The frequency dividing circuit 140 includes the clock generator 30.
The clock signal provided from 0 is divided. Control device 2
00 has a function for inputting the emulation model 110 or the test bench 120.

The clock generator 300 generates a stable clock signal, determines the speed at which the emulator 100 operates, and outputs the clock signal to the emulation model 110, the waiting extension control circuit 130, and the frequency dividing circuit 14.
It is provided to 0. This clock signal is used by the emulator 10
It is generated by dividing the frequency of one clock signal provided through the external terminal 157 of 0.

Input / output terminals 151 to 151 of the emulator 100
Reference numerals 156, 160 to 162, 171, and 172 denote the external input / output and control device 200 of the emulation model 110 itself.
In addition to being used as a connection part with the test bench 120 or a program for connecting the emulation model 110 and the waiting extension control circuit 130, or for setting the frequency division ratio in the frequency division circuit 140, To do.

Next, the operation of the above system configuration will be described. The waiting extension control circuit 130, when the input value changes from “valid” to “invalid”, the clock generation device 300.
Is set to “invalid” over the cycle width of the clock signal provided by the device, and under other conditions, a waiting extension signal that is “valid” is generated, the waiting extension signal is set to the terminal W, and the external terminal 162 of the emulator 100 is set. Output.

The frequency divider circuit 140 supplies a clock signal to be supplied to the emulation model 110, the waiting extension control circuit 130, and the test bench 120 to the emulator 100.
It is generated by dividing the frequency of one clock signal provided from the external terminal 157. The terminal for setting the frequency division ratio of the frequency dividing circuit 140 is connected to the external terminal 172 of the emulator 100.

When the test bench 120 or the emulation model 110 requests external input update,
Some of the signals changing from “valid” to “invalid” are connected to some external terminals 151, ..., 15 of the emulator 100.
4 is connected, the output from the control device 200 is connected to the external terminal 160, and the division ratio is connected to the external terminals 171 and 172 of the emulator 100.
0 is connected, and the external terminal 162 of the emulator 100 is connected to the waiting extension signal input of the control device 200.

[0036]

The first to fourth embodiments of the present invention will be described below. The respective embodiments described below are different in the connection method between the waiting extension control circuit programmed in the emulator and the frequency dividing circuit, the test bench, or the emulation model.

[First Embodiment] A first embodiment of the present invention will be described with reference to FIG. In FIG. 1, the logic emulation system includes an emulator 100, a control device 200, and a clock generator 300.

The controller 200 functions to input data to the test bench 120 or the emulation model 110. The clock generator 300 generates a stable periodic signal and determines the speed at which the emulator 100 operates. The input / output terminal of the emulator 100 is used as a connection portion with the external input / output 410 of the emulation model 110 itself and the input / output of the control device 200, and also connects the test bench 120 or the emulation model 110 and the waiting extension control circuit 130. It is programmed so that it can be used for the purpose of setting the frequency division ratio in the frequency dividing circuit 140 or for the purpose of setting.

The waiting extension control circuit 130 and the frequency dividing circuit 140 programmed in the emulator 100, the test bench 120, or the emulation model 11
The connection method with 0 is a feature of this embodiment. The structure and order of operation will be described below.

The emulation model 110 is a program in which the design contents to be operated by emulation and to be tested are programmed in the emulator.
The test bench 120 is an emulation model 110.
In order to test, the test pattern data is generated and the test results are collected and stored.

FIG. 2 shows the configuration of the test bench of the first embodiment of the present invention. The test bench 120 shown in FIG.
Control register write unit 121, write control unit 122, test pattern memory 123, data format converter 124, pattern generation control unit 125, read control unit 126, data format converter 127, test result memory 128, and result storage control unit 129. It is composed of

The test bench 120 permanently generates a test pattern by reading the contents stored in the test pattern memory 123 by the pattern generation control unit 125 based on a specific rule. Further, the result storage control unit 129 observes some of the output values of the simulation model in a specific time domain combination, and stores the result in the test result memory 128.

The contents of the test pattern memory 123 are transferred to the emulation controller 20 via the write controller 122.
You can write from 0. Further, the content of the test result memory 128 can be read by the emulation control device 200 via the read control unit 126.

A data output terminal input of the control device 200 is given to the test bench 120 or the emulation model 110. The value of this data output terminal is
The period during which the value of the terminal W controlled by the waiting extension control circuit 130 is “valid” is fixed. Here, the terminal W
The value of is positive logic. That is, the logical value "1" means "valid",
A logical value of 0 indicates "invalid".

When the logical value input to the terminal K changes from "0" to "1", the waiting extension control circuit 130 outputs 1 after that.
Only during the clock period, the value of the output terminal W to the control device 200 is set to "0". As a result, the waiting extension signal of the control device 200 becomes “invalid”, and during that period, the control device 200
Update the value of the data output terminal. The period during which the waiting extension signal is "invalid" is equal to the cycle of the clock signal applied to the terminal C of the waiting extension control circuit 130.

If the speed at which the waiting extension control circuit 130 can operate is too slow, the waiting extension signal cannot be changed so as to properly fix the data from the control device 200. However, in the present invention, the waiting extension control circuit 130
As will be described later, can be operated at a sufficient operation speed for the normal control device 200 in order to realize with a simple logical configuration. On the contrary, if the invalid period of the waiting extension signal is too short for the control device 200, it can be dealt with by setting the signal period of the clock generation device 300 longer.

The frequency dividing circuit 140 generates a periodic signal for determining the operating speed to the test bench 120 or the emulation model 110, and supplies it from the terminal M. In general, how fast the test bench 120 or emulation model 110 can operate is analyzed after configuration. Therefore, the frequency dividing circuit 140 is provided with a terminal P that can be connected from an external terminal of the emulator 100.
The frequency division ratio to the clock terminal M can be set.

As a result, even when the operable frequency of the test bench 120 or the emulation model 110 changes due to the modification or change of the logic circuit, the method of the present invention can be used. Also, as mentioned above,
Even when the clock signal cycle of the clock generator 300 is changed to the operating speed of the controller 200, the test bench 12
The frequency division ratio can be corrected by wiring so as to give 0 or an appropriate clock to the emulation model 110.

The logical value input to the terminal K of the waiting extension control circuit 130 is output from the test bench 120 or the emulation model 110. Emulator 10
Since 0 is programmed with various variable logic circuits, the wait extension signal is “invalidated” to the control device 200.
It is generally not possible to determine the conditions under which

Therefore, the terminal K of the waiting extension control circuit 130
Is given from the outside of the emulator 100, a plurality of signals are output to the external terminals in advance according to the design contents of the logic circuit, and the required terminals are selected externally and given to the terminal K. As a result, it is possible to change the conditions for giving the data from the control device 200 to the test bench 120 or the emulation model, for example, the frequency of updating the data, without performing time-consuming configuration.

FIG. 3 shows the configuration of the waiting extension control circuit of the first embodiment of the present invention. Waiting extension control circuit 1 shown in FIG.
30 is composed of registers R1 and R2 and a logic element N. The waiting extension control circuit 130 is a single-phase synchronizing circuit that operates using the signal from the clock generator 300 applied to its terminal C as a clock. While the logical value given to the terminal K is "0", the output value of the register R1 and the output value of the register R2 are both "0" no matter how many times the clock signal arrives at the terminal C. At this time, the output of the logic element N is "1", which is the value of the terminal W. FIG. 4 shows a truth table of the circuit.

When the logical value given to the terminal K changes from "0" to "1", the output value of the left register (R1) of the terminal K changes when the first clock signal arrives at the terminal C. The value becomes "1". In the register (R2) on the right side, the output value becomes "0" which is the value before change in the register R1. As a result, the output value of the logic element N becomes "0". Since the change in the value of the terminal K is much slower than the change in the value of the terminal C, the period in which the terminal K is “1” continues for a while, but the next clock signal is input to the terminal C.
When the output of the logic element N reaches "1", the value of the terminal W remains "1" until the value of the terminal K changes from "0" to "1" again.

In this way, the terminal W becomes "0" no matter how long the change in the logical value applied to the terminal K of the waiting extension control circuit 130 is compared with the clock signal applied to the terminal C. The period, that is, the period in which the waiting extension signal is "invalid" is equal to the cycle of the clock signal applied to the terminal C.

Further, since the waiting extension control circuit 130 has such a simple structure, even when programmed in the emulator 100, it can be operated sufficiently fast so as to match the operating speed of the control device 200. Next, the frequency dividing circuit 140 will be described. FIG. 5 shows the first of the present invention.
2 shows a configuration of a frequency dividing circuit according to the embodiment. A parameter for determining the frequency division ratio is given to the terminal P. This is a bundled terminal composed of a plurality of terminals, and the input / output terminals 171 and 1 of the emulator shown by the name of division ratio connection in FIG.
It is programmed to be placed at 72. When the connection having the potential of “1” or “0” as a logical value is performed on the division ratio connection, the logical value of the value of the corresponding terminal in the terminals P becomes “1” or “0”. The operation clock of the frequency dividing circuit 140 is applied to the terminal C. As shown in FIG. 1, the clock generator 300 is connected and a periodic signal is input. The frequency dividing circuit divides the cycle of the signal at the terminal C based on the setting at the terminal P and outputs it to the terminal M. The terminal M outputs a periodic signal whose frequency is divided to that of the terminal C.

Of the plurality of terminals P, half is connected to the terminal QI of the shift register 142, and the other half is connected to the terminal QR of the comparison section 141. In FIG. 5, the left half is connected to QR and the right half is connected to QI. Comparison unit 14
1 refers to the logical value array given to the terminal QR and the logical value array obtained from the connection with the terminal QS of the shift register, and refers to the arrangement position where the logical value of the terminal QR is "1". When all the logical values of the corresponding terminals QS are equal to the negated logical value of the terminal V, the logical value "1" is output to the terminal S, and the logical value "0" is output otherwise. Is what you are doing.

When the logical value given to the terminal L is "1", the shift register 142 internally holds the array of the values of the terminal QI when the clock signal first arrives at the terminal C thereafter. If the logical value given to the terminal L is “0”, then when the clock signal first arrives at the terminal C, the rightmost 1-bit value of the array of currently held values is set. It is discarded and the other currently held array of values is moved to the right by 1 bit, and the leftmost 1 bit is held as the negated logical value of the leftmost 1 bit of the terminal QI. The terminal M has a shift register 142
Of the array of logical values held inside, the rightmost 1-bit value is always output.

FIG. 6 shows an example of the operation of the frequency dividing circuit according to the first embodiment of the present invention. This figure shows an example in which the number of bits of the shift register 142 is 8 and the frequency is divided by 8. Set the value of terminal P to “1
111111000001111 "." 00001111 "is set as the array of the QI portion of the terminal P, and" 1111111 "is set as the array of the QR portion.
0 "is set. The contents held in the shift register 142 and the values of the respective terminals are moved row by row in the table of FIG. 6 every time the clock signal arrives at the terminal C. As can be seen from the value of the terminal M on the 16th to 16th rows,
When the terminal P is set in this way, a signal having a cycle that is eight times the cycle of the clock signal applied to the terminal C, that is, a signal divided into 1/8, appears at the terminal M. From line 17 onward, the process from line 9 onward is repeated.

With the number of bits of the shift register kept at 8,
Assuming that the value of the terminal P is “11111000000000111”, “00001111” is set as the logical value array of the QI portion of the terminal P, and “11111000” is set as the array of the QR portion. In this case, the frequency division by 6 is performed. Further, a larger frequency division ratio can be obtained by increasing the number of bits of the shift register.

[Second Embodiment] Next, a second embodiment of the present invention will be described. FIG. 7 shows the configuration of the logic emulation system of the second embodiment of the present invention. In the figure,
The same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. The system shown in the figure is different from that in FIG. 1 in the terminal configuration of the frequency dividing circuit 140 and the test bench 120.

In this embodiment, in order to extend the waiting time to the control device 200 so that the data from the control device 200 is updated at a cycle of a constant ratio to the operation clock of the test bench 120 or the emulation model 110,
The input to the terminal K of the waiting extension control circuit 130 is divided by the frequency dividing circuit 1
It is given by the output of the terminal K of 40.

Consider a case where the input is acquired at a cycle of a constant ratio R with respect to the operation clock of the test bench 120 or the emulation model 110 itself. Test bench 120 or emulation model 11
The frequency dividing circuit 14 is connected to the terminal K so that the signal becomes valid at the cycle of the ratio R for the signal of the terminal M where 0 is the operating clock.
0 outputs the signal.

At this time, if the terminal K of the frequency dividing circuit 140 is connected to the terminal K of the waiting extension control circuit 130, the control device 200 supplies data to the test bench 120 or the emulation model 110. The waiting time can be extended so that the operation clock of the emulation model 110 itself is updated at a cycle of a constant ratio R.

[Third Embodiment] Next, a third embodiment of the present invention will be described. FIG. 8 shows the configuration of the logic emulation system of the third embodiment of the present invention. In the figure, the same components as those in FIGS. 1 and 7 are designated by the same reference numerals, and the description thereof will be omitted. The configuration of FIG. 7 differs from the configuration of FIG. 7 in that the terminals of the waiting extension control circuit 130 and the spontaneous cancellation period connection 440 are connected.

In the present embodiment, the waiting extension control circuit 130 is provided with a spontaneous canceling function of the waiting extension signal so that the waiting extension period does not become longer than a predetermined time. In the third embodiment, the control device 200 is restricted so that the period in which the waiting extension signal is "valid" does not continue for a certain time or longer. That is, in the third embodiment, if the waiting extension signal is "valid" for a certain period of time or more, the control device 2 is inhibited from spontaneous operation.
00 and the test bench 120 or the emulation model 110 that requires data from the control device 200 only rarely, the method of the present invention can be applied.

FIG. 9 shows the structure of a waiting extension control circuit in the third embodiment of the present invention. The waiting extension control circuit 130 shown in the figure comprises a counter, registers R1 and R2, a logic element N, and a gate O. The counter in the figure operates by using the signal given to the terminal C as a clock,
Each time the number of clocks corresponding to the value given to the terminal arrives, the logical value "1" is output to the terminal S only for one cycle of the clock signal at the terminal C. At other times, the logical value "0" is output to the terminal S.

The gate O in the figure outputs the logical sum of the value of the terminal K and the value of the terminal S of the counter. FIG.
A truth table of the gate O is shown in FIG. The operation of the waiting extension control circuit 130 of FIG. 9 is the same as that of FIG. 3 for the terminal K, but when the terminal S of the counter changes from “0” to “1”, the terminal K is As in the case of changing from "0" to "1", the waiting extension signal of the terminal W is set to the logical value "0" which is "invalid" only for the period of one cycle of the clock signal of the terminal C. Since the value of the terminal K of the control circuit 130 is given from the test bench 120 or the emulation model 110, an appropriate value is set to the terminal T even when the waiting extension signal remains "valid" for a considerably long period. Therefore, the waiting extension time can be restricted so as not to exceed a certain time.

FIG. 11 shows another configuration example of the waiting extension control circuit in the third embodiment of the present invention. In the figure,
Test bench 120 or emulation model 1
When 10 continuously reads data from the control device 200, the read cycle is T of the cycle of the clock signal at the terminal C.
Under a condition that is shorter than twice (T is a value given to the terminal T), the terminal S of the counter does not cause the terminal W of the waiting extension control circuit 130 to be "invalid".

When the test bench 120 or the emulation model 110 continuously reads data from the control device 200, the data from the control device 200 is also continuously updated at a specific cycle. If the counter automatically voluntarily “disables” the waiting, the test bench 120 or the emulation model 110 may update data that may not be received from the control device 200.
Test bench 120 or emulation model 1
For 10, this data is missing. The configuration of the waiting extension control circuit 130 shown in FIG. 11 in the third embodiment is for preventing data loss caused by this mechanism.

In FIG. 11, the terminal K is internally connected to the terminal R of the counter. The counter has a terminal R, but when the value of this terminal R becomes "1", the terminal C
When the clock signal arrives at, the value inside the counter is reset. The operation of the counter after the internal value is once reset is that the value of the terminal S remains unchanged while the clock signal arrives at the terminal C (T-2) times after the value of the terminal R returns to "0". It remains “0”. When the (T-1) th clock arrives, the value of the terminal S becomes "1", and T
When the second clock arrives, the value of the terminal S remains "0" while the clock signal again arrives at the terminal C (T-2) times thereafter, and this is repeated thereafter.

Therefore, once the value of the terminal K becomes "1", as a result, the waiting extension control circuit 130 invalidates the waiting extension control signal, but in parallel, the terminal S of the counter is connected.
Spontaneous invalidation of the waiting extension signal by means of the clock signal at the terminal C is suppressed over a period of (T-1) times.

As a result, when the test bench 120 or the emulation model 110 continuously receives data from the control device 200 at intervals shorter than the period of (T-1) times, the test bench 120 or the emulation model 110. Can be prevented from updating data that may not have been received from the controller 200.

[Fourth Embodiment] Next, a fourth embodiment of the present invention will be described. FIG. 12 shows the configuration of the logic emulation system according to the fourth embodiment of the present invention. In the logic emulation system shown in the figure, a terminal L is provided separately from the terminal K of the waiting extension control circuit 130 in the above-described embodiment, and, for example, a notice signal for reading data is output from the terminal L of the test bench 120 or the emulation model 110. By giving the signal, the waiting extension control circuit 130 is prevented from voluntarily invalidating the waiting extension signal during the period.

Even if the value of the terminal K is "0", it is necessary to spontaneously "disable" the waiting extension signal.
Alternatively, since the emulation model 110 can be suppressed, the present invention is also applied to the test bench 120 or the emulation model 110 that requires not to update the output from the control device 200 for a relatively long time according to the present embodiment. be able to.

FIG. 13 shows the structure of a waiting extension control circuit according to the fourth embodiment of the present invention. The waiting extension control circuit 130 shown in the figure comprises a counter, registers R1 and R2, a logic element N, a gate O, and a logic element G. Terminal L
While the value of is "1", the logic element G prevents the waiting extension signal from being "invalid" even if the terminal S of the counter is "1".

FIG. 14 shows a truth table of the logic element G in the fourth embodiment of the present invention. Further, while the value of the terminal L is "1", "1" is given to the terminal H of the counter so that the content of the counter does not change even if the clock signal arrives at the terminal C.

The counter has a terminal H, and when the logical value given to this terminal is "0", the content of the counter itself is updated once when the clock signal arrives at the terminal C thereafter. Every time the content is updated T times, "1" is output to the terminal S for the time of one cycle of the clock signal arriving at the terminal C, and "0" is output to the terminal S during the other periods. By the way, if the value given to the terminal H is "1", the counter does not update the contents even if the clock signal arrives at the terminal C. Therefore, the timing at which "1" is output to the terminal S next is postponed only during the period when "1" was applied to the terminal H.

Using the above waiting extension control circuit 130, the test bench 120 or the simulation model 1
If the logic value of "1" is programmed in one of the outputs of the emulator 100 for a period requiring the output from the control device 200 not to be updated, this terminal is used for reading data. By connecting to the terminal L of the waiting extension control circuit 130 as a notice signal, independently of setting the value of the terminal K to "1",
Depending on the value of the terminal L, it is possible to suppress the waiting extension control circuit 130 from spontaneously invalidating the waiting extension signal, and the control device 200 can be operated for a relatively long period.
The present invention can also be applied to the test bench 120 or the emulation model 110 that requires that the output from the device is not updated.

FIG. 15 shows another configuration example of the waiting extension control circuit of the fourth embodiment of the present invention. In the figure, terminal R
When the value of is "1", the value of the terminal R of the counter whose content is reset is given from the terminal L of the waiting extension control circuit 130. While the value of the terminal L is "1", the value of the terminal R of the counter is also "1".
Since "0" remains output, the fourth embodiment described above can be configured even by using the waiting extension control circuit 130 of this configuration.

While the value of the terminal L returns from "1" to "0" and thereafter the clock arrives at the terminal C (T-1) times, "0" is still output to the terminal S. , It is suppressed that the waiting extension signal is voluntarily made "invalid". It should be noted that the present invention is not limited to the above-described embodiment, but can be variously modified and applied within the scope of the claims.

[0080]

As described above, according to the present invention, a finite amount of data is given in advance in order to generate an emulation test pattern inside the emulator by programming the emulation model and the test bench together in the emulator. By doing so, it becomes possible to generate test data permanently and perform a test by emulation. As a result, it is possible to perform emulation without being influenced by the frequency of data exchanged between the emulation control device and the emulator.

When the control device having the waiting extension signal detection function is connected to the test bench or the connection for supplying data to the emulation model, according to the present invention, the data is sent back to the control device to check the contents. There is no need to perform any procedures other than the data transfer itself, such as Further, the external circuit for generating the waiting extension signal does not impair the versatility of the emulator, and data can be given from the control device to the test bench or the emulation model.

Further, according to the present invention, since the clock supplied to the test bench or the emulation model is generated from the clock for operating the waiting extension circuit by the frequency dividing circuit, one clock generator provided outside the emulator is sufficient. Therefore, it is not necessary to separately provide the test bench or the emulation model and the waiting extension control circuit. As a result, the phase of the clock signal is kept stable between the test bench or emulation model and the waiting extension control circuit, and long-time emulation can be performed with high reliability.

Further, according to the present invention, all devices required for emulation except the emulation control device and the clock generator are programmed in the emulator. Since the connection between the emulator and the other two devices does not depend on the model of the logic emulator, the applicable range is wide.

In addition, the waiting extension control circuit and the frequency dividing circuit are
Since it does not affect the function of the test bench or emulation model, it is not emulation but FPGA (Fiel
Even if the logic circuit is actually implemented by using a d Programmable Gate Array) to configure a device that receives data from the control device, the operating speed of the device is not sufficient for the operating speed of the control device. If so, in order to control the waiting extension signal of the control device, the waiting extension control circuit and the frequency dividing circuit can be left as they are, and the entire device can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a logic emulation system of the present invention.

FIG. 2 is a configuration diagram of a test bench according to a first embodiment of the present invention.

FIG. 3 is a configuration diagram of a waiting extension control circuit according to the first embodiment of the present invention.

FIG. 4 is a truth table of a logic element N of the waiting extension control circuit according to the first embodiment of the present invention.

FIG. 5 is a configuration diagram of a frequency dividing circuit according to a first embodiment of the present invention.

FIG. 6 is a diagram showing an example of the operation of the frequency dividing circuit of the first exemplary embodiment of the present invention.

FIG. 7 is a configuration diagram of a logic emulation system according to a second embodiment of the present invention.

FIG. 8 is a configuration diagram of a logic emulation system according to a third embodiment of the present invention.

FIG. 9 is a configuration diagram of a waiting extension control circuit according to a third embodiment of the present invention.

FIG. 10 is a truth table of the logic element N of the waiting extension control circuit according to the third embodiment of the present invention.

FIG. 11 is a diagram showing another configuration example of the waiting extension control circuit in the third exemplary embodiment of the present invention.

FIG. 12 is a configuration diagram of a logic emulation system according to a fourth embodiment of the present invention.

FIG. 13 is a configuration diagram of a waiting extension control circuit according to a fourth embodiment of the present invention.

FIG. 14 is a truth table of the logic element G according to the fourth embodiment of the present invention.

FIG. 15 is a diagram showing another configuration example of the waiting extension control circuit of the fourth exemplary embodiment of the present invention.

FIG. 16 is a diagram for explaining conventional logic emulation.

[Explanation of symbols]

 100 emulator 110 emulation model 120 test bench 121 control register write unit 122 write control unit 123 test pattern memory 124 data format converter 125 pattern generation control unit 126 read control unit 127 data format conversion unit 128 test result memory 129 result storage control unit 130 Wait extension control circuit 140 Frequency divider circuit 141 Comparison section 142 Shift register 151-156 External input / output terminal 157 Clock terminal 160-162 Control device terminal 171,172 Frequency division ratio connection terminal 182,183 Spontaneous release cycle connection terminal 200 Control device 300 Clock generator 410, 420 External I / O connection 430 Frequency division ratio connection 440 Spontaneous release cycle connection

Claims (13)

[Claims] 1. An emulation model which is a logic circuit when a logic circuit is programmed in an emulator and an operation of the emulation model are confirmed.
A test bench that generates a test pattern to be given to the emulation model and stores the output of the emulation model in its own memory, and a control device that fixes the data of the transmission terminal for a period in which the signal is valid. A waiting extension control circuit for generating a waiting extension signal for instructing and a programmable frequency divider circuit are programmed in a logic emulator and have a communication output, a communication input, and a waiting control signal input, and the waiting control signal input is valid. A logic emulation having a function to maintain the communication output updated during a certain period until the waiting control signal input is invalidated, and a function to store the communication input at the time when the waiting control signal input changes from valid to invalid A logic emulation method for connecting a control device, comprising: Then, when the input value changes from valid to invalid, it is invalidated over the cycle width of the clock signal provided separately, and under other conditions, a valid waiting extension signal is generated and the waiting extension signal is output. Is set to the first external terminal W of the logic emulator, the input to the waiting extension control circuit is set to the second external terminal of the logic emulator, and the frequency dividing circuit is configured to emulate the emulation model and the waiting extension control. A clock signal provided to the circuit and the test bench is generated by dividing one clock signal provided from the external terminal of the logic emulator, and the division ratio is set to the third external terminal P of the logic emulator. However, some of the signals that change from valid to invalid when the test bench or the emulation model externally requests an input update are described above. Logic emulator to output to an external terminal, one of the external terminals is set to the second external terminal, and some of the test bench or the input terminals of the emulation model are connected to the logic terminal. Set to the external terminal of the emulator, connect the communication output from the emulation control device to the external terminal, set some of the output terminals of the test bench or the emulation model to the external terminal of the logic emulator, A communication input to the emulation control device is connected to the external terminal, a connection for setting a frequency division ratio is connected to the third external terminal P of the logic emulator, and the first external terminal W of the logic emulator is connected. Is implemented by connecting to the waiting extension signal input of the control device. Method. 2. The frequency division circuit is provided with an output terminal K capable of setting a frequency division ratio, and the input terminal of the waiting extension control circuit is connected to the output terminal K of the frequency division circuit. Logic emulation method. 3. The waiting extension control circuit voluntarily invalidates the waiting extension signal and sets a terminal for instructing its cycle to a fourth external terminal T of the logic emulator, and the fourth external terminal T is set. 2. The logic emulation method according to claim 1, which is carried out by connecting a wire for giving a value to. 4. When the period elapsed from the time when the output terminal K is finally enabled to the disabled state exceeds the period set as a cycle until the waiting extension signal is automatically disabled, Using the waiting extension control circuit, which voluntarily invalidates the waiting extension signal, and thereafter voluntarily invalidates the waiting extension signal with a set period as a cycle until the output terminal K becomes valid to invalid. The logic emulation method according to claim 1, which is implemented. 5. The waiting extension control circuit is provided with a terminal L, the terminal L is set as an external terminal of the logic emulator, and the waiting extension signal is voluntarily disabled while the value of the terminal L is valid. By using a waiting extension control circuit having a function of suppressing the operation, the signal that is valid during the period when the input is required to be stable in the emulation model is output to the external terminal of the logic emulator. And the external terminal is connected to the terminal L.
The described logic emulation method. 6. The output terminal K to the waiting extension control circuit.
In addition to the above, a terminal L is provided, the terminal L is set as an external terminal of the logic emulator, and the waiting extension signal is invalidated voluntarily for the period that has elapsed since the value of the terminal L was finally changed from valid to invalid. When the period set as the period until is exceeded, the waiting extension signal is invalidated spontaneously, and thereafter, until the value of the terminal L is changed from valid to invalid, the set period is voluntarily set. A waiting extension control circuit for invalidating the waiting signal is used to output a signal that is valid during a period in which the input is required to be stable in the emulation model, to an external terminal of the logic emulator. 4. The logic emulation method according to claim 3, wherein the logic emulation is performed by setting and connecting an external terminal of the logic emulator to the terminal L. 7. An emulation model, which is a logic circuit when a logic circuit is programmed in an emulator, and an operation of the emulation model are confirmed.
A test bench that generates a test pattern to be given to the emulation model and stores the output of the emulation model in its own memory, and a control device that fixes the data of the transmission terminal for a period in which the signal is valid. A wait extension control circuit for generating a wait extension signal for instructing, a logic emulator including means for programming a programmable frequency divider circuit in the logic emulator, a communication output, a communication input, and a wait control signal input, Means for maintaining the communication output updated during the period when the waiting control signal input is valid until the waiting control signal input becomes invalid,
In a logic emulation system comprising a logic emulation control device including means for storing a communication input at a time when the wait control signal input changes from valid to invalid, and a clock generation device for generating a clock, the wait extension control circuit comprises: When the input value changes from valid to invalid, it is invalidated over the cycle width of the clock signal provided from the clock generation device, and under other conditions, a valid waiting extension signal is generated, and the waiting extension signal is generated. Of the output of the logic emulator to the first external terminal W of the logic emulator, and input means for receiving the input from the second external terminal of the logic emulator, the frequency divider circuit, the emulation model and the The clock signal provided to the waiting extension control circuit and the test bench is output from outside the logic emulator. Means for dividing and generating from one clock signal provided from the terminal, and setting the dividing ratio to the third external terminal P of the logic emulator; and the test bench or the emulation model for updating the input. When requesting to the outside, it is set to output to a first external terminal for outputting some of the signals that change from valid to invalid, and one of the external terminals is set to the second external terminal. Setting, setting some of the input terminals of the test bench or the emulation model to external terminals of the logic emulator, connecting the communication output from the emulation control device to the external terminals, By setting some of the output terminals of the emulation model as external terminals of the logic emulator, A communication input to the control unit is connected to the external terminal, a wire for setting a division ratio is connected to the third external terminal P of the logic emulator, and the first external terminal W of the logic emulator is connected. A logic emulation system having a connecting means for connecting to a waiting extension signal input of the control device. 8. The connecting means updates a first external terminal W for setting an output of the waiting extension control device, an input of the waiting extension control device, and an input of the test bench or the emulation model. A second external terminal K for setting any of output signals that change from valid to invalid when requesting externally, a third external terminal P for setting a frequency division ratio of the frequency dividing circuit, 8. The logic emulation system according to claim 7, further comprising a fourth external terminal which is connected to either a test bench or an input terminal of an emulation model and sets an output from the control device. 9. The logic emulation system according to claim 7, wherein the frequency dividing circuit has an output terminal K for setting a frequency dividing ratio as an input to the waiting extension controller. 10. The waiting extension control device voluntarily waits based on the instruction input via a fifth external terminal T for setting an instruction of a cycle for invalidating the waiting extension signal. The logic emulation system of claim 7, including means for disabling the extension signal. 11. The waiting extension control device is set such that a period elapsed from when the output terminal K was last enabled to invalid is set as a cycle until the waiting extension signal is automatically disabled. A means for voluntarily invalidating the waiting extension signal when exceeding the period, and thereafter, voluntarily invalidating the waiting extension signal with the set period as a cycle until the output terminal K is invalidated. 8. The logic emulation system according to claim 7, further comprising: 12. The emulation model, wherein the waiting extension controller includes an external terminal L, a suppressing unit that suppresses an operation of voluntarily invalidating the waiting extension signal while the external terminal L is valid. 8. The logic emulation system according to claim 7, further comprising means for outputting to the external terminal of the logic emulator a signal which is valid during a period when the input is required to be stable. 13. The waiting extension control circuit, as an external terminal of the logic emulator, a terminal L set separately from the output terminal K in a signal control circuit, and finally, a value of the terminal L is changed from valid to invalid. In the emulation model, an invalidating unit that voluntarily invalidates the waiting extension signal when the period that has elapsed since the time exceeds the period set as the period until the waiting extension signal is voluntarily invalidated. 8. The logic emulation system according to claim 7, further comprising means for generating, by using the invalidating means, a waiting extension signal which becomes valid during a period in which the input is required to be stable, and outputs the signal to the terminal L.