JPH09146551A - Waveform memory sound source device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable accessing a waveform memory efficiently for every channel by required quantity when required by buffering address and waveform sample to an address storage means and a sample storage means. SOLUTION: A waveform read-out interpolation circuit 102 generates successively read-out addresses of a waveform memory 208. Read-out addresses are values that specified read-out pitches are successively totaled from the start of a specified read-out section. In this master sound source 207 M, the waveform read-out interpolation circuit 102 is provided with a waveform buffer buffering a waveform sample, only a required number of waveform samples (waveform data) are read out from the waveform memory 208 for every channel, and the number of times of accessing waveform memories in each channel are variable. Read-out timing of a waveform sample can be adjusted properly, and continuous access can be performed corresponding to the speed of a waveform memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tone generator for generating and outputting digital tone waveform data.
The present invention relates to a waveform memory read type sound source device in which two sound sources can share one waveform memory.

[0002]

2. Description of the Related Art Conventionally, there has been known a waveform memory sound source which simultaneously generates musical tones for a plurality of channels by time division channel operation. In such a sound source, a tone generation operation of each channel is performed in a time slot of each channel obtained by equally dividing one sampling period. Similarly, access to the waveform memory is a time-division channel operation, and for each channel, access is performed a fixed number of times in a time slot corresponding to the channel.

Further, the sound source of the waveform memory reading system is provided with an interpolation circuit, and performs an interpolation calculation using several consecutive samples (waveform data) for each channel.
There is one that obtains musical tone waveform data for a point. In addition, the interpolation circuit has a sample buffer,
There is a waveform memory sound source that enables high-order interpolation calculation. This is because the waveform data read from the waveform memory is stored in the sample buffer, and when the waveform memory is being read, if there is little advance in the address, the waveform data stored in the sample buffer and the newly read The interpolation is performed by using the waveform data.

[0004]

As described above, in the waveform memory sound source which simultaneously generates musical tones for a plurality of channels in the time-division channel operation, the waveform memory access is fixed at a fixed number of times for each channel. Has been. In general, according to the waveform read speed (F number) of each channel, etc., and for each sampling cycle,
Although the required number of times of accessing the waveform memory is different, the conventional technique has not done so, and the limited operation speed (accessible number) of the waveform memory has not been effectively utilized.

In the method using the sample buffer, the data in the sample buffer can be effectively used for interpolation when the advance of the address is small, but when the advance of the address is large, all necessary waveform data must be read out. However, the interpolation order may be lowered (for example, 4-point interpolation is changed to 2-point interpolation).

According to the present invention, in a sound source of a waveform memory reading system which simultaneously generates musical tones for a plurality of channels by time division channel operation, the waveform memory can be efficiently accessed by each channel when needed. The purpose is to do so.

[0007]

The invention according to claim 1 of the present invention is a waveform memory sound source device for generating musical sounds of a plurality of channels by operating in a time-divisional manner in a plurality of channels at a predetermined sampling cycle. Of the waveform memory, which can be accessed a predetermined number of times within the processing time of one channel within the predetermined sampling period, address storage means for storing the address of each channel, and A waveform sample storage means for storing a waveform sample, an address creating means for creating an address of each channel prior to reading the waveform memory, and storing the address in the address storage means, and an advance amount of the address of each channel. On the basis of,
Access number calculating means for calculating the number of times the waveform memory is accessed for each channel; and accumulating means for accumulating the access numbers calculated by the access number calculating means for a predetermined number of channels and outputting the accumulated number. Determination means for determining whether or not access for the accumulated number of times is possible within an access period corresponding to the predetermined number of channels, and a time width of the access period is set to a normal length or a shortened length. When the access period switching means for switching and the determining means determine that it is possible, based on the address of each channel stored in the address storage means, the access period for each access frequency of each channel calculated by the access count calculating means The waveform memory of each channel that is read by continuously accessing the waveform memory in First access means for storing in the sample memory means, second access means for accessing the waveform memory during the free time generated by shortening the access period by the access period switching means, and the waveform sample storage means. And a musical tone generating means for generating a musical tone for each sampling period of each channel based on the waveform sample of each channel stored in the above.

The second access means in claim 1 is a waveform memory sound source in the embodiment of the invention described later, but it is not necessarily a waveform memory sound source. For example, a sampling circuit for writing a new waveform in the waveform memory, a CPU for editing and processing the waveform stored in the waveform memory, and a DMAC for transferring the waveform data to the waveform memory.
(Direct memory access control circuit), refreshing when the waveform memory has a DRAM configuration, or the like may be used.

According to a second aspect of the present invention, by operating in a time-divisional manner for a plurality of channels at a predetermined sampling period,
In a waveform memory sound source device for generating musical tones of a plurality of channels, wherein a waveform memory is connected and a waveform memory which can be accessed a predetermined number of times within a processing time of one channel within the predetermined sampling period is connected, An address storage unit for storing the address of each channel, a waveform sample storage unit for storing the waveform sample of each channel, an address of each channel is created prior to reading the waveform memory, and the address storage unit stores the address. Means for storing in the means, an access number calculating means for calculating the number of times of accessing the waveform memory for each channel based on the amount of advance of the address of each channel, and an access number calculating means for a predetermined number of channels. Accumulate the number of accesses calculated in
The accumulating means for outputting the number of times of accumulation and the time width of the access period set corresponding to the predetermined number of channels are the same as the time width when the time division channel timing is processed for the predetermined number of channels. A width, or a time width shorter than that, based on the input instruction signal, and an access period switching means, and whether or not access for the accumulated number of times is possible within the access period. When the determination means and the determination means determine that it is possible, the access count of each channel calculated by the access count calculation means is calculated based on the address of each channel stored in the address storage means within the access period. To access the waveform memory continuously,
Based on the first access means for storing the read-out waveform sample of each channel in the waveform sample storage means and the waveform sample of each channel stored in the waveform sample storage means, a musical sound for each sampling period of each channel is generated. And a musical sound generating means.

According to a third aspect of the present invention, in the second aspect, a mode designation signal for designating whether to operate in the first mode or the second mode is input,
In the waveform memory sound source in which the first mode is designated, the access period switching means sets the access period to a shortened time width, and a synchronization signal is sent to another waveform memory tone generator device in which the second mode is designated. In the waveform memory sound source in which the second mode is designated, the access period switching means shortens the access period, and the first mode is outputted from the designated waveform memory sound source. Input sync signal,
The processing timing is adjusted so that the access period in the waveform memory tone generator in which the second mode is designated is arranged in a section other than the access period in the waveform memory tone generator in which the first mode is designated. It was done.

The invention described in claims 2 and 3 focuses on the configuration of a one-chip sound source in an embodiment of the invention described later. It is made clear that the access period switching means changes the time width of the section in which the process B is executed according to the 2-chip instruction or the 1-chip instruction in the embodiment of the invention. Further, the first mode is a mode indicating that the master sound source is instructed in the embodiment of the invention, and the first mode is a mode indicating that the slave sound source is instructed.

According to the invention described in claim 4, by operating in a time-divisional manner for a plurality of channels at a predetermined sampling period,
In a waveform memory sound source device for generating musical tones of a plurality of channels, a first sound source for generating musical tones of a plurality of channels, a second sound source for generating musical tones of another plurality of channels, a musical sound from the first sound source and the Mixing means for mixing and outputting musical tones from two sound sources, and a waveform memory for storing waveform samples, the waveform memory being accessible a predetermined number of times within a processing time for one channel within the predetermined sampling period. The first sound source includes a first address storage unit for storing an address of each channel, and a first address storage unit for storing a waveform sample of each channel.
Prior to reading the waveform sample storage means and the waveform memory, the address of each channel is created, and the first
First address creating means for storing in the address storing means; first access number calculating means for calculating the number of times of accessing the waveform memory for each channel based on the advance amount of the address of each channel; and the first address storing On the basis of the address of each channel stored in the means, the waveform memory is continuously accessed by the number of access times of each channel calculated by the first access number calculating means, and the waveform sample of each channel read A first access means for storing in one waveform sample storage means, and a tone generation means for generating a tone for each sampling period of each channel based on the waveform sample of each channel stored in the first waveform sample storage means. The second sound source has a second address for storing the address of each channel. Storage means, second waveform sample storage means for storing the waveform sample of each channel, and an address for each channel is created prior to reading of the waveform memory and stored in the second address storage means Address creation means, second access count calculation means for calculating the access count of the waveform memory for each channel based on the advance amount of the address of each channel, and each of the channels stored in the second address storage means. Based on the address, the waveform memory is continuously accessed for each access count of each channel calculated by the second access count calculation means, and the read waveform samples of each channel are stored in the second waveform sample storage means. Second access means and each channel stored in the second waveform sample storage means A tone generating means for generating a tone for each sampling period of each channel based on a waveform sample, and utilizing the idle time of access of the waveform memory by the first accessing means of the first sound source, the second tone The timing is adjusted so that the waveform memory is accessed by the second access means of the sound source.

In the waveform memory sound source device according to claim 4, the first access means of the first sound source divides the predetermined sampling period into m (m is an integer of 2 or more) intervals for each interval. , The plurality of channels to be processed in the section are continuously accessed in the waveform memory in a section having a time width shorter than that of the section, and the second access means of the second sound source sets the predetermined sampling cycle to m ( m is an integer greater than or equal to 2), the waveform memory is continuously accessed for each section divided into sections having a time width shorter than the section for a plurality of channels to be processed in the section. The waveform memory access by the first access means of the sound source and the waveform memory access by the second access means of the second sound source are alternately performed. It may be so that the timing adjustment has been made to divide. It is desirable that the sampling period be equally divided into the first half and the second half.

The waveform memory tone generator according to claim 4, further comprising third access means for performing at least one of reading and writing of the waveform memory,
The third access means may access the waveform memory by utilizing the extra time after the access of the waveform memory by the first access means. Third
The access means is, for example, refresh when the waveform memory has a DRAM configuration, access by the CPU for editing and processing the waveform stored in the waveform memory, access from a sampling circuit for writing a new waveform in the waveform memory, or the waveform. DM for transferring waveform data to memory
Access from the AC is performed.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2A shows an overall block configuration of an electronic musical instrument to which the sound source device according to the embodiment of the present invention is applied. FIG. 2B shows a schematic configuration of the sound source unit of this embodiment. FIG. 1 shows a detailed block configuration of the sound source unit of this embodiment. 1 and 2, the same numbers indicate the same things.

First, the overall construction of this electronic musical instrument will be described with reference to FIG. This electronic musical instrument has a keyboard 20
1, a display unit 202, a switch group (SW) 203, a central processing unit (CPU) 204, a read only memory (RO
M) 205, random access memory (RAM) 20
6, sound source unit 207, waveform memory 208, digital-analog converter (DAC) 210, sound system (S
S) 211, an external storage device 212, and a bus 213. Keyboard 201, display unit 202, switch group 2
03, the CPU 204, the ROM 205, the RAM 206, the sound source unit 207, and the external storage device 212 are the bus 213.
Are connected to each other.

The keyboard 201 is a keyboard provided with a plurality of keys for a user to perform a performance operation. The display unit 202 is provided on the panel of the electronic musical instrument and displays various kinds of information. The switch group 203 is provided on the panel,
By operating this, the user can give various instructions to the electronic musical instrument. The CPU 204 controls the operation of the entire electronic musical instrument. In particular, during a normal performance, the operation of the keyboard 201 is detected, and the sound source unit 207 is instructed to sound according to the operation. ROM 205 is a CPU
Stores programs executed by the sound generator (such as a sound source control program for controlling the sound source unit 207) and various constant data. The RAM 206 is used as a work register or the like. The external storage device 212 includes a DRAM, which will be described later.
Waveform data and the like to be loaded into the configured waveform memory 208 are stored.

As shown in FIG. 2B, the sound source section 207 comprises a master sound source 207M, a slave sound source 207S, and a mixer 220. The master sound source 207M and the slave sound source 207S have the same internal configuration and share one waveform memory. That is, the master sound source 207
M and the slave sound source 207S are respectively CPU2
In response to the instruction 04, the waveform data is read from the waveform memory 208, processed such as interpolation, envelope addition, channel accumulation, and effect addition, and output as tone waveform data. The musical tone waveform data output from the sound sources 207M and 207S are mixed by the mixer 220, and DA
It is converted into an analog signal by C210 and is emitted by the sound system 211.

The waveform memory 208 is composed of a DRAM (dynamic RAM). Waveform memory 208
Stores waveform sample data sampled at a predetermined rate. One waveform sample is in a 16-bit uncompressed format, and an address is assigned to each waveform sample. That is, one waveform sample can be read by one access. The waveform sample is read from the external storage device 212 prior to the pronunciation of the musical sound, and the waveform memory 2 is read.
08, but especially in the sound source of this embodiment,
Since it is possible to use an empty time slot that has not been used when performing the operation of generating musical tones of a plurality of channels for another purpose, the waveform sample is stored from the external storage device 212 using the empty time slot. It may be read and stored in the waveform memory 208.

Next, the sound source unit 207 will be described in detail. In FIG. 1, the master sound source 20 in the sound source unit 207
7M is a control register 101, a waveform reading interpolation circuit 1
02, volume change control unit 105, channel (ch) accumulator 106, effect circuit 107, refresh counter 10
8, a CPU access control unit 109, a selector 110, a selector 111, a system clock generation unit 112, and a channel (ch) counter 113.

The control register 101 is a control register for storing designation information (command and parameter information for the master sound source 207M) sent from the CPU 204. The CPU 204 sets predetermined designation information in the control register 101 and issues a sounding start instruction. The designation information to be set includes designation information such as an assigned channel, a memory read pitch (frequency number), a memory read section, an envelope, and an effect coefficient.

Upon receiving a sound generation start instruction for a certain channel, the master sound source 207M starts the operation of generating a musical tone waveform. First, the waveform read interpolation circuit 102 sequentially generates read addresses of the waveform memory 208. The read address is a value obtained by sequentially accumulating the designated read pitch from the beginning of the designated read section. Particularly, in this master sound source 207M, a waveform buffer for buffering waveform samples is provided in the waveform reading interpolation circuit 102, and only the required number of waveform samples (waveform data) is read from the waveform memory 208 for each channel. Therefore, the number of waveform memory accesses in each channel can be changed.
Therefore, the waveform read interpolation circuit 102 is designed to successively output the addresses of the waveform memory according to the number of times of access required for each channel, at a timing different from the time division channel timing.

An empty time slot is obtained by outputting the address from the waveform read interpolation circuit 102 at a timing different from the time division channel timing. The refresh counter 108 and the CPU access control unit 109 are for refreshing the waveform memory 208 or accessing the waveform memory 208 from the CPU 204 in this empty time slot. The selectors 110 and 111 have the refresh counter 108 in an empty time slot.
The CPU access control unit 109 is controlled to be connected to the waveform memory 208.

The read address generated by the waveform read interpolation circuit 102 is input to the waveform memory 208 via the selector 110, whereby the waveform sample is read from the waveform memory 208. Waveform readout interpolation circuit 102
Receives the waveform samples via selector 111,
Store in internal waveform buffer. The waveform read interpolation circuit 102 has an interpolation circuit therein, and the interpolation circuit reads the waveform sample of each channel stored in the waveform buffer and performs the interpolation process (basically performing 6-point interpolation, If the number of access times for each channel is insufficient and waveform data for 6 points cannot be secured, the interpolation order is reduced to 4-point or 2-point interpolation).

The volume change control circuit 105 adds an envelope to the tone waveform data of each channel. The channel accumulator 106 accumulates the tone waveform data of each channel. The effect circuit 107 adds various effects to the result of channel accumulation. The tone waveform data to which the effect is added is the mixer 22 shown in FIG.
At 0, the tone waveform data from the slave sound source 207S is mixed. The tone waveform data from the mixer 220 is DAC
It is input to 210, converted into an analog signal, and emitted by the sound system 211.

This master sound source 207M operates on 32 channels in time division. The system clock 112 supplies a control clock signal Φ serving as a reference signal for performing a time division operation to each unit in the master sound source 207M. The channel counter 113 counts the channel count value CHC for performing the time-divisional channel operation (specifically, repeating 0 to 31), and the master sound source 2
Supply to each block in 07M.

The slave sound source 207S has exactly the same configuration as the master sound source 207M, and the master sound source 207M
It operates in parallel with. However, the master sound source 20
The synchronization signal 114 from the 7M system clock 112 is input to the slave sound source 207S, and the slave sound source 207S
Controls all processing according to this synchronization signal so as to be executed at a timing later than the master sound source 207M by a quarter sampling period. This timing will be described later in detail. The slave sound source 207S also operates on 32 channels in time division, but the master sound source 207M
Performs the processing of channels 0 to 31, and the slave sound source 207S performs the processing of channels 32 to 63 in parallel therewith. The tone generator 207 as a whole can generate musical tones for 64 channels.

FIG. 3 shows a block configuration of the waveform read interpolation circuit 102 in the master sound source 207M. The waveform reading circuit 102 in the slave sound source 207S has the same configuration. The waveform read interpolation circuit 102 includes a processing A arithmetic circuit 301, an address RAM (ARAM) 302, an accumulator (ACC) 303, a control RAM 304, a processing B arithmetic circuit 305, an interpolation circuit 306, a waveform buffer 307,
And a capture circuit 308.

The waveform read interpolation circuit 102 roughly performs four processes: process A, process B, fetching process, and interpolation process. The processing A arithmetic circuit 301
Execute The process A is a process of mainly creating the address of each channel according to the time division channel timing. The address of each channel is ARAM3
02 is held. The process B arithmetic circuit 305 executes the process B. In the process B, the address WMA is stored in the waveform memory 20 at a timing different from the time division channel timing.
This is a process for sending the data to the destination 8. Capture circuit 308
Performs import processing. The fetching process is a process of fetching the waveform sample read according to the address sent to the waveform memory 208 in the process B and writing the waveform sample in the waveform buffer 307 for each channel. The interpolation circuit 306 performs interpolation processing. The interpolation processing is performed by the waveform buffer 30 according to the time division channel timing.
In this process, the waveform samples of the respective channels are read from 7, and interpolation is performed to generate and output interpolated samples.
These four processes will be described in detail later. The interpolated sample output from the interpolation circuit 306 is input to the volume change control circuit 105 in FIG.

FIG. 4 shows the configuration of the control RAM 304 shown in FIG. As will be described later in detail, in the process A, in parallel with the creation of the address of each channel, a process of obtaining the required number of samples to be read for each channel and storing it in the control RAM 304 is performed. Therefore, the control RAM 304
A plurality of areas for storing the channel number and the number of samples to be read in that channel are prepared and configured. A write pointer and a read pointer are provided in the waveform read interpolation circuit 102 to control the number of required samples to be read in each channel.
When writing to 304 (process A), the write pointer is advanced, and when reading the channel number and the number of samples from the control RAM 304 and sending the read address for the channel (process B), the read pointer is advanced. The control RAM 304 is designed to be used in a ring shape, and the write or read pointer is controlled by the control R 304.
When the one end of the AM 304 is reached, the position of the next pointer becomes the other end of the control RAM 304. Further, writing and reading are performed so that the position pointed by the read pointer follows the position pointed by the write pointer, but it is assumed that the size of the area is ensured so that the write pointer does not overtake the read pointer. Similar to the accumulator ACC, the write pointer and the read pointer are provided separately for the first half processing and the second half processing. When simply referred to as the write pointer and the read pointer, the first half processing indicates the one for the first half processing, and the second half processing indicates the one for the second half processing. In addition to the configuration shown in FIG. 4, an address may correspond to each channel one by one, and the required number of samples may be written there.

FIG. 5 shows a memory map of the ARAM 302 shown in FIG. The ARAM 302 is an area used to create an address of each channel in the process A. A
The RAM 302 has 32 channels (channels 0 to 31 for the master sound source and channels 32 to 63 for the slave sound source).
Channel) for each channel, and the current address value of each channel is stored in these areas. The area of each channel is composed of an address upper ADH and an address lower ADL. The size of each of the ADH and ADL areas is 16 bits. A 32-bit address value that is a combination of the upper address ADH and the lower address ADL is divided into an address integer part and an address decimal part. The address integer part corresponds to the address of the waveform memory 208. That is, the waveform sample of the waveform memory 208 corresponds to 1 value corresponding to one value of the address integer part.
Exist. The address decimal part indicates a finer unit, and is information used in interpolation processing using some waveform samples. The address integer part has 23 bits, and the address decimal part has 9 bits.

FIG. 6 shows the configuration of the waveform buffer 307 of FIG. The waveform buffer 307 has 6 channels for each channel.
It consists of one sample storage area. The six sample storage areas are used in a ring shape. That is, a pointer is provided for each channel, and when writing a sample, the sample is written at the position indicated by the pointer and the pointer is advanced by one.
For example, in the case of the i-th channel in FIG. 6, the pointer advances in the order of sample 1 → 2 → 3 → 4 → 5 → 6 → 1 → 2 → .... Since FIG. 6 shows the waveform buffer of the waveform reading interpolation circuit 102 of the master sound source 207M, the 0th to 31st
A sample storage area for a channel is shown. Similarly, the waveform buffer of the waveform readout interpolation circuit of the slave sound source 207S is composed of sample storage areas of the 32nd to 63rd channels.

Next, the four processes executed by the waveform read interpolation circuit 102 will be described in detail. First, we explain the timing of executing these processes, and then
Details of each process will be described.

FIG. 7 shows the waveform read interpolation circuit 1 for each of the master sound source 207M and the slave sound source 207S.
The processing timings of processing A, processing B, capture processing, and interpolation processing performed in 02 are shown. Master sound source 207M
Each processing section is divided into the first half and the latter half, and the first half performs the processing of channels 0 to 15, and the latter half performs the processing of channels 16 to 31. Similarly, the interval of each process in the slave sound source 207S is divided into the first half and the second half, and the third half is divided in the first half.
2 to 47 channels are processed, and in the latter half, the 48th to
The 63rd channel is processed. Further, the processing timing of the slave sound source 207S is delayed by 1/4 sampling cycle as compared with the processing timing of the master sound source 207M.

The process B first half section 702 for performing the process B of the 0th to 15th channels of the master sound source is started immediately after the end of the process A first half section 701 for performing the process A of the channel. The 16th to 3rd master sound sources
Processing B second half section 706 for performing processing B of one channel
Is the latter half section 7 of the process A for performing the process A of the channel.
It will start immediately after the end of 05. The timing relationship between the first half and second half sections 712 and 716 of the slave sound source process B and the first half and second half sections 711 and 715 of the process A is the same. Processing B first half and second half section 70
2, 706, 712 and 716 each have a time width of 1/4 of one sampling cycle. Therefore, as for the process B, the first half process B process of the 0th to 15th channels of the master sound source → the first half process B process of the 32nd to 47th channels of the slave sound source → the second half process B of the 16th to 31st channels of the master sound source Process → Slave sound source 48th to 6th
Process B of the third channel, process B of the second half, and ... Process B of the master sound source and the slave sound source are alternately executed in this order.

Since the fetching process is performed in accordance with the address sending timing of the process B, the fetching process is similarly performed in the first half of the fetching of the master tone generator on the 0th to 15th channels → the 32nd of the slave tone generators.
The first half of the process of capturing the 47th channel → the latter half of the process of capturing the 16th to 31st channels of the master sound source → the latter half of the capturing of the 48th to 63rd channels of the slave sound source → ... in this order It is executed alternately.

FIG. 8 shows the state of the channel during the first half processing of the master sound source 207M of FIG. “Processing A” in FIG.
The first half ch ”is a section 70 in which the first half processing of the process A in FIG.
The state of the channel in 1 is shown. The “process B first half channel” of FIG. 8 is a section 702 in which the process B first half process of FIG. 7 is performed.
Shows the state of the channel in. The “first half channel for fetching” in FIG. 8 is a section 70 in which the first half channel for fetching in FIG. 7 is performed.
The state of the channel in 3 is shown. “First half channel of interpolation” in FIG. 8 shows the state of the channel in the section 704 in which the first half process of interpolation in FIG. 7 is performed. FIG. 8 shows the master sound source 20.
The channel state in the first half processing of 7M is shown, but the second half processing of the master sound source 207M, slave sound source 2
The same applies to the first half and second half of 07S. Note that, in FIG. 8, the timings of the respective channels are vertically aligned and aligned, but in reality, the timing of each process is shown in FIG.
It is misaligned as shown in.

As can be seen from FIG. 7 and FIG.
The interpolation processing is performed for each channel in order according to the time division channel timing obtained by equally dividing one sampling period. On the other hand, the process B and the fetching process are performed at a timing independent of the time division channel timing. Specifically, the process B and the fetching process can perform the process B and the fetching process for four accesses in a time width of performing the process for one channel at the time division channel timing. further,
The process B and the fetching process are designed so that the channels that need to be accessed are continuously processed in a left-justified manner regardless of the time division channel timing.

For example, in FIG. 7 and FIG.
In the first half section 701, the processing A arithmetic circuit 301
Addresses of the respective channels are created in order according to the time division channel timing for the 0th to 15th channels. At the end of this section 701, addresses related to channels 0 to 15 have already been set in the ARAM 302.

Next, in the first half 702 of the process B, the process B arithmetic circuit 305 sets one address of the 0th channel and the address of the second channel at a timing different from the time division channel timing (FIG. 8). Three, fifth
0 to 0 for one channel address, etc.
The 15th channel address is being sent out. The time width of the section for sending out one address is ¼ of the time width of the section for processing one channel at the time division channel timing. The number of addresses sent on each channel is different because the waveform buffer 30
This is because the past waveform samples are held in 7 and it is sufficient to read only the required number of waveform samples for each channel, or there is a channel that does not need to sound and does not need to send out an address.

Here (FIG. 8), the 0th channel has 1 sample, the 2nd channel has 3 samples, and the 5th channel has 5 samples.
Channel 1 shows the case where it is necessary to read from the waveform memory of 1 sample and channel 7 shows the case where it is necessary to read from the waveform memory. The other channels are channels that are not sounding or that can generate musical tones only with the samples that have already been read and stored in the waveform buffer 307. Note that a channel that is not sounding is a channel whose volume level has been lowered, such as EG.
The control is performed so as not to use the access timing of the waveform memory in.

In the first half section 703 of the acquisition, the acquisition circuit 308 acquires the waveform sample read from the waveform memory 208 in accordance with the address sending timing of the first section 702 of the process B. The fetched waveform sample is written in the waveform buffer 307.

In the first half section 704 of the interpolation, the interpolation circuit 306 performs the interpolation processing on the 0th to 15th channels by using the data of the sample RAM by the time division channel timing. At the time of performing interpolation for a certain channel, the waveform sample of the channel required for performing the interpolation is prepared in the sample RAM.

As described above, the musical tone waveform data of the 0th to 15th channels are generated. The same applies to the 16th to 31st channels processed using the latter half section. The same applies to the processing timing in the first half and the second half of the slave sound source. Particularly, since the waveform memory 208 is shared by the master sound source and the slave sound source, the process B
(Address sending to waveform memory) and acquisition processing (acquisition of waveform sample from waveform memory) are shown in FIG.
The timing is adjusted so that the master sound source and the slave sound source are alternately performed as shown in.

The process B and the fetch process in the process B arithmetic circuit 305 are performed at a timing different from the time division channel timing, so that an empty time slot appears. In the sections 702 and 703 of FIG. 8, “-c
"h" indicates an empty time slot that is not used for sample reading of any channel. This empty time slot section can be used arbitrarily. In the present embodiment, the refresh counter 108 of FIG. 1 refreshes the waveform memory 208 or the CPU access control unit 109 accesses the waveform memory 208 during the empty time slot.

Next, the waveform read interpolation circuit 102 of FIG.
The four processes according to will be described in detail in (1) to (4) below.

(1) Process A Process A executed by the arithmetic circuit 301 will be described in detail. When an instruction to start the generation of a musical sound is given to a certain channel, the processing A arithmetic circuit 301 starts execution of processing A relating to that channel. Processing A
Is executed at time division channel timing as described in FIGS. First, in the first time slot of the relevant channel (immediately after the rise of note-on), the processing A
The arithmetic circuit 301 is an ARAM corresponding to the channel.
Address storage area of 302 (FIG. 5) (ADH and ADL)
Is initialized. The initial value is the start address of the waveform data to be read, and the CPU 204 controls the control register 101.
Specify via. In subsequent time slots of the channel, the processing A arithmetic circuit 301 adds the pitch PITCH, which is the advance value (frequency number) of the address of the channel, to the current address value of the address storage area of the ARAM 302 corresponding to the channel. To do.
The addition result is stored in the address storage area of the original ARAM 302. The pitch PITCH is designated by the CPU 204 via the control register 101.

In this addition, specifically, the pitch PITCH is added to the address fraction part of the current address value of the channel, and the value overflowing higher than the number of bits of the address fraction part of the addition result is added to the current address value. This is done by adding to the integer part of the address. This overflow value is the number of waveform samples to be newly read. This is because the waveform read interpolation circuit 102 holds the waveform samples read up to that time in the waveform buffer 307, and the overflow value is the advance amount of the read address on the waveform memory.

FIG. 8 described above shows a case where the overflow value is 1 for the 0th channel, 3 for the 2nd channel, 1 for the 5th channel, and 2 for the 7th channel. The other channels are channels that are not sounding or have an overflow value of 0.

The waveform data on the waveform memory 208 is composed of an attack section and a loop section that follows it.
The access of the waveform sample is started from the beginning of the attack portion, and when the reading of the attack portion is completed, the loop portion is entered.
Thereafter, the waveform samples of the loop section are repeatedly read as necessary. Therefore, when the current address value reaches the end position of the loop section, it is necessary to return the current address value to the vicinity of the beginning of the loop section. The process A arithmetic circuit 301 is also performing a process of returning such an address to the vicinity of the beginning of the loop part during the process of creating the above-mentioned address.

As described above, the pitch (frequency number) is accumulated in the current address on the ARAM 302 in the time slot of the channel to obtain the sequential address of the channel.

In the process A, in addition to the process of creating the address of each channel described above, the write pointer pointing to the write position in the control RAM 304 is advanced by 1 to determine the required number of samples for each channel to the control RAM 304 (FIG. 4).
Is stored at the position indicated by the write pointer. The required number of samples for each channel is equal to the overflow value above the number of bits of the address fractional part in the addition result obtained by adding the pitch fraction PITCH to the address fractional part of the current address value. Is obtained and stored in the control RAM 304 together with the channel number.

Further, in the process A, in addition to the process of creating the address of each channel and storing the required number of samples for each channel, the number of waveform memory accesses required for each predetermined plurality of channels (in this embodiment, the number of samples is sampled). The number and the number of accesses are the same). Specifically, in the process A arithmetic circuit 301 of the waveform reading interpolation circuit 102 in the master sound source 207M,
The number of necessary samples to be read for these channels is accumulated in parallel with the address creation of the 15th channel (first half processing), and these channels are created in parallel with the address creation of the 16th to 31st channels (second half processing). Accumulate the required number of samples to read for. In addition, the waveform read interpolation circuit 1 in the slave sound source 207S
In the processing A arithmetic circuit 301 of 02, the number of necessary samples to be read for these channels is accumulated in parallel with the address creation (first half processing) of channels 32 to 47, and the addresses of channels 48 to 63 are added. In parallel with the creation (second half processing), the required number of samples to be read for these channels is accumulated.

An accumulator (ACC) 303 is an accumulator for performing this accumulation. In each of the master and slave sound sources 207M and 207S, since the first half processing and the second half processing are separately performed for accumulation,
The accumulator (ACC) 303 is actually composed of two accumulators, a first half accumulator and a second half accumulator. The accumulator (ACC) 303 simply refers to the first half accumulator in the first half processing and the second half accumulator in the second half processing.

Specifically, the accumulation process is performed as follows. First, the accumulator (ACC) 303 is initialized (cleared to zero) at the start of the first half process and the second half process. After that, the required number of samples (that is, the number of accesses) is accumulated in the accumulator (ACC) 303 until the last channel of the first half processing and the last half processing. The required number of samples to read for each channel is known when writing to the control RAM 304.

Further, in the process A, it is judged whether or not the access count cumulative value, which is the result of the accumulation as described above, exceeds the maximum accessible number in the first half section or the second half section of the process B in which the access is actually executed. , Determine the number of accesses and the interpolation order for each channel. In this embodiment, the maximum accessible number is 32. As described with reference to FIG. 8, the time width of the section in which one address is sent out in the process B is 1/4 of the time width of the section in which the processing for one channel is performed at the time division channel timing. This is because 32 accesses are possible in each of the latter half sections. Therefore, the accumulator ACC
If the accumulated access count value of does not exceed 32, all the sample numbers of each channel in the first half or the latter half written in the control RAM 304 can be accessed. Therefore, the access number of each channel and the interpolation order are determined according to the sample number. To do. In this case, it means that 6-point interpolation can be performed on all 16 channels in the first half or the second half. On the other hand, the accumulated access count value of the accumulator ACC is 32.
If it exceeds the above, it is not possible to access all the sample numbers of each channel written in the control RAM 304, so the access frequency of any channel is reduced and the interpolation order is lowered. As a method of deciding a channel for reducing the number of accesses, for example, the following methods and are available.

The number of accesses is reduced from one end in the order of channels. At that time, the number of accesses is reduced from the channel having the lower volume level. In this way, the influence on the musical sound is small. The volume level of each channel is known from the envelope value.

In this embodiment, basically, 6-point interpolation is performed on each channel, but when reducing the number of accesses, it is reduced to 4-point or 2-point interpolation so that at least 2-point interpolation can be performed. The number of samples shall be secured. Therefore, the number of times of access is not reduced to such an extent that two-point interpolation cannot be performed (in the worst case, access to each channel is secured twice. Therefore, in each processing B, there are 16 channels × 2 = 32 access slots).

FIG. 10 shows a specific example (including an example where the number of times of access is not reduced) in the present embodiment. FIG.
In (a) to (h), the advance amount is the advance amount (the same value as the overflow value described above) of the waveform memory address (specifically, the address integer part of the ARAM 302), and the number of samples required to be read in each channel. That is.
A downward arrow ↓ indicates a convenient reference position (a sample position where reading has been completed in the previous processing B of the same channel) for indicating the address advance amount. ×, ○, and ●
Indicates one sample of waveform data. The  indicates a sample already existing in the waveform buffer 307, and the ◯ indicates a sample to be read.

FIG. 10A shows the case where the address advance amount is 0. Since the samples for 6 points necessary for the 6-point interpolation exist in the waveform buffer 307, new reading is unnecessary and the number of accesses is 0. Naturally, the number of accesses is not reduced.

FIG. 10B shows the case where the advance amount of the address is 1. Five of the required six samples are already present in the waveform buffer 307, so only one sample is newly read. Therefore, it is necessary to access once. In this case, the number of accesses is not reduced.

FIG. 10C shows the case where the address advance amount is 2. Since four of the required six samples are already present in the waveform buffer 307, two new samples are read out. It is necessary to access twice. In this case, when the number of accesses is reduced, FIG.
As described on the lower side, the interpolation order is reduced from 6 points to 4 points, and the number of accesses is reduced by newly reading out one sample required for 4-point interpolation.

FIG. 10D shows the case where the advance amount of the address is 3. Since 3 of the required 6 samples are already present in the waveform buffer 307, 3 samples are newly read. The number of accesses is 3 times. In this case, when reducing the number of accesses, FIG.
As described below, the interpolation order is reduced from 6 points to 4 points or 2 points, and the number of accesses is reduced by newly reading 2 or 1 sample required for 4 point or 2 point interpolation.

FIG. 10E shows the case where the advance amount of the address is 4. Since two of the required six samples are already present in the waveform buffer 307, four samples are newly read. The number of times of access is 4 times. In this case, when the number of accesses is reduced, FIG.
As described below, the interpolation order is reduced from 6 points to 4 points or 2 points, and the number of accesses is reduced by newly reading out 3 or 2 samples required for 4-point or 2-point interpolation.

FIG. 10 (f) shows a case in which the address advance amount is 5. Since one point out of the required six points of samples already exists in the waveform buffer 307, five samples are newly read. The number of times of access is 5 times. In this case, when the number of accesses is reduced, FIG.
As described below, the interpolation order is reduced from 6 points to 4 points or 2 points, and 4 or 2 samples required for 4 point or 2 point interpolation are newly read to reduce the number of accesses.

FIG. 10G shows the case where the amount of advance of the address is 6. Required 6 samples are waveform buffer 3
Since it does not exist in 07, all 6 samples are read out. It is necessary to access 6 times. In this case, when the number of accesses is reduced, the interpolation order is reduced from 6 points to 4 points or 2 points as described in the lower part of FIG. Alternatively, the number of accesses is reduced by newly reading two samples.
The case where the amount of advance in FIG. 10 (h) is 7 is also the same as in FIG. 10 (g).

(2) Next, the process B executed by the process B arithmetic circuit 305 will be described in detail. Processing B operation circuit 3
Reference numeral 05 designates a process B, that is, an address, in the waveform memory 208 at a timing different from the time division channel timing.
The process of sending out to is performed. As described with reference to FIG. 8, four accesses (reading of four samples) are possible within the time per channel of the time division channel timing. The waveform memory access process of the process B has no relation to the process of the process A according to the time-division channel timing, and is sequentially and continuously performed for each channel that needs to be read. The channels and the number of samples that need to be read have been determined in the above-mentioned processing A. Further, as described with reference to FIG. 7, when the process B is performed for a certain channel, the process A for the relevant channel has already been executed, and the address value of the relevant channel is ARAM30.
It is set to 2.

The address sending process will be described. First, it is determined whether or not the value of the read pointer that indicates the read position in the control RAM 304 shown in FIG. 4 matches the value of the write pointer at the end of the first half or the second half of the process A for the channel. For example, when the process B of the channel is a process in the first half section 702 of the process B in FIG. 7, the value of the read pointer is compared with the value of the write pointer at the end of the first half section 701 of the process A. . If they match, it means that there are no more samples to be read in the section of the process B, so the process of the access surplus time described later is performed.

When the value of the read pointer does not match the value of the write pointer, the read pointer is advanced by 1 and the channel number and the sample number pointed to by the read pointer are read from the control RAM 304. And
Addresses related to the channel number corresponding to the number of samples are sent to the waveform memory 208. Specifically, ARA
The integer part of the current address of the channel is read from M302, a plurality of offsets for sequentially accessing the required number of samples are added, and the address reference value WA is further added (the address created in the process A is a relative address). Therefore, the address reference value is added to convert to an absolute address), and the final read address WM
A is sent to the waveform memory 208. The address sending timing has been described with reference to FIGS. FIG.
The offset of each access timing is 0 for the 0th channel, -2 for the first time of the second channel, -2 for the second time, 0 for the third time, and 1 for the fifth channel.
The first time is -1, the second time is 0, etc.
The sample corresponding to is surely read out. As described above, the addresses are continuously sent out while advancing the read pointer. When the value of the read pointer matches the value of the write pointer, the address sending process ends.

As described with reference to FIGS. 7 and 8, since the address sending processing is performed at a timing different from the time division channel timing, an empty time slot appears as an access extra time. Therefore, after the address sending processing, under the control of the processing B arithmetic circuit 305, the remaining time is used to refresh the waveform memory 208 by the refresh counter 108 in FIG. 1 or the waveform by the CPU access control unit 109. Access processing to the memory 208 is performed. When there is no more time to access, the process ends.

(3) Next, the capture processing executed by the capture circuit 308 will be described. Capture circuit 308
Is the address W sent from the processing B arithmetic circuit 305.
The waveform sample read by the MA is fetched and written in the waveform buffer 307. As a result of the acquisition, basically, 6 samples for each channel are prepared in the waveform buffer 307. However, if there is a channel in which the interpolation order is reduced to 4-point or 2-point interpolation in the process A, the samples necessary for the interpolation are prepared in the waveform buffer 307 for the channel.

(4) Next, the interpolation processing executed by the interpolation circuit 306 will be described in detail. The interpolation circuit 306 performs interpolation processing for each channel in order according to the time division channel timing. The interpolation process for one channel is as follows.

First, 6 samples of the channel are sequentially read from the waveform buffer 307. Then, each sample is multiplied by a predetermined interpolation coefficient and accumulated. The interpolation coefficient by which each sample is multiplied is the address fractional part F of the channel.
Determine based on RAC. Address decimal part FRAC
Is input from the ARAM 302 via the processing B arithmetic circuit 305. As described above, the interpolated musical tone waveform data is generated and output. For the channels whose interpolation order is reduced from 6 points to 4 points or 2 points by reducing the number of times of accessing the waveform memory as described above, 4 points or 2 points are used to interpolate 4 points or 2 points instead of 6 samples, and interpolation is completed. To obtain musical tone waveform data of.

In the above embodiment, the master sound source 207M and the slave sound source 207S are LSIs having the same configuration.
It uses a chip. The distinction between the master sound source 207M and the slave sound source 207S is based on the 2-chip designation information and the master / slave (M / S) designation information designated by the CPU 204 via the control register 101. That is, each sound source chip operates as the above-mentioned master sound source 207M if two chips are designated by the two-chip designation information and a master is designated by the master / slave designation information. If two chips are designated by the two-chip designation information and a slave is designated by the master / slave designation information, the slave sound source 207S operates as described above. On the contrary, when one chip is designated by the two-chip designation information, the sound source chip operates when one chip is designated. When the master or slave is designated by the master / slave designation information, it may be considered that two chips are designated by the two-chip designation information.

FIG. 9 is a diagram showing the timing of each process when one chip is designated. Compared to the timing when two chips are designated in FIG. 7, the timings of the process A and the interpolation processing are the same in time division channel timing when one chip is designated and when two chips are designated. Regarding the process B and the fetching process, the sections 702, 703, and 70 in FIG.
6, 707 is 1/4 of one sampling cycle, whereas in FIG. 9, sections 902, 903, 906, 90
The difference is that 7 is 1/2 of one sampling period. The state of the channel when processing B and import processing are performed in sections 902, 903, 906, and 907 are as follows.
This is the same as described with reference to FIG. That is, one access is possible in a 1/4 section of a time slot for processing one channel at time division channel timing,
The waveform memory is sequentially and continuously accessed according to the required number of samples of each channel stored in the control RAM 304. When 2 chips are specified, the first half processing section 702
32 accesses were possible in each of the sections 703 and 707 of the latter half processing. When one chip is designated, 64 accesses are possible in each of the first half processing sections 902 and 903 and the second half processing sections 906 and 907. This is because the length of the access section has doubled.

As described above, the sound source chip of this embodiment is
By inputting designation information indicating 1 chip or 2 chips, the access period (section of processing B and fetch processing) is shortened to half when it is 2 chips, and the free time caused by it is reduced. One of the sound source chips can be used for access.

In the above embodiment, the process A arithmetic circuit 301 and the process B arithmetic circuit 305 are independent of each other in the waveform read interpolation circuit 102 of FIG. 3, but the process A arithmetic circuit 301 and the process B arithmetic circuit 305 are formed separately. In summary,
The processing A and the processing B may be performed by sharing one arithmetic circuit in a time division manner.

In the above embodiment, the waveform samples in the waveform memory are in the 16-bit uncompressed format, but other formats may be used. For example, an 8-bit uncompressed format or an 8-bit compressed format may be used while 16 bits can be read with one access. However, in this case, since the number of samples and the number of accesses are different, it is necessary to adjust them. In the case of the compression format, reproduction cannot be performed unless samples are continuously read out, so that it is necessary to take measures in skipping reading.

In the above embodiment, it is determined whether or not the access count accumulated value of the accumulator ACC exceeds 32, which is the maximum accessible count, and the read sample count, access count, and interpolation order of each channel are determined. However, the maximum accessible number may be determined by prioritizing the amount of other processing. For example, when it is known in advance that the waveform memory is refreshed or accessed by the CPU, the number of accesses for these processes is secured in advance, and the above determination is performed with the remaining number as the maximum accessible number. You may do it.

In particular, when a DRAM is used as the waveform memory, refreshing is always necessary, so it is preferable to prioritize the number of accesses for refreshing. Also, reading / writing of the waveform memory from the CPU is as follows.
It is advisable to respond according to the degree of urgency. For example, when the urgency of the waveform memory access from the CPU is low, the access is performed using an empty time slot not used in the sound source channel. When the degree of urgency is high, a portion for waveform memory access from the CPU is secured first, and the rest is used for the sound source channel.

Further, in the above embodiment, as shown in FIG. 8, the waveform memory is continuously accessed in the slots on the front side of the first half and the second half of the processing B and the fetching, but it is not limited to the front side. Good. For example, with respect to the above-mentioned preferentially secured refresh or access from the CPU, those processes are performed in the front slot in the section, and continuous waveform memory access for each channel is performed in the rear slot. You may However, in that case, for example, after the processing of the first half section 703 of the capture processing of FIG. 7 is completed and all the samples necessary for interpolation are prepared in the waveform buffer, the first half section 704 of the interpolation process is performed.
It is necessary to start the interpolation processing of (the same applies to the latter half processing). Therefore, it is necessary to shift the section in which interpolation is performed (it suffices to start the interpolation first-half process after the capture first-half process ends and start the interpolation second-half process after the capture second-half process ends).

Further, in the above embodiment, the process A and the interpolation process are performed by alternately performing the first half process and the second half process in units of the interval obtained by dividing one sampling cycle into 1/2 (the first half and the second half), and fetching the process B and the process. In the processing, the first half processing and the second half processing are alternately performed with a unit of ½ thereof (that is, ¼ of one sampling cycle) as a unit, but the division of the interval is not limited to this. For example, one sampling cycle is divided into ⅓, ¼, ..., Process A and interpolation are performed in units of these intervals, and process B and import processing are performed in ½ of these intervals. You may The processing B and the fetching processing are performed in a section having a time width that is ½ of the processing A and the interpolation processing, and the processing timing of the slave sound source is delayed by that time width from the processing timing of the master sound source. If the adjustment is performed, the waveform memory can be alternately accessed by the master sound source and the slave sound source.
Further, irregular division may be performed instead of equal division. For example, channels 0 to 14 and 15 to 3
It may be divided into one channel, the process A and the interpolation process are performed in each section, and the time width may be adjusted so that the process B and the fetch process can be alternately performed by the master and the slave. Further, one sampling period may be used as a unit without dividing the section. However, it is necessary to ensure that the ARAM is not rewritten by the process A before the address is sent in the process B and the waveform memory is accessed. For that purpose, for example, when the sections are not divided, two sets of address RAMs are prepared, and two sets of address RAMs are alternately used for rewriting addresses by the process A and sending addresses by the process B. Need to collect. According to the method in which one sampling period is divided into the first half and the second half,
Since the processing A and the processing B can be alternately performed by one set of the address RAMs, it can be said that the circuit configuration is simple and rational.

Further, in the above-described embodiment, one waveform memory is shared by the two chips of the master tone generator and the slave tone generator, but one waveform memory can be shared by more tone generator chips. For that purpose, the waveform memory access may be performed by dividing the sections of the process B and the acquisition process by a plurality of sound source chips.

When the number of access points for a certain channel is insufficient and the number of interpolation points is reduced and then the original number of interpolation points is restored, at that time, the number of access times of the same channel is temporarily increased to be larger than usual. You may

In the present embodiment, the access to the waveform memory of the sound source is limited in order to share one waveform memory between the two sound sources. However, the access can be limited for other purposes. . For example, when one sound source is connected to the waveform memory, the waveform memory access period of the sound source is limited, and the generated access period is used by the waveform sampling circuit, the CPU, the DMAC, and other data transfer circuits. You may do it. Further, the method of limiting the access period does not have to be limited to 1/2 of the entire period, and may be 2/3, 2/5, or the like. Further, the player or the CPU may be allowed to specify the length of the access period by the time length.

[0087]

According to the present invention, the address of each channel is created and temporarily stored in the address storage means prior to the reading of the waveform memory, and the number of accesses is based on the advance amount of the address of each channel. Is calculated, and the waveform memory is continuously accessed for each access. The waveform sample read from the waveform memory is
The tone generation means, once stored in the waveform sample storage means, generates a tone for each sampling period of each channel based on the waveform sample of each channel stored in the waveform sample storage means. Since the address and the waveform sample are buffered in the address storage means and the sample storage means, the timing of reading the waveform sample can be adjusted appropriately, and continuous access matching the speed of the waveform memory becomes possible. Therefore, when it is not necessary to read the waveform sample on a certain channel, or when only a small number of waveform samples need to be read because a waveform sample buffered on a certain channel can be used,
The remaining time slots can be used for other processing (for example, periodical access to the waveform memory by other access means). Further, since the surplus time slots can be used for access to other channels, the number of cases in which the interpolation order needs to be reduced due to the relationship between channels decreases.

In particular, in the present invention, since the waveform memory access periods of a plurality of sound sources are adjusted so that they do not conflict with each other, a plurality of sound sources can share one waveform memory.

As described above, according to the present invention, in the sound source of the waveform memory reading system which simultaneously generates musical tones for a plurality of channels in the time-division channel operation, the waveform can be efficiently generated by each channel when necessary. You will be able to access the memory.

[Brief description of the drawings]

FIG. 1 is a block configuration diagram of a sound source unit to which a sound source device according to an embodiment of the present invention is applied.

FIG. 2 is an overall block configuration diagram of an electronic musical instrument to which the tone generator device of the present embodiment is applied and a schematic configuration diagram of a tone generator section.

FIG. 3 is a block configuration diagram of a waveform readout interpolation circuit.

FIG. 4 is a configuration diagram of a control RAM.

FIG. 5 is a diagram showing a memory map of ARAM.

FIG. 6 is a configuration diagram of a waveform buffer;

FIG. 7 is a processing timing chart in the waveform reading interpolation circuit of each of the master sound source and the slave sound source.

FIG. 8 is a diagram showing a state of a channel during each processing of FIG.

FIG. 9 is a diagram showing the timing of each process when one chip is designated.

FIG. 10 is a diagram showing a specific example of reducing the number of accesses in this embodiment.

[Explanation of symbols]

101 ... Control register, 102 ... Waveform reading interpolation circuit, 105 ... Volume change control unit, 106 ... Channel (c
h) Accumulator, 107 ... Effect circuit, 108 ... Refresh counter, 109 ... CPU access control unit, 110, 1
11 ... Selector, 112 ... System clock generator, 1
13 ... Channel (ch) counter, 204 ... Central processing unit (CPU), 207 ... Sound source section, 207M ... Master sound source, 207S ... Slave sound source, 208 ... Waveform memory,
210 ... Digital-to-analog converter (DAC), 211
… Sound system (SS), 212… External storage,
213 ... Bus, 220 ... Mixer, 301 ... Process A arithmetic circuit, 302 ... Address RAM (ARAM), 303 ... Accumulator (ACC), 304 ... Control RAM, 305
... Process B arithmetic circuit, 306 ... Interpolation circuit, 307 ... Waveform buffer, 308 ... Acquisition circuit.

Claims (4)

[Claims] 1. A waveform memory sound source device for generating musical tones of a plurality of channels by operating in time division on a plurality of channels at a predetermined sampling period, the waveform memory storing waveform samples, One that can be accessed a predetermined number of times within the processing time for one channel, address storage means for storing the address of each channel, waveform sample storage means for storing the waveform sample of each channel, said waveform Prior to reading the memory, the address of each channel is created and stored in the address storage means, and the number of times the waveform memory is accessed for each channel is calculated based on the advance amount of the address of each channel. Access count calculation means and the number of channels , Accumulates the number of accesses is calculated by the access number calculation unit, and accumulating means for outputting the accumulated number of times, within the access period corresponding to said predetermined number of channels,
Determination means for determining whether or not access for the accumulated number of times is possible, access period switching means for switching the time width of the access period to a normal length or a shortened length, and the determination means determines that the access is possible In this case, based on the address of each channel stored in the address storage means, the waveform memory is continuously accessed and read for each access count of each channel calculated by the access count calculation means, within the access period. First access means for storing the waveform sample of each channel in the waveform sample storage means, and second access means for accessing the waveform memory in a free time generated by shortening the access period by the access period switching means. And the waveform sample of each channel stored in the waveform sample storage means. A waveform memory sound source device, comprising: a tone generation means for generating a tone for each channel sampling period based on pulling. 2. A waveform memory sound source device for generating musical sounds of a plurality of channels by operating in a time-divisional manner on a plurality of channels at a predetermined sampling period, wherein waveform samples are stored and one channel within the predetermined sampling period is stored. An address storage unit for storing an address of each channel, a waveform sample storage unit for storing a waveform sample of each channel, in which a waveform memory that can be accessed a predetermined number of times within a processing time is connected, Prior to reading the waveform memory, an address of each channel is created and stored in the address storage means, and the number of times the waveform memory is accessed for each channel is calculated based on the advance amount of the address of each channel. A method of calculating the number of accesses and a predetermined number of channels The accumulating means for accumulating the access times calculated by the access frequency calculating means and outputting the accumulated times, and the time width of the access period set corresponding to the predetermined number of channels are set to the predetermined number. Access period switching means for determining, on the basis of an input instruction signal, whether to set the same time width as the time width in the case of processing at time division channel timing for the channel A determining means for determining whether or not it is possible to access the accumulated number of times within an access period; and when the determining means determines that the access is possible, the access is performed based on the address of each channel stored in the address storage means. The waveform memory is continuously accessed and read by the number of times of access of each channel calculated by the number-of-times calculating means within the access period. First access means for storing the projected waveform sample of each channel in the waveform sample storage means, and a tone for each sampling period of each channel based on the waveform sample of each channel stored in the waveform sample storage means A waveform memory sound source device comprising: 3. A waveform memory sound source in which a mode specifying signal for specifying whether to operate in the first mode or the second mode is input, and the access period is switched in the waveform memory sound source in which the first mode is specified. With the time width shortened by the means, the synchronizing signal is output to another waveform memory sound source device in which the second mode is designated, and in the waveform memory sound source in which the second mode is designated, The access period switching means sets the access period to a shortened time width, and the synchronization signal output from the waveform memory sound source in which the first mode is designated is input to designate the first mode. The access period of the waveform memory tone generator in which the second mode is specified is arranged in a section other than the access period of the waveform memory tone generator. Claim 2 to adjust the processing timing
Waveform memory sound source device described in. 4. A waveform memory sound source device for generating musical tones of a plurality of channels by operating in a time-divisional manner on a plurality of channels at a predetermined sampling period, and a first tone generator for generating musical tones of a plurality of channels and another plurality of channels. A second sound source for generating a musical sound;
Mixing means for mixing and outputting the musical sound from the sound source and the musical sound from the second sound source, and a waveform memory storing a waveform sample, which is stored a predetermined number of times within the processing time for one channel within the predetermined sampling period. An accessible waveform memory, wherein the first sound source has first address storage means for storing an address of each channel, first waveform sample storage means for storing a waveform sample of each channel, Prior to the reading of the waveform memory, an address of each channel is created and stored in the first address storage means, first address creating means, and the waveform of each channel based on the advance amount of the address of each channel. First access count calculating means for calculating the memory access count; and each channel stored in the first address storing means. Based on the address of the channel, the waveform memory is continuously accessed by the number of times of access of each channel calculated by the first number of accesses calculation means, and the read waveform sample of each channel is stored in the first waveform sample storage means. The second sound source includes: a first access unit that stores the tone; and a tone generation unit that generates a tone for each sampling period of each channel based on the waveform sample of each channel stored in the first waveform sample storage unit. A second address storage means for storing an address of each channel, a second waveform sample storage means for storing a waveform sample of each channel, and an address of each channel created prior to reading the waveform memory. The second address creating means to be stored in the second address storing means, and each channel. Second access number calculation means for calculating the number of times of access to the waveform memory for each channel based on the amount of advance of the address of the channel, and the second access number calculation means based on the address of each channel stored in the second address storage means. Second access means for continuously accessing the waveform memory for each access count of each channel calculated by the access count calculation means and storing the read waveform sample of each channel in the second waveform sample storage means; A tone generating means for generating a tone for each sampling period of each channel based on the waveform sample of each channel stored in the second waveform sample storage means, the waveform memory by the first access means of the first sound source. By using the free time of access of the second sound source by the second access means. A waveform memory sound source device, wherein timing adjustment is performed so as to access the waveform memory.