JPH09140162A - Inverter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent distortion of output current by providing a phase voltage detector in parallel with upper and lower switching elements and combining the detection outputs therefrom under specified conditions thereby regulating the concurrent nonconduction time. SOLUTION: Arm switching elements SW 9, 10 are conducted alternately based on a signal from an inverter control section 5 to apply an AC voltage to an induction motor 3 thus producing an inverter output current I0 . A phase voltage detection circuit PC 4, 4a set a predetermined value for varying the output signal such that each phase voltage V0 will be slightly lower than a DC input voltage. A synthesizer circuit 20 synthesizes a timing at which the PC 4 on the lower arm side makes a transition from H to L and a timing at which the PC 4a on the upper arm side makes a transition from H to L. Consequently, the timing immediately after function of the SW 9, 10 can be detected under same conditions.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to control of a switching element used in an inverter device.

[0002]

2. Description of the Related Art FIGS. 7 and 8 are disclosed in JP-A-4-69066.
FIG. 7 is a diagram showing a configuration of one phase of a multi-phase inverter device, and FIG. 8 is a time chart showing its operation, which is a conventional example shown in Japanese Patent Publication No.

In FIG. 7, reference numeral 1 is a DC power source composed of a converter or the like, 2 is an inverter portion for one phase for obtaining an AC current from the DC power source 1, and generates a driving current for the induction motor 3 and a reference numeral 9 It is composed of an arm switching element, a lower arm switching element, freewheel diodes 11 and 12, and a phase voltage detection circuit of 4. The phase voltage detection circuit 4 comprises 13/14 voltage dividing resistors, 15 current limiting resistors, 16 pull-up resistors, 17 shunt regulator signal supply means, and 18 photocoupler signal insulation means. Reference numeral 5 denotes an inverter control unit, which is composed of a Td correction circuit 6 and a Td generation circuit 7 and a base drive circuit 8 and receives signals from the phase voltage detection circuit 4 and outputs the base drive circuit 8 to switch the upper and lower arm switching elements. Drive control of 9/10.

Next, the operation will be described. Since the configuration of each phase of the multi-phase inverter is the same, the operation for one phase will be described here. An arm switching element 9.1 according to a signal from the inverter control unit 5
0 alternately conducts, and the inverter output current I ₀ flows by applying an AC voltage to the induction motor 3. Further, the phase voltage detection circuit 4 inputs the output phase voltage V ₀ and outputs a signal when the value exceeds a predetermined value. The inverter control unit 5 controls the drive of the arm switching element based on the signal from the phase voltage detection circuit 4 while ensuring a short circuit prevention time (hereinafter referred to as Td) for preventing a short circuit of the DC power supply due to the simultaneous vertical conduction of the arm switching elements. . That is, as shown in FIG. 8, the ideal output phase voltage of the inverter has the waveform of (1), but delays the conduction of the upper and lower arm switching elements in order to secure Td. It conducts at the timing shown.

[0005]

In the conventional inverter device, the potential of the phase voltage is not established near the point where the current I ₀ flowing through the induction motor 3 is small, and the potential of the phase voltage is not established. Shows unstable changes such as. Therefore, when the predetermined value for changing the output signal of the phase voltage detection circuit 4 is set as shown by the alternate long and short dash line in the figure, the detection timing is a large output current I ₀ shown in (a) of (5) in the figure. A time shift of t _n shown in (b) occurs as compared with time. In the conventional example of the above-mentioned publication, the predetermined value is set to about 1/2 of the DC input voltage value to reduce the time lag, but as shown in the figure, the output current becomes unstable due to instability. It is enough. In other words, no matter how the predetermined value is set to 1/2, which is the center value of the voltage, in the phase voltage detection circuit on one side, it is not possible to obtain uniform timing for the upper and lower arms when fluctuations in the voltage occur. As a result, the Td correction is not properly performed for the switching of the element, and the distortion of the inverter current waveform becomes remarkable in the low frequency region where the influence of Td is particularly large, and the rotation unevenness occurs in the induction motor 3. There was a problem.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain an inverter device in which the distortion of the output current is small even in the low frequency region and the induction motor can be smoothly operated. And

[0007]

According to a first aspect of the present invention, an inverter device is provided with a phase voltage detecting device in parallel with upper and lower switching elements, and a detection output of each phase voltage detecting device is set under a predetermined condition. By synthesizing the signals, a signal for adjusting the simultaneous non-conduction time Td for preventing the short circuit of the DC power supply due to the simultaneous conduction of the upper and lower switching elements is stably obtained.

In the inverter device according to the second aspect of the present invention, the detection output of the phase voltage detecting device is waveform-shaped in the differential pulse generating circuit to synthesize it as a more reliable timing signal, thereby making the Td adjustment more stable. It is what

The inverter device according to the third aspect of the present invention stabilizes the output by the phase voltage detection circuit at the timing when the phase voltage rises immediately after the conduction of the switching element is cut off. It is intended.

In the inverter device according to the fourth aspect of the present invention, the change in the phase voltage after the conduction of the switching element is cut off is detected by the voltage differential detection circuit, and the signal corresponding to each switching element is determined. By combining under the conditions, T
The d adjustment is made more stable.

In the inverter device according to the fifth aspect of the present invention, as a phase voltage differential pulse generating circuit, a series connection circuit of a capacitor and a photocoupler is used, and the phase of the photocoupler is changed only when the phase voltage changes and the charging current of the capacitor flows. An output signal is output, the circuit response is good because of the differentiation circuit, and Td
Besides contributing to the stabilization of the adjustment, the current consumption of this circuit is reduced.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. 1 and 2 show an example of an embodiment of an inverter device according to the present invention. FIG. 1 is a diagram showing a configuration of one phase of a multi-phase inverter device, and FIG. 2 is a time chart showing its operation. It is a chart. In FIG. 1, 1 to
Reference numerals 12, 15, 16 and 18 are the same as those in the conventional device and will not be described. Reference numeral 4a is a phase voltage detection circuit inserted in parallel with the upper arm switching element 9, and comprises a current limiting resistor 15a, a pull-up resistor 16a, and a photocoupler 18a. 20 is a signal from the phase voltage circuit 4a and the phase voltage circuit 4 inserted in parallel with the lower arm switching element 10.
Is a synthesizing circuit for synthesizing the signals from the above to generate a signal used for Td correction and supplying the signal to the inverter control unit 5.

Next, the operation will be described. Similar to the conventional example, the configuration of each phase of the multi-phase inverter is the same for all the phases, and therefore the operation for one phase will be described here. The arm switching elements 9 and 10 are alternately turned on by a signal from the inverter control unit 5, and by applying an AC voltage to the induction motor 3, the inverter output current I
_The same applies to the point where ₀ flows. Further, the phase voltage detection circuits 4 and 4a set the predetermined value for changing the output signal to a value at which each phase voltage V ₀ is slightly lower than the DC input voltage value, so that (5) in FIG. The output signal shown in is obtained. Therefore, the timing when the output signal of the phase voltage detection circuit 4 on the lower arm side changes from the H (high) level to the L (low) level, and the output signal of the phase voltage detection circuit 4a on the upper arm side changes from H to L. The timing for performing the synthesis circuit 20
The signal shown in (6) of FIG. 2 is obtained by synthesizing.

[0014] This signal, even unstable change in the output phase voltage as shown, the variation in the value of t _n in the figure because it is generated on the basis of the timing immediately after the change has started Can be suppressed. That is, the timing immediately after the operation of each arm switching element can be detected under the same upper and lower conditions. Therefore, by inputting the output of the synthesizing circuit 20 to the inverter control unit 5, Td correction synchronized with the switching of the element can be performed, so that the distortion of the inverter current waveform is minimized even when the output current is near zero. Even when the induction motor is operated in the low frequency range due to the inverter current, smooth operation can be performed without causing uneven rotation.

Embodiment 2 FIGS. 3 and 4 show an example of an embodiment of another inverter device according to the present invention. FIG. 3 is a diagram showing a configuration of one phase of a multi-phase inverter device, and FIG. It is a time chart shown. In FIG. 3, 1 to 12, 15, 16, 18, 4a, 1
Reference numerals 5a, 16a, and 18a are the same as those of the inverter device of the first embodiment, and description thereof will be omitted. 21 is a falling differential pulse generation circuit, which is a delay circuit of 22.22a, 23.
A set / reset flip-flop 25 is constituted by an inverting gate 23a and a NOR gate 24.24a.

Next, the operation will be described. Compared to the first embodiment, the synthesizing circuit 20 includes a falling differential pulse generating circuit 21 and a set / reset flip-flop 25. That is, the phase voltage detection circuit 4
The NOR gate 24, 24a outputs the signal output from 4a.
To the other gate of the NOR gate through the delay circuits 22 and 22a and the inverting gates 23 and 23a to generate a differential pulse. Set and reset these flip-flops 2
By inputting to 5, the signal corresponding to the synthesizing circuit 20 of the first embodiment can be generated as shown in (5) of FIG. 4, and the same effect as described above can be obtained.

Embodiment 3 5 and 6 show an example of an embodiment of another inverter device according to the present invention. FIG. 5 is a diagram showing the structure of one phase of a multi-phase inverter device, and FIG. 6 shows its operation. It is a time chart shown. In FIG. 5, 1-3, 5-12, 15, 16, 18,
Reference numerals 4a, 15a, 16a, and 18a are the same as those of the inverter device of the first embodiment, and the description thereof will be omitted. Reference numeral 25a is a flip-flop, 26 and 26a are phase voltage differential pulse generation circuits, 27 and 27a are capacitors, and 28 and 28a are bypass diodes.

Next, the operation will be described. Compared to the first embodiment, the phase voltage detection circuits 4 and 4a are replaced with the phase voltage differential pulse generation circuits 26 and 26a, and the synthesis circuit 20 is replaced with a flip-flop 25a. That is, as shown in FIG. 6, when the phase voltage V ₀ rises, the phase voltage differential pulse generation circuit 26 has a built-in capacitor 27.
Due to the charging current of, the phase voltage fluctuation input V _d has a voltage waveform as shown in (3) in the figure. Therefore, the photocoupler 18 is operated by the charging current of the capacitor 27, and the phase voltage differential pulse shown in (a) of (4) in the figure is generated. The same operation is performed on the upper arm side, and the phase voltage differential pulse shown in (b) is generated. These pulses are flip-flop 25a
By inputting into, it is possible to obtain the timing that is the basis of the Td correction shown in (5) in the figure. Therefore, also in this embodiment, the same effects as those of the other embodiments described above can be obtained. In this embodiment, since the duty of the current flowing through the current limiting resistors 15 and 15a can be greatly reduced, the amount of heat generated by the resistor is reduced, the rated capacity of the resistor can be reduced, and energy saving can be realized. In other words, the current flowing through the current limiting resistor, which is a resistor that adjusts the current flowing through this circuit, is different from the DC current according to the other inventions described above, and is only the charging / discharging current flowing through the capacitor. is there.

[0019]

As described above, the present invention is provided with a pair of upper and lower phase voltage detection circuits for each phase of the inverter device. The outputs of the detection circuits are combined to generate a signal, and the combined signal is generated. By uniformly detecting the conduction timings of the upper and lower arm switching elements by using the time T, the upper and lower arm switching elements are simultaneously turned off.
By correcting d, it is possible to correct the bias, so that the distortion of the output current can be reduced when the inverter is operated in a low frequency range. You can get it.

Further, by using the phase voltage differential pulse generating circuit as the phase voltage detecting circuit, the duty of the current flowing through the current limiting resistor of the photocoupler can be significantly reduced. It is possible to significantly reduce the rated power of the resistor.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of one phase of a multi-phase inverter device showing an example of an embodiment of the present invention.

FIG. 2 is a diagram showing a time chart of the operation corresponding to the example of the embodiment.

FIG. 3 is a diagram showing a configuration of one phase of a multi-phase inverter device showing another example of the embodiment of the present invention.

FIG. 4 is a diagram showing a time chart of an operation corresponding to another example of the above embodiment.

FIG. 5 is a diagram showing a configuration of one phase of a multi-phase inverter device showing still another example of the embodiment of the present invention.

FIG. 6 is a diagram showing a time chart of the operation corresponding to still another example of the above embodiment.

FIG. 7 is a diagram showing a configuration of one phase of a conventional multi-phase inverter device.

FIG. 8 is a diagram showing a time chart of the operation of the conventional multi-phase inverter device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 DC power supply 2 Inverter section for 1 phase 4.4a Phase voltage detection circuit 5 Inverter control section 20 Combining circuit 21 Falling differential pulse generating circuit 25 Set / reset flip-flop 26.26a Phase differential voltage generating circuit

Claims (5)

[Claims] 1. An inverter unit connected to a DC power source, wherein a pair of upper and lower switching elements are connected in series and an output is taken out from the connection point, and a time Td for simultaneously bringing the pair of upper and lower switching elements into a non-conducting state is adjusted. In an inverter device provided with the same number of output phases as an inverter control unit for giving a conduction instruction of the switching element, a phase voltage detection circuit connected in parallel to each of the switching elements and an output signal of each of the phase voltage detection circuits. An inverter device comprising: a synthesizing circuit for extracting timings of a predetermined condition from, synthesizing and outputting the timings to an inverter control unit. 2. An inverter unit connected to a DC power supply, in which a pair of upper and lower switching elements are connected in series and an output is taken out from the connection point, and a time Td during which the pair of upper and lower switching elements are brought into a non-conducting state at the same time is adjusted. In an inverter device provided with the same number of output phases as an inverter control unit for giving a conduction instruction of the switching element, a phase voltage detection circuit connected in parallel to each of the switching elements and an output signal of each of the phase voltage detection circuits. Of the differential pulse generating circuit that generates each pulse signal when the voltage changes and output pulses corresponding to each phase voltage detection circuit signal of the differential pulse generating circuit. An inverter device comprising a combining circuit for outputting. 3. The inverter device according to claim 1 or 2, wherein the timing of the predetermined condition extracted by the synthesis circuit means that the conduction of the lower switching element is cut off. An inverter device characterized in that the timing detected by the signal output and detected by the upper phase voltage detection circuit and the signal output by the upper phase voltage detection circuit are obtained. 4. An inverter unit connected to a DC power supply, in which a pair of upper and lower switching elements are connected in series and an output is taken out from the connection point, and a time Td for simultaneously bringing the pair of upper and lower switching elements into a non-conducting state is adjusted. In the inverter device provided with an inverter control unit for giving a conduction command of the switching element for the number of output phases, a phase voltage differential pulse generation circuit connected in parallel to each of the switching elements,
An inverter device comprising a combining circuit for extracting timings of a predetermined condition from respective output signals of the phase voltage differential pulse generating circuit, combining the extracted timings, and outputting the combined timings to an inverter control section. 5. The inverter device according to claim 4, wherein the phase voltage differential pulse generation circuit is configured by connecting a capacitor and a current limiting resistor in series to a photocoupler in which a bypass diode having a reverse polarity is connected in parallel. And the photocoupler is activated by the charging current of the capacitor generated by the input voltage of the phase voltage differential pulse generation circuit which rises when the switching elements connected in parallel cut off the conduction, and the output pulse is generated. Inverter device.