JPH09139757A - Contention data processing circuit - Google Patents

Contention data processing circuit

Info

Publication number
JPH09139757A
JPH09139757A JP7294173A JP29417395A JPH09139757A JP H09139757 A JPH09139757 A JP H09139757A JP 7294173 A JP7294173 A JP 7294173A JP 29417395 A JP29417395 A JP 29417395A JP H09139757 A JPH09139757 A JP H09139757A
Authority
JP
Japan
Prior art keywords
data
priority
reception
received
received data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7294173A
Other languages
Japanese (ja)
Inventor
Masayuki Suzuki
昌幸 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7294173A priority Critical patent/JPH09139757A/en
Publication of JPH09139757A publication Critical patent/JPH09139757A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To attain communication processing such as frame multiplexing even when some of plural reception data received in parallel are in contention to each other. SOLUTION: The circuit is provided with a memory section 10 consisting of a register 8 storing all of synchronous serial reception data of plural numbers N of the same fixed length by each of received data and of a selector 9 selecting any of output data, a simultaneous reception detection section 3 detecting a state that some of plural reception data are simultaneously received and they are in contention, and a control section 7 conducting a processing 6 that when the contention state is detected, reception data received in average together with information in a register 5 storing preceding contention information are discriminated to be priority data. One of received data stored in the register 8 is selected as a selection signal for the selector as to the discrimination result of priority processing by the control section 7 and used for output data.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、並列に複数N の固定長
の同期式シリアルデータを受信してフレーム多重等の通
信処理をする場合のデータ処理回路に係り、特に並列入
力の複数N の受信データの幾つかが同時に受信され互に
競合する場合に、其の後段でフレーム多重等の通信処理
が可能となる様に受信データを処理する競合データ処理
回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing circuit for receiving a plurality of N fixed-length synchronous serial data in parallel and performing communication processing such as frame multiplexing. The present invention relates to a competitive data processing circuit that processes received data so that communication processing such as frame multiplexing can be performed in the subsequent stage when some of received data are simultaneously received and compete with each other.

【0002】[0002]

【従来の技術】従来の並列に複数N の固定長の同期式シ
リアルデータを受信して例えばフレーム多重等の通信処
理をする場合には、図15の従来例の回路図に示す様に、
受信入力データ(IN DATA 1〜IN DATA N)の並列数N だ
け、各受信データの時間関係を,フレーム同期を取って
多重化するのに適する様に制御する受信制御回路を具
え、それぞれの受信制御回路が個別の受信データに対し
必要な時間の制御を行った後、フレーム多重MUX 等の通
信処理をしていた。
2. Description of the Related Art Conventionally, when a plurality of N fixed-length synchronous serial data are received in parallel and communication processing such as frame multiplexing is performed, as shown in a circuit diagram of a conventional example of FIG.
The number of parallel input data (IN DATA 1 to IN DATA N) N, the reception control circuit that controls the time relationship of each received data so as to be suitable for multiplexing in frame synchronization. After the control circuit controlled the required time for each received data, it performed communication processing such as frame multiplexing MUX.

【0003】[0003]

【発明が解決しようとする課題】その為に、複数N の受
信データの中の幾つかが同時に受信され互に競合した場
合には、其の複数N の受信データをフレーム多重MUX 等
の通信処理をすることが出来なかった。本発明の課題
は、この様に並列に入力する複数N の受信データが互に
競合した場合でも、フレーム多重MUX 等の通信処理が可
能となる様に、受信データを処理する競合データ処理回
路を提供することにある。
Therefore, when some of a plurality N of received data are received at the same time and compete with each other, the plurality of N received data are subjected to communication processing such as frame multiplexing MUX. I couldn't do it. An object of the present invention is to provide a competitive data processing circuit that processes received data so that communication processing such as frame-multiplexed MUX can be performed even when multiple N received data input in parallel compete with each other. To provide.

【0004】[0004]

【課題を解決するための手段】この課題を解決するため
の本発明の請求項1の競合データ処理回路の基本構成
は、図1の原理的な構成図に示す如く、並列に入力する
複数N の夫々が同じ固定長で同期式シリアルデータ(IN
DATA 1〜IN DATA N)の受信データの全てを, 各受信入力
データ別に格納するレジスタ(8)と其の出力データの一
つを選択するセレクタ(9)から成るメモリ部(10)と、該
複数N の受信入力データの幾つかが同時受信され互に競
合する状態を検出する同時受信検出部(3)とを具え、該
受信入力データが競合する状態が検出された場合には、
前回の競合時の情報判定部(6)を含めて平均的に受信回
数の多い受信データを優先すると判定する処理(6) を行
い、其の優先処理の判定結果を前記メモリ部(10)のデー
タのセレクタ(9)の選択信号として、前記複数N のレジ
スタ(8)に格納した受信データの一つを選択して、出力
データ(OUT DATA)とするように構成する。
The basic configuration of the competing data processing circuit according to the first aspect of the present invention for solving this problem is a plurality of N input in parallel as shown in the principle configuration diagram of FIG. Have the same fixed length and synchronous serial data (IN
A memory unit (10) consisting of a register (8) for storing all the received data of (DATA 1 to IN DATA N) for each received input data and a selector (9) for selecting one of the output data, A simultaneous reception detection unit (3) for detecting a state in which some of the plurality of N received input data are simultaneously received and competes with each other, and when a state in which the received input data competes is detected,
The process (6) that determines that the reception data that has received a large number of times on average is prioritized, including the information determination unit (6) at the time of the last conflict, and the determination result of the priority process is stored in the memory unit (10). As the selection signal of the data selector (9), one of the reception data stored in the plurality of N registers (8) is selected and is set as output data (OUT DATA).

【0005】この本発明の構成では、並列に入力する複
数N の同じ固定長の同期式シリアルデータである受信デ
ータを、フレーム多重MUX 等の通信処理を行う場合で、
複数N の受信データの幾つかが同時受信され互に競合し
た場合には、前回の競合時の情報を保持しているレジス
タ(5) の情報を含めて平均的に受信回数の多い受信デー
タを優先すると判定する処理(6)を行うことで、順次入
力されたデータとしてメモリ部(10)から出力される。そ
うすれば、其の出力データ(OUT DATA)を用いて、フレー
ム多重MUX 等の通信処理を行うことが可能となる。
In the configuration of the present invention, when a plurality of N pieces of received data, which are synchronous serial data of the same fixed length and are input in parallel, are subjected to communication processing such as frame multiplexing MUX,
If some of the received data of multiple N are received at the same time and compete with each other, the received data with the most number of receptions including the information of the register (5) that holds the information at the time of the previous competition is received. By performing the process (6) for determining priority, the data is sequentially output from the memory unit (10). Then, the output data (OUT DATA) can be used to perform communication processing such as frame multiplexing MUX.

【0006】[0006]

【発明の実施の形態】図1は、本発明の請求項1に対応
する実施例の競合データ処理回路の構成図でもある。図
1の(3) 同時受信検出部の中の並列に複数N の(1)受信
パルス生成部は、個別に受信入力データ(IN DATA) の中
の固定長の同期式シリアルデータの検出を行う。その検
出方法は、図9の回路構成と其の動作説明図に示す様
に、受信したクロックの固定長L の同期式シリアルデー
タAから其のフレーム先端FTOPのBを検出し、其の検出
出力Bを基準としてシリアルの受信データAを S/P変換
器でパラレルデータに変換し、受信入力した同期式シリ
アルデータの誤りの有無を調べる巡回冗長検査CRC(Cycl
ic Redundancy Check)を行い、其の検査CRC の結果が O
K の時に出力するパルスCにより、一定時間幅(ウイン
ドウW )の受信パルスOUT を生成し出力する。この各受
信パルス生成部(1)にて生成された複数N の受信パルスO
UT を、同時検出判定部(2) に入力し、並列に N本の固
定長の同期式シリアルデータの中で同時受信され競合状
態にある幾つかの受信データの組み合せの検出を行う。
図10はN=3の場合の同時受信検出部(3) の動作説明図で
あり、図11は其の中の同時検出判定部(2)の回路構成例
を示す。図11の同時検出判定部の動作を以下に説明す
る。その前段のN=3個の各受信パルス生成部(1)で生成
した各INDATA 1〜IN DATA 3 毎の3個の受信パルスOUT
の A,B,Cを、各入力IN DATA 毎に受信情報 A1,B1,C1〜A
3,B3,C3として、各レジスタ1 〜レジスタ3 に格納する
が、其の各3入力IN DATA の論理和OR出力により、最初
に受信した情報A1,B1,C1はレジスタ1 に書き込み格納す
る。一度書き込むと、ライトカウンタはカウントUPす
る。次に IN DATA2 の受信パルスOUT が来ると、その受
信した情報 A2,B2,C2をレジスタ2 に格納(ライト)す
る。更に受信した IN DATA 3の受信パルスOUT の情報A
3,B3,C3は、レジスタ3 に格納(ライト)する。そして
各レジスタ1,2,3 の出力をセレクタSEL の3入力とし、
読み出し用リードカウンタの出力の2ビット信号によ
り選択し、選択した出力の3情報を入力とし、受
信判定デコーダDEC にて、図12の (a)同時受信判定DE
C 表に示す如く、同時受信か単独受信かの判定を行う。
そして其の判定結果をリードカウンタの入力とする。
図12の(b) は同時検出判定部(2)の中のリードカウンタ
の構成を示す。このリードカウンタは、図11の受信判定
DECの判定結果を入力して現カウント値をUPするかD
OWNするかの判定を行う UP/DOWN判定器と、その出力で
動作する3進のUP/DOWN カウンタと、そのカウンタ出力
で3受信データA,B,C の1つを選択するセレクタSEL と
で構成される。3進の UP/DOWNカウンタは、前記判定結
果が、3情報の中の2つ以上が同時受信と判定
された場合に動作する。3進カウンタの UP/DOWNは、図
13の優先処理判定部の動作を表す優先処理状態遷移表に
従って行われる。図12の(b) のリードカウンタの中のセ
レクタSEL の3入力の中の"00"は IN DATA 1の受信パル
スOUT のAに相当し,"01" は IN DATA 2の受信パルスOU
T のBに相当し,"10" は IN DATA 3の受信パルスOUT の
Cに相当する。そして、各 IN DATAの単独受信時には、
セレクタSEL の出力"00"のA,"01" のB ," 10"のCを
選択して、各データの単独受信を表す2ビットの出力
とする。
1 is also a block diagram of a competitive data processing circuit of an embodiment corresponding to claim 1 of the present invention. In Fig. 1, (3) Simultaneous reception detection unit, multiple N in parallel (1) reception pulse generation units individually detect fixed-length synchronous serial data in reception input data (IN DATA). . The detection method is, as shown in the circuit configuration of FIG. 9 and its operation explanatory diagram, detecting the B of the frame front end FTOP from the synchronous serial data A of the fixed length L of the received clock and detecting the detection output. Cyclic redundancy check CRC (Cycl) that converts serial received data A into parallel data with the S / P converter using B as a reference and checks whether there is an error in the received synchronous serial data.
ic Redundancy Check) and the result of the inspection CRC is O
The pulse C output at the time of K generates and outputs the reception pulse OUT having a constant time width (window W). Multiple N received pulses O generated by each received pulse generator (1)
The UT is input to the simultaneous detection judgment unit (2), and a combination of several received data that are simultaneously received in parallel among N fixed length synchronous serial data is detected.
FIG. 10 is an operation explanatory diagram of the simultaneous reception detection unit (3) in the case of N = 3, and FIG. 11 shows a circuit configuration example of the simultaneous detection determination unit (2) therein. The operation of the simultaneous detection determination unit in FIG. 11 will be described below. Three reception pulses OUT for each INDATA 1 to IN DATA 3 generated by N = 3 reception pulse generation units (1) in the preceding stage
A, B, C of the received information A1, B1, C1 ~ A for each input IN DATA
The information A1, B1, C1 received first is written and stored in the register 1 by the logical OR output of the three inputs IN DATA, which are stored in the registers 1 to 3 as 3, B3, C3. Once written, the write counter will count up. When the IN DATA2 receive pulse OUT arrives next, the received information A2, B2, C2 is stored (written) in register 2. Further received IN DATA 3 received pulse OUT information A
3, B3, C3 are stored (written) in register 3. And the output of each register 1,2,3 is 3 inputs of selector SEL,
It is selected by the 2-bit signal of the output of the read counter for reading, and the 3 information of the selected output is input, and the reception judgment decoder DEC (a) Simultaneous reception judgment DE of FIG.
As shown in Table C, it is judged whether simultaneous reception or single reception.
Then, the result of the determination is input to the read counter.
FIG. 12B shows the configuration of the read counter in the simultaneous detection determination unit (2). This read counter is used for the reception judgment of Fig. 11.
Enter the DEC judgment result to increase the current count value or D
With the UP / DOWN decision device that decides whether to perform OWN, the ternary UP / DOWN counter that operates by its output, and the selector SEL that selects one of the three received data A, B, C by the counter output. Composed. The ternary UP / DOWN counter operates when the determination result indicates that two or more of the three pieces of information are simultaneously received. UP / DOWN of ternary counter
This is performed according to the priority processing state transition table showing the operation of the 13 priority processing determination units. "00" in the three inputs of the selector SEL in the read counter of Fig. 12 (b) corresponds to A of the IN DATA 1 received pulse OUT, and "01" is the IN DATA 2 received pulse OU.
Equivalent to B of T, "10" corresponds to C of received pulse OUT of IN DATA 3. And when receiving each IN DATA independently,
The output of the selector SEL is selected from "00" A, "01" B, and "10" C to provide a 2-bit output indicating the individual reception of each data.

【0007】図1に戻り、同時検出判定部(2)の検出結
果(4)と、制御部のレジスタに格納されている前回
の同時受信検出時に優先処理されて出力された最終処理
データの情報とにより、優先処理判定部(6)にて受信デ
ータの優先処理の判定を行う。其の判定方法は、レジス
タ(5)に格納されている前回の競合情報を含めて受信回
数の最も多い受信データを優先して出力すると判定する
処理を行う。図13は受信入力データが3本の場合の優先
処理判定方法を表す優先処理状態遷移表を示し、図14は
其の単独受信と競合受信の場合の動作のフローチャート
を示す。同時受信検出部(3)にて、並列に3本の固定長
の同期式シリアルデータの受信データA,B,Cを単独
受信した場合は、先着データを優先して選択し其の処理
が終了するまで、他データの処理は待機させられる。並
列に3本の受信データA,B,Cの2つ以上3つを同時
に受信し競合受信となった場合は、図13の優先処理状態
遷移表に従う優先順位で受信データの出力処理を行う。
図13の優先処理状態遷移表について説明する。左端の
「状態」A,B,Cは、一番最近に処理をした状態の出
力の受信データであり、次の「入力データ」A,B,C は、
前記「状態」の後に入力する3個並列の受信データであ
り、〇印は受信有り、X印は受信無しを表す。次の「優
先データ」は、其の「入力データ」時に、前回の情報を
含めて平均的に受信回数が最も多く優先処理される受信
データであり、例えば前記「状態」がAで、「入力デー
タ」A,B,C が全て受信有り〇,〇,〇の競合受信の場合
には、「優先データ」は受信回数が最も多いA となる。
次の「出力後受信」A,B,C は「優先データ」の出力後の
3受信データであり、A がXで、B,C が共に〇印である
X,〇,〇であるので、其の状態(次状態)での前回情
報を含めた平均的に受信回数が最も多くて優先処理され
る受信データは B,Cとなる。そこで「次状態」の出力デ
ータとして、 B,Cの中の例えば Bを選択し「状態」Bに
移る。「状態」Bでの「入力データ」A,B,C が、夫々例
えばX,〇,〇であれば、「優先データ」は Bとなり、
次の「出力後受信」A,B,C が、夫々例えばX,X,〇で
あれば、「次状態」のデータとして受信データC が選択
され「状態」Cに移る。「状態」Cでの「入力データ」
A,B,C が、全て受信有りの〇,〇,〇であれば、「優先
データ」は Cとなり、次の「出力後受信」A,B,C が、夫
々例えば〇, 〇,Xであれば、「次状態」として受信デ
ータA が選択されて出力データとなる。この優先処理判
定方法により、同時に複数のデータが受信されて競合し
た場合には前回情報を含めて平均的に受信回数が最も多
い受信データを優先して出力するデータ処理を行うこと
が出来る。
Returning to FIG. 1, the detection result (4) of the simultaneous detection determination unit (2) and the information of the final processing data stored in the register of the control unit and output by priority processing at the time of the previous simultaneous reception detection. Thus, the priority processing determination unit (6) determines the priority processing of the received data. The determination method is a process of determining that the reception data having the largest number of receptions including the previous competition information stored in the register (5) is preferentially output. FIG. 13 shows a priority processing state transition table showing a priority processing determination method in the case of three pieces of received input data, and FIG. 14 shows a flowchart of operations in the case of single reception and contention reception. When the simultaneous reception detection unit (3) independently receives the reception data A, B, and C of three fixed-length synchronous serial data in parallel, the first-come-first-served data is selected and the processing ends. Until that is done, processing of other data is made to wait. When two or more of the three reception data A, B, and C are simultaneously received in parallel and the contention is received, the output processing of the reception data is performed in the priority order according to the priority processing state transition table of FIG.
The priority processing state transition table of FIG. 13 will be described. The "states" A, B, C on the left end are the received data of the output of the most recently processed state, and the next "input data" A, B, C are
It is three pieces of parallel received data input after the "state". The mark "O" indicates reception and the mark "X" indicates no reception. The next "priority data" is the reception data including the previous information and having the highest average number of receptions at the time of the "input data". For example, the "state" is A, and the "input data" is "input data". If all the data "A, B, C have been received, and there is a competitive reception of 0, 0, and 0, the" priority data "will be A with the highest number of receptions.
The next "reception after output" A, B, C are the three reception data after the output of "priority data". Since A is X and both B and C are ◯, X, 〇, 〇. In that state (next state), the received data including the previous information, which has the largest number of receptions on average and is preferentially processed, is B and C. Then, for example, B is selected from B and C as the output data of the "next state", and the state is shifted to the "state" B. If the “input data” A, B, C in the “state” B is, for example, X, 〇, 〇, respectively, the “priority data” is B,
If the next "reception after output" A, B, C is, for example, X, X, ◯, the received data C is selected as the "next state" data, and the "state" C is entered. "Input data" in "state" C
If A, B, C are all ◯, 〇, 〇 with reception, the “priority data” is C, and the next “reception after output” A, B, C is, for example, 〇, 〇, X respectively. If so, the received data A is selected as the "next state" and becomes the output data. By this priority processing determination method, when a plurality of data are received at the same time and conflict with each other, it is possible to perform the data processing in which the reception data including the previous information and having the largest average number of receptions is preferentially output.

【0008】図2は、本発明の請求項2に対応する競合
データ処理回路である。図1の制御部(7)において、レ
ジスタ(5)の代わりに、予め N本のデータの優先順位を
設定しておく優先処理設定部(11)を設け、其の設定情報
に従って、受信データの同時検出信号(4)を監視して、
優先処理判定部(6)にて競合データの出力処理の優先順
位の判定を行う。この様にして、優先処理設定部(11)に
て予め設定した優先順位で、競合データの出力処理を行
うことが出来る。
FIG. 2 shows a competing data processing circuit according to claim 2 of the present invention. In the control unit (7) of FIG. 1, instead of the register (5), a priority processing setting unit (11) for setting the priority of N data in advance is provided, and the received data of the received data is set according to the setting information. Monitor the simultaneous detection signal (4),
The priority processing determination unit (6) determines the priority of the competitive data output processing. In this way, the competitive data output process can be performed in the priority order preset by the priority process setting unit (11).

【0009】図3は、本発明の請求項3に対応する競合
データ処理回路である。図1の制御部(7)において、レ
ジスタ(5)の代わりに、外部入力の優先順位設定アドレ
スを制御するアドレスデコーダDEC と其の出力を保持す
るレジスタとから成るアドレス制御部(12)を設ける。ア
ドレス制御部(12)のアドレスデコーダDEC は、外部入力
の優先順位設定アドレスにより、優先処理の設定情報を
予め格納してあるレジスタのアドレスを生成する。レジ
スタには、優先処理設定情報を予め格納してあり、アド
レスデコーダDEC の出力により設定情報の読み出しを行
う。この読み出した情報により、競合する受信データの
優先処理の判定を制御部(7)の中の優先処理判定部(6)に
て行う。
FIG. 3 shows a competing data processing circuit according to claim 3 of the present invention. In the control unit (7) of FIG. 1, instead of the register (5), an address control unit (12) including an address decoder DEC that controls the priority setting address of the external input and a register that holds the output thereof is provided. . The address decoder DEC of the address control unit (12) generates an address of a register in which setting information for priority processing is stored in advance according to the priority setting address of the external input. Priority processing setting information is stored in advance in the register, and the setting information is read by the output of the address decoder DEC. Based on this read information, the priority processing determination unit (6) in the control unit (7) determines the priority processing of the competing received data.

【0010】図4は、本発明の請求項4に対応する競合
データ処理回路である。(3)同時受信検出部の中の N個
の受信パルス生成部(1)において、各受信データ別に固
定長の同期式シリアルデータを検出した後に、それぞれ
に番号を付加する番号付加部(13)を設ける。番号の付加
方法は、予め定めた優先順位に従って優先順位の高いも
のから順番に番号を付加する。但し番号の付加を行うデ
ータは、受信入力データから受信パルスOUT を検出した
受信データのみとし、其の付加された番号を基にして、
制御部(7)の中の優先処理判定部(6)にて優先順位の処理
を行い、競合する受信データの選択出力の処理を行う。
FIG. 4 shows a competing data processing circuit according to claim 4 of the present invention. (3) A number addition section (13) that adds a number to each of the reception pulse generation sections (1) in the simultaneous reception detection section after detecting fixed-length synchronous serial data for each reception data To provide. As a method of adding numbers, numbers are added in order from the highest priority according to a predetermined priority. However, the data to which the number is added is only the received data in which the received pulse OUT is detected from the received input data, and based on the added number,
The priority processing determination unit (6) in the control unit (7) performs priority processing, and performs selection output of conflicting received data.

【0011】図5は、本発明の請求項5に対応する競合
データ処理回路である。(3) 同時受信検出部に対し、受
信データの同時検出の判定を行う際に基準となる時間幅
(ウインドウW )を生成する同時検出ウインドウ生成部
(14)を設ける。この生成した同時検出ウインドウW を基
準として、受信パルス生成部(1) にて検出した受信パル
スOUT を監視して、受信データの同時検出の判定を行
い、其の判定結果を基に、制御部(7) およびメモリ部(1
0)で、競合データの処理を行う。この様にして、受信デ
ータの競合の起きる確率を変えることが可能となり、競
合データの処理に融通性を与えることが出来る。
FIG. 5 shows a competitive data processing circuit according to a fifth aspect of the present invention. (3) Simultaneous detection window generator that generates a reference time width (window W) when determining the simultaneous detection of received data for the simultaneous reception detector
(14) is provided. Using the generated simultaneous detection window W as a reference, the received pulse OUT detected by the received pulse generator (1) is monitored and the simultaneous detection of the received data is judged, and based on the judgment result, the controller (7) and memory section (1
In 0), the competition data is processed. In this way, it is possible to change the probability of occurrence of competition of received data, and it is possible to give flexibility to the processing of competition data.

【0012】図6は、本発明の請求項6に対応する競合
データ処理回路である。並列に複数N の受信データの全
てのクロックを、外部入力の非同期クロックに乗り換え
るクロック乗換え部(15)を設ける。クロック乗換え以後
の処理(同時受信検出部3 ,制御部7 ,メモリ部10)
は、乗り換えたクロックにより行うことにより、受信デ
ータのクロックに非同期の競合データの処理を行うこと
が出来ることになる。
FIG. 6 shows a competing data processing circuit according to claim 6 of the present invention. A clock transfer unit (15) is provided in parallel for transferring all the clocks of the plurality of N received data to the asynchronous clock of the external input. Processing after clock transfer (simultaneous reception detection unit 3, control unit 7, memory unit 10)
By performing with the changed clock, it becomes possible to process the competitive data asynchronous with the clock of the received data.

【0013】図7は、本発明の請求項7に対応する競合
データ処理回路である。受信データの全てを格納してお
く複数N のレジスタ(8)を、受信データの数N の整数M
倍だけ具え、制御部(7)の優先処理結果を基に、N x M
個のレジスタ(8)の内容を読み出す。この様にして、M
回連続して同じ受信データが競合した場合でも、N x M
個のレジスタ(8) の内容を読み出す事により、データの
競合を避ける処理が出来る。
FIG. 7 shows a competitive data processing circuit according to claim 7 of the present invention. Set multiple N registers (8) that store all the received data to the integer M of the received data number N.
Based on the priority processing result of the control unit (7), N x M
Read the contents of this register (8). In this way, M
Even if the same received data competes consecutively N times M
By reading the contents of each register (8), it is possible to avoid data conflict.

【0014】図8は、本発明の請求項8に対応する競合
データ処理回路である。回路の電源投入時に入力する初
期状態信号(初期リセット)により、初期状態での優先
順位の設定を行う初期リセット優先処理部(16)を設け、
初期リセット時のみ、優先順位を固定とする。この様に
して、電源投入時の競合データの処理動作を早く安定さ
せることが出来る。
FIG. 8 shows a competing data processing circuit according to claim 8 of the present invention. An initial reset priority processing unit (16) that sets the priority order in the initial state by the initial state signal (initial reset) input when the circuit power is turned on is provided.
Priority is fixed only at initial reset. In this way, the processing operation of competing data when the power is turned on can be stabilized quickly.

【0015】[0015]

【発明の効果】以上説明した如く、本発明によれば、並
列に複数の固定長の同期式シリアルデータの受信データ
をフレーム多重する等の通信処理において、複数のデー
タを同時に受信して競合した場合でも、出力として競合
が避けられるデータ処理が出来て、所要の通信処理を支
障無く行うことが出来る様になる効果が得られる。
As described above, according to the present invention, in communication processing such as frame multiplexing of received data of a plurality of fixed length synchronous serial data in parallel, a plurality of data are simultaneously received and competed. Even in such a case, it is possible to perform data processing in which contention can be avoided as output, and it is possible to perform the required communication processing without any trouble.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の請求項1の競合データ処理回路の構
成図
FIG. 1 is a configuration diagram of a competitive data processing circuit according to claim 1 of the present invention.

【図2】 本発明の請求項2の競合データ処理回路の構
成図
FIG. 2 is a configuration diagram of a competitive data processing circuit according to claim 2 of the present invention.

【図3】 本発明の請求項3の競合データ処理回路の構
成図
FIG. 3 is a configuration diagram of a competitive data processing circuit according to claim 3 of the present invention.

【図4】 本発明の請求項4の競合データ処理回路の構
成図
FIG. 4 is a configuration diagram of a competitive data processing circuit according to claim 4 of the present invention.

【図5】 本発明の請求項5の競合データ処理回路の構
成図
FIG. 5 is a configuration diagram of a competitive data processing circuit according to claim 5 of the present invention.

【図6】 本発明の請求項6の競合データ処理回路の構
成図
FIG. 6 is a configuration diagram of a competitive data processing circuit according to claim 6 of the present invention.

【図7】 本発明の請求項7の競合データ処理回路の構
成図
FIG. 7 is a configuration diagram of a competitive data processing circuit according to claim 7 of the present invention.

【図8】 本発明の請求項8の競合データ処理回路の構
成図
FIG. 8 is a configuration diagram of a competitive data processing circuit according to claim 8 of the present invention.

【図9】 本発明の競合データ処理回路の受信パルス生
成部の構成と動作の説明図
FIG. 9 is an explanatory diagram of a configuration and an operation of a reception pulse generation unit of the competition data processing circuit of the present invention.

【図10】 本発明の競合データ処理回路の同時受信検
出部の動作説明図
FIG. 10 is an operation explanatory diagram of the simultaneous reception detecting unit of the competitive data processing circuit of the present invention.

【図11】 本発明の実施例の同時検出判定部の構成図FIG. 11 is a configuration diagram of a simultaneous detection determination unit according to an embodiment of the present invention.

【図12】 本発明の実施例の同時受信検出部の同時受
信判定表とリードカウンタの構成の図
FIG. 12 is a diagram showing a configuration of a simultaneous reception determination table and a read counter of the simultaneous reception detector according to the embodiment of the present invention.

【図13】 本発明の実施例の優先処理判定部の動作を
説明するための優先処理状態遷移表の図
FIG. 13 is a diagram of a priority processing state transition table for explaining the operation of the priority processing determination unit according to the embodiment of this invention.

【図14】 本発明の実施例の処理動作のフローチャー
FIG. 14 is a flowchart of the processing operation of the embodiment of the present invention.

【図15】 従来のフレーム多重の為の受信データ制御
回路の構成例の図
FIG. 15 is a diagram of a configuration example of a conventional received data control circuit for frame multiplexing.

【符号の説明】[Explanation of symbols]

(1) は受信パルス生成部、(2) は同時検出判定部、(3)
は同時受信検出部、( 4)は同時受信の検出信号、(5) は
前回情報を保持するレジスタ、(6) は優先処理判定部、
(7) は制御部、(8) は並列に複数N の各レジスタであ
り、複数N の受信データを個別に格納する。(9)はデー
タ選択部(セレクタ) であり、複数N のレジスタ8 の出
力データの一つを選択して出力する。(10)はメモリ部で
あり、複数N のレジスタ(8) と一つのデータ選択部(9)
とから成る。
(1) is the received pulse generator, (2) is the simultaneous detection judgment unit, (3)
Is a simultaneous reception detection unit, (4) is a detection signal of simultaneous reception, (5) is a register that holds the previous information, (6) is a priority processing determination unit,
(7) is a control unit, and (8) is a plurality of N registers in parallel, and stores a plurality of N received data individually. (9) is a data selection unit (selector), which selects and outputs one of the output data of the plurality N of registers 8. (10) is a memory part, which has a plurality of N registers (8) and one data selection part (9)
Consisting of

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 並列に複数N の同じ固定長で同期式シリ
アルの受信データの全てを各受信データ別に格納するレ
ジスタと其の出力データの一つを選択するセレクタとか
ら成るメモリ部と、該複数N の受信データの幾つかが同
時受信され互に競合する状態を検出する同時受信検出部
と、該幾つかの受信データが競合する状態が検出された
場合には、前回の競合情報を保持しているレジスタ情報
を含めて平均的に受信回数の多い受信データを優先する
と判定する処理を行う制御部とを具え、其の制御部にお
ける優先処理の判定結果を前記メモリ部の出力データの
セレクタの選択信号として前記複数N のレジスタに格納
した受信データの一つを選択して、出力データとするこ
とを特徴とする競合データ処理回路。
1. A memory unit comprising, in parallel, a plurality of N registers for storing all received data of the same fixed length and synchronous serial for each received data, and a selector for selecting one of the output data. Simultaneous reception detection section that detects the state where some of the multiple N received data are simultaneously received and competes with each other, and if the state where some of the received data competes is detected, the previous competition information is retained. And a control unit that performs a process of determining that received data having a large number of receptions on average including register information is prioritized, and the determination result of the priority process in the control unit is used as a selector for the output data of the memory unit. The competitive data processing circuit is characterized in that one of the reception data stored in the plurality of N registers is selected as the selection signal and is used as output data.
【請求項2】 前記制御部におけるレジスタの代わり
に、予め複数Nの受信データの処理の優先順位を設定し
ておく優先処理設定部を設け、其の設定情報に従って該
受信データの同時受信の検出信号を監視し、前記優先処
理判定部にて競合データの処理の優先順位の判定を行う
ことを特徴とする請求項1記載の競合データ処理回路。
2. A priority processing setting section for presetting the processing priority of a plurality of N pieces of received data is provided in place of the register in the control section, and simultaneous reception of the received data is detected according to the setting information. 2. The competitive data processing circuit according to claim 1, wherein a signal is monitored and the priority processing determination unit determines the priority of processing of the competitive data.
【請求項3】 前記制御部におけるレジスタの代わり
に、外部入力の優先順位設定アドレスを制御するアドレ
スデコーダと其の出力を保持するレジスタとから成るア
ドレス制御部を設けたことを特徴とする請求項1記載の
競合データ処理回路。
3. An address control section comprising an address decoder for controlling a priority setting address of an external input and a register for holding the output thereof is provided in place of the register in the control section. 1. The competitive data processing circuit according to 1.
【請求項4】 前記同時受信検出部の中の複数Nの受信
パルス生成部にて各受信データの固定長の同期式シリア
ルデータを検出した後に、複数Nの受信データのそれぞ
れに、予め定めた優先順位の高いものから順番に番号を
付加する番号付加部を設け、其の付加した番号に従って
優先順位の高い受信データから順番に出力することを特
徴とする請求項1記載の競合データ処理回路。
4. The plurality of N reception pulse generators in the simultaneous reception detector detect fixed serial data of fixed length of each reception data, and then predetermined for each of the plurality N of reception data. 2. The competing data processing circuit according to claim 1, further comprising: a number adding unit for adding numbers in order from the highest priority, and receiving data in order from the highest priority received data according to the added numbers.
【請求項5】 前記同時受信検出部に対し、受信データ
の同時検出の判定を行う際に基準となる時間幅を生成す
る同時検出ウインドウ生成部を設け、その生成した同時
検出ウインドウを基準として前記受信パルス生成部にて
検出した受信パルス出力を監視し、受信データの同時検
出の判定を行うことを特徴とする請求項1記載の競合デ
ータ処理回路。
5. A simultaneous detection window generation unit is provided for the simultaneous reception detection unit, which generates a time width that serves as a reference when determining the simultaneous detection of received data, and the simultaneous detection window is used as a reference. 2. The competing data processing circuit according to claim 1, wherein the reception pulse output detected by the reception pulse generation unit is monitored and the simultaneous detection of reception data is determined.
【請求項6】 前記並列に複数N の受信データの全ての
クロックを、外部入力の非同期クロックに乗り換えるク
ロック乗換え部を設け、クロック乗換え以後の処理は、
乗り換えたクロックにより行うことを特徴とする請求項
1記載の競合データ処理回路。
6. A clock transfer unit for transferring all the clocks of a plurality N of received data in parallel to an asynchronous clock of an external input, and processing after the clock transfer is performed.
2. The competing data processing circuit according to claim 1, wherein the clock is changed.
【請求項7】 前記複数N の受信データの全てを個別に
格納しておく複数Nのレジスタを、受信データの数N の
整数M 倍だけ具え、前記制御部の優先処理結果を基に、
N x M 個のレジスタの内容を読み出すことを特徴とする
請求項1記載の競合データ処理回路。
7. The plurality of N registers for individually storing all of the plurality of N received data are provided by an integer M times the number N of received data, and based on the priority processing result of the control unit,
The contention data processing circuit according to claim 1, wherein the contents of N x M registers are read.
【請求項8】 電源投入時に入力する初期リセット信号
により、初期状態での優先順位の設定を行う初期リセッ
ト優先処理部を設け、電源投入時のみ、優先順位を固定
とすることを特徴とする請求項1記載の競合データ処理
回路。
8. An initial reset priority processing unit for setting a priority order in an initial state by an initial reset signal input when the power is turned on, and the priority order is fixed only when the power is turned on. The competitive data processing circuit according to Item 1.
JP7294173A 1995-11-13 1995-11-13 Contention data processing circuit Pending JPH09139757A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7294173A JPH09139757A (en) 1995-11-13 1995-11-13 Contention data processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7294173A JPH09139757A (en) 1995-11-13 1995-11-13 Contention data processing circuit

Publications (1)

Publication Number Publication Date
JPH09139757A true JPH09139757A (en) 1997-05-27

Family

ID=17804264

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7294173A Pending JPH09139757A (en) 1995-11-13 1995-11-13 Contention data processing circuit

Country Status (1)

Country Link
JP (1) JPH09139757A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6070216A (en) * 1998-01-29 2000-05-30 Mitsubishi Denki Kabushiki Kaisha Serial I/O multichannel semiconductor device capable of selecting a transmitting pin for data output and of detecting received data at a plurality of receiving pins
JP2004229287A (en) * 2003-01-18 2004-08-12 Samsung Electronics Co Ltd Method and system for allocating multiple-source to multiple-channel
JP2006094310A (en) * 2004-09-27 2006-04-06 Sony Corp Information processing apparatus, method, and program

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6070216A (en) * 1998-01-29 2000-05-30 Mitsubishi Denki Kabushiki Kaisha Serial I/O multichannel semiconductor device capable of selecting a transmitting pin for data output and of detecting received data at a plurality of receiving pins
JP2004229287A (en) * 2003-01-18 2004-08-12 Samsung Electronics Co Ltd Method and system for allocating multiple-source to multiple-channel
US7760768B2 (en) 2003-01-18 2010-07-20 Samsung Electronics Co., Ltd. System and method for allocating a plurality of sources to a plurality of channels
JP4662723B2 (en) * 2003-01-18 2011-03-30 三星電子株式会社 Method and system for assigning multiple sources to multiple channels
JP2006094310A (en) * 2004-09-27 2006-04-06 Sony Corp Information processing apparatus, method, and program

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