JPH09139665A - Input circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an input circuit device in a simple circuit form efficient for a base grounded input circuit and a gate grounded input circuit effective as the circuit of low power consumption by composing this circuit of a pair of control terminal grounded circuit consisting of transistors and constant current sources and phase change circuit. SOLUTION: When signals A and B are inputted to the input terminal of chip 1, differential signals from transistors Q11 and Q13 at the ECL output circuit of chip 1 are outputted. The differential signals are inputted to the base terminals of transistors Q17 and Q15 at the input circuit of chip 2 as signals C and D and after their potentials are lowered by transistors Q21 and Q22 for level shift, these signals are inputted to the emitter terminals of transistors Q15 and Q17 as signals E and F. Namely, the signals of phases opposite to the phases of signals inputted to the emitter terminals of transistors Q15 and Q17 at the input circuit are inputted to the base terminals of transistors Q15 and Q17. In this case, level shift circuits LS1 and LS2 are composed of diodes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output interface used for inputting / outputting signals between semiconductor devices or a signal input / output interface between a clock signal distribution circuit inside an IC and each partial circuit. The present invention relates to an input circuit in a circuit system that transmits a signal to a circuit such as a face, which has a long wiring length and a long load, and has a large load.

[0002]

In an interface used for inputting / outputting a signal in an ECL circuit or the like, an open emitter type circuit is generally used in a signal output section, and a signal input to this is used. An input circuit that terminates at a potential of -2V with a 50Ω terminating resistor was used in the section. The specifications of such an input / output circuit are determined by the voltage amplitude of the signal output section, and the high level and low level voltages of a normal signal are 1V.
The front and back are necessary. Therefore, the interface of the signal input / output part
Power consumption was extremely high on the face.

In order to avoid this, the signal input section is composed of a circuit for inputting a signal to the emitter terminal by using a base ground type circuit. Since such an input circuit can operate even if the voltage amplitude of the input signal is small, it has been conventionally proposed as a low power consumption interface.

Further, when a high speed signal such as a clock signal is distributed to each part inside a large-scale, high speed IC, the interface system based on the voltage amplitude has conventionally been adopted. The capacity and the capacity of the input circuit are I
It increases with the scale of C and the wiring length of the signal line,
As a result, the voltage amplitude of the signal is deteriorated and the wiring delay is increased.

As a method for avoiding such a problem, a high-speed transmission method has been proposed in which a signal is input to the emitter terminal of a base-ground type circuit which is a current sense type circuit. Such a method has been proposed as a new interface circuit in the past, but when the voltage generating circuit connected to the base terminal is unstable and tends to generate noise, it is possible to detect an input signal with a small voltage amplitude. The input circuit may malfunction. Therefore, it is necessary to use a highly stable voltage generation circuit for this voltage source.

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to provide an input circuit device of an efficient and simple circuit type, which is a base ground type input circuit or a gate ground type input circuit useful as a low power consumption circuit. To provide.

According to the present invention, each transistor has an individual control terminal (base or gate) and an individual charge injection terminal (emitter or source) to which the differential signals sent via the transmission line are respectively input. (A bipolar transistor or FET) and a pair of control terminal grounded circuits (base or gate grounded circuit) composed of a constant current source connected to a charge injection terminal of the transistor, and a pair of control terminal grounded circuits An input circuit device including a phase change circuit for inputting a differential signal to a charge injection terminal of a transistor of a pair of control terminal grounded circuits in a phase relationship opposite to the differential signal input to the control terminal of the transistor. Will be provided.

According to the present invention, each transistor has an individual control terminal (base or gate) and an individual charge injection terminal (emitter or source) to which the differential signals sent via the transmission line are respectively input. (Bipolar transistor or FET) and a pair of impedance matching elements (resistors) that are respectively connected to the charge injection terminals of the transistor and are set to values that match the characteristic impedance of the transmission line and the input impedance of the input circuit. The pair of control terminal grounded circuits and the differential signals input to the control terminals of the transistors of the pair of control terminal grounded circuits are provided with a differential signal in a reverse phase relationship. Input circuit device composed of phase change circuit for inputting to charge injection terminal of transistor It is provided.

According to the present invention, the first transistor (bipolar transistor or FET) having a control terminal (base or gate) to which a signal sent via the transmission line is input and a charge injection terminal (emitter or source). And a second transistor having a control terminal and a charge injection terminal (bipolar transistor or FE
T) and a pair of control terminal grounded circuits composed of a voltage source for applying a bias voltage to the control terminals of the second transistors and a constant current source connected to the charge injection terminals of the first and second transistors. And a signal introduction circuit that introduces a signal input to the control terminal of the first transistor to the charge injection terminal of the second transistor and guides the bias voltage of the voltage source to the charge injection terminal of the first transistor. An input circuit device is provided.

The phase changing circuit or the signal introducing circuit is the first
Between the base or gate of the second transistor and the emitter or source of the second transistor, and between the first level shift circuit and the base or gate of the second transistor and the emitter or source of the first transistor. It is composed of a second level shift circuit connected.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments will be described below with reference to the drawings. FIG. 1 shows an input / output circuit including an input circuit according to an embodiment of the present invention. According to this circuit, the bipolar transistors Q8 and Q9 whose base terminals are connected to the input terminals IN0 and IN1, respectively, form a differential circuit of the signal output circuit of the chip 1, and this differential circuit connects the power supply line Vcc1 and the ground line. Is connected in series to the constant current source I1. The bipolar transistors Q11 and Q13 form an open-emitter type ECL output circuit, and this ECL output circuit is a power supply line Vcc1.
And a transmission line, and outputs a signal to the input circuit of the chip 2 of the present invention via the transmission lines T1 and T2.

In the input circuit, the transistors Q11 and Q1 of the ECL output circuit are connected via the transmission lines T1 and T2.
3 has a charge injection terminal, that is, an emitter terminal, and bipolar transistors Q17 and Q1 forming a grounded base circuit.
5 control terminals, that is, base terminals are respectively connected.
Further, the emitter terminal of the transistor Q15 shifts the signal level, so that the diode-connected transistor Q21
Is connected to the transistor Q11 via the transmission line T1. Similarly, the emitter terminal of the transistor Q17 is connected to the level shift circuit LS2 including the diode-connected transistor Q22 for shifting the signal level, and is also connected to the transistor Q13 via the transmission line T2. That is, the base terminal of the transistor Q15 in the input circuit is connected to the transistor Q13 in the output circuit, and the emitter terminal is connected to the transistor Q11 via the transistor Q21. Similarly, the base terminal of the transistor Q17 of the input circuit is connected to the transistor Q11 of the output circuit of the chip 1, and the emitter terminal is connected to the transistor Q13 via the transistor Q22. Further, the emitter terminals of these transistors Q15 and Q17 are constant current sources I
2 and I3, respectively. Transistor Q1
The collectors of 5 and Q17 are connected to the power supply line Vcc2 via resistors R1 and R2, respectively, and are also connected to the output terminals OUT1 and OUT0, respectively.

The operation of the circuit having the above configuration will be described with reference to the timing chart of FIG. When the signals A and B are input to the input terminals of the chip 1, differential signals are output from the transistors Q11 and Q13 of the ECL output circuit of the chip 1. The differential signals are input as the signals C and D to the base terminals of the transistors Q17 and Q15 of the input circuit of the chip 2 via the transmission lines T1 and T2, respectively, and the potentials thereof are lowered by the level shift transistors Q21 and Q22. Transistors Q15 and Q1
Signals E and F are respectively input to the emitter terminal of 7. That is, the differential signals of the transistors Q11 and Q13 of the ECL output circuit are input to the base terminal and the emitter terminal of the transistor Q17 as signals C and F, respectively, and similarly, the signals E and D are input to the emitter terminal and the base terminal of the transistor Q15, respectively. Is entered. In other words, signals of opposite phase to the signals input to the emitter terminals of the transistors Q15 and Q17 of the input circuit are input to the base terminals of the transistors Q15 and Q17. As a result, the signals output to the charge collecting terminals of the transistors Q15 and Q17, that is, the collector terminals, have double the amplitude of the conventional input circuit under the condition that the load resistors R1 and R2 have the same value.

With reference to FIG. 3, the difference in frequency characteristic of voltage gain between the input circuit of the present invention shown in FIG. 1 and the conventional input circuit will be described. This frequency characteristic has input terminals IN0, I
When a signal is input to N1, output terminals OUT1 and OU
It is obtained by measuring the output signals G and H from T0. According to this, the input circuit characteristic A of the present invention is 6 dB higher in voltage gain than the characteristic B of the conventional circuit although the frequency band is not changed.

FIG. 4 shows a comparison of output signal amplitude characteristics of the input circuit of the present invention of FIG. 1 and the conventional input circuit.
This characteristic is also obtained by measuring in the same manner as in FIG.
According to this, while the characteristic B of the conventional circuit has an amplitude of 0.4 Vpp or less at the same power consumption, the characteristic A of the circuit of the present invention reaches nearly 0.8 Vpp. Further, while the waveform is distorted in the conventional input circuit, in the input circuit of the present invention, a good waveform in which the rising and falling waveforms are symmetrical is obtained.

In the above embodiment, the grounded base circuit is used for the input circuit, but a field grounded transistor, that is, a grounded gate circuit using FETs Q115 and Q117 may be used as shown in FIG. . In this case, the differential signals of the transistors Q11 and Q13 are the control terminals of the FET Q117 for the transistor Q11,
That is, the FET Q1 diode-connected to the gate terminal and the charge injection terminal of the FET Q115, that is, the source terminal.
21 is input to the control terminal of the FET Q115, that is, the gate terminal of the transistor Q13.
And a charge injection terminal of the FET Q117, that is, a source terminal, through a diode-connected FET Q122. In other words, the input circuit FETs Q115, Q1
The signal of the opposite phase to the signal input to the gate terminal of 17 is F
It is input to the gate terminals of ETQ115 and Q117. As a result, the output terminals OU connected to the charge collecting terminals of the FETs Q115 and Q117, that is, the drain terminals.
The signals output to T1 and OUT2 are load resistors R1 and
Under the condition that R2 has the same value, a double amplitude of the conventional input circuit can be obtained.

In the above embodiment, the grounded base circuit and the grounded gate circuit may be Darlington connection circuits. The level shift circuits LS1 and LS2 used in the input circuit of the embodiment shown in FIG. 1 may be configured by diodes D1 and D2 as shown in FIG. 6, and similarly, in the input circuit of the embodiment of FIG. The level shift circuits LS1 and LS2 used may be configured by diodes. Further, the level shift circuits LS1 and LS2 may be configured by resistors or level shift voltage sources.

In the above embodiment, the transmission line has two phases, but it may have a single phase as shown in the embodiment of FIG. In this case, the emitter of the transistor Q11 of the ECL output circuit of the chip 1 is connected to the transmission line T, but the emitter of the transistor Q13 is the constant current source I1 ′.
Connected to. In the chip 2, the transmission line T is connected to the base of the transistor Q17 of the base-grounded circuit and also to the emitter of the transistor Q15 via the diode D1 of the level shift circuit LS1. The base of the transistor Q15 is connected to the voltage source V0 and also connected to the emitter of the transistor Q17 via the diode D2 of the level shift circuit LS2.

According to the embodiment shown in FIG. 7, the signal output from the transistor Q11 of the ECL output circuit is input to the base of the transistor Q17 via the transmission line T and to the emitter of the transistor Q15 via the diode D1. Supplied. Since the base of the transistor Q15 and the emitter of the transistor 17 are biased with a constant voltage by the voltage source V0, when the input signal is at L (low) level, the transistor Q15 is turned on and the transistor Q17 is turned off. Therefore, the output terminal OUT
1 becomes L level, and the output terminal OUT0 becomes H (high) level. Next, when the input signal goes high, the transistor Q15 turns off and the transistor Q17 turns off.
N. As a result, the output terminal OUT1 becomes H level and the output terminal OUT0 becomes L level. Such an output corresponds to the output signals G and H in FIG.

In the above embodiment, the input impedance of the input circuit is such that the constant current sources I2 and I3 are replaced with low impedance elements such as resistors, or the transistor Q15,
By adjusting the transistor size of Q17, a circuit having a characteristic impedance substantially the same as that of the transmission lines T1 and T2 may be configured. In this case, reflection due to impedance mismatch at the input portion can be reduced.

Next, an embodiment for realizing the input impedance matching will be described with reference to FIG. In this embodiment, the characteristic impedance Zo of the transmission line and the impedance Zin of the input circuit of the chip 2 are matched.

According to this embodiment, the transmission lines T1, T2
Are connected to the bases of the bipolar transistors Q17 and Q15 of the grounded-base circuit, respectively, and the transistors Q15 and Q15 are connected via the diodes D1 and D2, respectively.
It is connected to the emitter of Q17, respectively. The collectors of the transistors Q15 and Q17 are connected to the power supply line Vcc2 via the resistors R1 and R2, and the emitters are connected to the ground line via the input impedance matching resistors R3 and R4. For impedance matching, the input impedance Zin needs to be Zin to Zo. However, Zo is the characteristic impedance of the transmission line. Zin is given by the following equation.

[0023]

(Equation 1)

However, Z _Q17b : input impedance of base terminal of transistor Q17 R _D1 : forward resistance of diode D1 Z _Q15e : input impedance of emitter terminal of transistor Q15 R _R3 : resistance value of resistor R3 According to the example, since the input impedance is matched in the transmission line and the input circuit, the power of the signal input to the input circuit is maximized and the distortion is extremely reduced. In this embodiment, the diode may be replaced with a diode-connected transistor, and the input circuit may be configured to be applicable to the single-phase transmission system as shown in FIG.

FIG. 9 shows an embodiment for realizing impedance matching in a single-phase transmission system. In this embodiment, the constant current sources I2 and I3 of the input circuit shown in FIG. 7 are replaced with the impedance matching resistors R3 and R4 shown in FIG.

[0026]

As described above, the use of the present invention eliminates the need for the complicated power supply generator required in the conventional input / output circuit, and doubles the signal waveform and the amplitude to improve the waveform. A circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a signal transmission system using an input circuit device according to an embodiment of the present invention.

FIG. 2 is a timing chart of signals at respective points of the input circuit of FIG.

FIG. 3 is a diagram showing voltage gain frequency characteristics of an input circuit device of the present invention and a conventional input circuit device.

FIG. 4 is a diagram showing voltage amplitude characteristics of an input circuit of the present invention and a conventional input circuit device.

FIG. 5 is a circuit diagram of a signal transmission system using an input circuit device including an FET according to another embodiment of the present invention.

FIG. 6 is a circuit diagram of a signal transmission system using an input circuit device using a diode, which is another embodiment of the present invention.

FIG. 7 is a circuit diagram of a signal transmission system using an input circuit device used in a single-phase transmission system according to another embodiment of the present invention.

FIG. 8 is a circuit diagram of a signal transmission system using an input circuit device having an input impedance matching function according to another embodiment of the present invention.

FIG. 9 is a circuit diagram of a signal transmission system using an input circuit device used in a single-phase transmission system having an input impedance matching function according to another embodiment of the present invention.

[Explanation of symbols]

 T1, T2 ... Transmission line Q15, Q17 ... Bipolar transistor Q21, Q22 ... Diode connected transistor Q115, Q116 ... FET Q121, Q122 ... Diode connected FET LS1, LS2 ... Level shift circuit I2, I3 ... Constant current source R1, R2 ... Resistor R3, R4 ... Resistors for impedance matching D1, D2 ... Diodes

Claims (7)

[Claims] 1. An individual transistor having an individual control terminal and an individual charge injection terminal to which a differential signal sent via a transmission line is respectively input, and a constant transistor connected to the charge injection terminal of the transistor. The pair of control terminal grounded circuits composed of a current source, and the differential signal having a reverse phase relationship with the differential signals respectively input to the control terminals of the transistors of the pair of control terminal grounded circuits. And a phase change circuit for respectively inputting to the charge injection terminals of the transistors of the pair of grounded control terminals circuits. 2. The pair of control terminal grounded circuits each have an individual bipolar to which each of the differential signals is input and which has an individual base corresponding to the control terminal and an individual emitter corresponding to the charge injection terminal. The input circuit device according to claim 1, wherein the input circuit device includes a pair of grounded base circuits each including a transistor. 3. The pair of control terminal grounded circuits each have an individual gate corresponding to the control terminal and an individual source corresponding to the charge injection terminal, to which the differential signals are respectively supplied. The input circuit device according to claim 1, wherein the input circuit device is constituted by a grounded-gate type circuit constituted by the field effect transistor. 4. The phase change circuit includes a first level shift circuit connected between one control terminal of the transistor and another charge injection terminal, the other control terminal of the transistor and the one charge. 2. A second level shift circuit connected between the injection terminal and the injection terminal.
4. The input circuit device according to any one of items 1 to 3. 5. An individual transistor having an individual control terminal and an individual charge injection terminal to which differential signals sent via a transmission line are respectively input, and each transistor is connected to the charge injection terminal of the transistor, A pair of control terminal grounded circuits configured by a pair of impedance matching elements set to a value that matches the characteristic impedance of the transmission line and the input impedance of the input circuit, and the pair of control terminal grounded circuits Phase change circuit for inputting the differential signals to the charge injection terminals of the transistors of the pair of control terminal grounded circuits in an opposite phase relationship to the differential signals input to the control terminals of the transistors. An input circuit device composed of and. 6. A first transistor having a control terminal to which a signal sent through a transmission line is input, a charge injection terminal, and a second transistor having a control terminal and a charge injection terminal, and the second transistor. A pair of control terminal grounded circuits, each of which includes a voltage source that applies a bias voltage to the control terminal of the transistor and a constant current source that is connected to the charge injection terminals of the first and second transistors; An introduction circuit for introducing the signal input to the control terminal of the first transistor to the charge injection terminal of the second transistor, and introducing the bias voltage of the voltage source to the charge injection terminal of the first transistor; An input circuit device configured by. 7. A pair of transistors, each having a control terminal to which a signal sent via a transmission line is input and a charge injection terminal, and a constant current source connected to the charge injection terminal of the transistor. A control terminal grounded circuit, and a signal level-shifted from a signal input to each of the control terminals of the transistors of the pair of control terminal grounded circuits, the charge of the transistor of the pair of control terminal grounded circuits. An input circuit device composed of a signal introduction circuit for inputting to each of the injection terminals.